The ICS503 is a member of the LOCO™ family,
the most cost effective way to generate a high
quality, high frequency clock output from a low
frequency crystal or clock input. The name LOCO
stands for LOw Cost Oscillator, as it is designed
to replace crystals and crystal oscillators in most
electronic systems. Using Phase-Locked-Loop
(PLL) techniques, the device uses a standard
fundamental mode, inexpensive crystal to produce
output clocks up to 160 MHz.
Stored in the chip’s ROM is the ability to generate
9 different multiplication factors, allowing one
chip to be used in two or three different
applications (see page 2).
Features
• Packaged as 8 pin SOIC or die
• ICS’ lowest cost PLL clock family
• Generates 16.9344 MHz for stereo codecs from
the 14.31818 MHz motherboard clock
• Can be cost effective in replacing a single
surface-mount crystal
• Can be driven by other 5xx series
• Input crystal frequency of 5 - 27 MHz
• Input clock frequency of 2 - 50 MHz
• Output clock frequencies up to 160 MHz
• Low jitter - 50 ps one sigma
• Duty cycle of 45/55 up to 160 MHz
• Operating voltages of 3.0 to 5.5V
• Full CMOS level outputs with 25mA drive
capability at TTL levels
Block Diagram
Crystal or
clock input
S0
S1
X1/ICLK
X2
VDD GND
Clock Multiplier
Crystal
Oscillator
Optional crystal capacitors
• Advanced, low power CMOS process
PLL
Output
Circuitry
and
ROM
Buffer
CLK
MDS 503 A1 Revision 111000
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose •CA•95126•(408) 295-9800tel • www.icst.com
Page 2
Pin Assignment
PRELIMINARY
PRELIMINARY
INFORMATION
INFORMATION
ICS503
LOCO™ PLL Clock Multiplier
X1/ICLK
VDD
GND
NC
18
2
3
4
X2
7
S1
6
S0
5
CLK
Clock Decoding Table (MHz)
S1S0Multiplier Typical Input (MHz) CLK (MHz) Input Range (MHz) at 5V Input Range (MHz) at 3.3V
0 = connect directly to ground, 1 = connect directly to VDD, M = leave unconnected (floating).
Pin Descriptions
NumberName TypeDescription
1X1/ICLKICrystal connection or clock input.
2VDDPConnect to +3.3V or +5V.
3GNDPConnect to ground.
4NC-Nothing is connected to this pin.
5CLKOClock output per Table above. Output frequency equals input frequency times multiplier.
6S0TISelect 0 for output clock. Connect to GND or VDD or float.
7S1TISelect 1 for output clock. Connect to GND or VDD or float.
8X2OCrystal connection. Leave unconnected for clock input.
Key: I = Input, TI = Tri-Level Input, O = output, P = power supply connection
MDS 503 A2 Revision 111000
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose •CA•95126•(408) 295-9800tel • www.icst.com
Page 3
PRELIMINARY
ABSOLUTE MAXIMUM RATINGS (stresses beyond these can permanently damage the device)
DC CHARACTERISTICS (VDD = 5.0V unless otherwise noted)
AC CHARACTERISTICS (VDD = 5.0V unless otherwise noted)
PRELIMINARY
INFORMATION
INFORMATION
ICS503
LOCO™ PLL Clock Multiplier
Electrical Specifications
ParameterConditionsMinimumTypicalMaximumUnits
Supply Voltage, VDDReferenced to GND7V
InputsReferenced to GND-0.5VDD+0.5V
Clock OutputReferenced to GND-0.5VDD+0.5V
Ambient Operating Temperature070°C
Soldering TemperatureMax of 10 seconds260°C
Storage temperature-65150°C
Input Frequency, crystal inputSee table on page 2527MHz
Input Frequency, clock inputSee table on page 2250MHz
Output FrequencyVDD = 4.5 to 5.5V14160MHz
Output FrequencyVDD = 3.0 to 3.6V14100MHz
Output Clock Rise Time0.8 to 2.0V1ns
Output Clock Fall Time2.0 to 0.8V1ns
Output Clock Duty Cycleat VDD/24549 to 5155%
Absolute Clock Period JitterDeviation from mean±120ps
One Sigma Clock Period Jitter50ps
MDS 503 A3 Revision 111000
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose •CA•95126•(408) 295-9800tel • www.icst.com
Page 4
PRELIMINARY
Inches
Millimeters
PRELIMINARY
INFORMATION
INFORMATION
ICS503
LOCO™ PLL Clock Multiplier
External Components / Crystal Selection
The ICS503 requires a 0.01µF decoupling capacitor to be connected between VDD and GND. It must be
connected close to the ICS503 to minimize lead inductance. No external power supply filtering is required
for this device. A 33Ω terminating resistor can be used next to the CLK pin. The total on-chip capacitance
is approximately 6 pF, so a parallel resonant, fundamental mode crystal should be used. If exact tuning of
the frequency is required, crystal capacitors should be connected from each of the pins X1 and X2 to
ground as shown in the Block Diagram on page 1. The value (in pF) of these crystal caps should be equal
to (CL-6)*2, where CL is the crystal load capacitance in pF. These external capacitors are only required for
applications where the exact frequency is critical. For a clock input, connect to X1 and leave X2
unconnected (no capacitors on either).
Package Outline and Package Dimensions
8 pin SOIC
EH
Q
Pin 1
e
D
h x 45°
A
c
b
SymbolMinMaxMinMax
A0.0550.0681.3971.7272
b0.0130.0190.3300.483
D0.1850.2004.6995.080
E0.1500.1603.8104.064
H0.2250.2455.7156.223
e
h0.0150.381
Q0.0040.010.1020.254
Ordering Information
Part/Order NumberMarkingPackageTemperature
ICS503MICS503M8 pin SOIC0-70°C
ICS503MTICS503M8 pin SOIC on tape and reel0-70°C
While the information presented herein has been checked for both accuracy and reliability, ICS/MicroClock assumes no responsibility for either its use or for the infringement of
any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not
recommended without additional processing by ICS/MicroClock. ICS/MicroClock reserves the right to change any circuitry or specifications without notice. ICS/MicroClock
does not authorize or warrant any ICS/MicroClock product for use in life support devices or critical medical instruments.
MDS 503 A4 Revision 111000
LOCO is a trademark of ICS
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose •CA•95126•(408) 295-9800tel • www.icst.com
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