Datasheet ICM 7556 Datasheet (FREI)

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Page 1

TLC556, TLC556Y

DUAL LinCMOS TIMERS

SLFS047B – FEBRUARY 1984 – REVISED SEPTEMBER 1997

Very Low Power Consumption ...2 mW Typ at VDD = 5 V

Capable of Operation in Astable Mode

CMOS Output Capable of Swinging Rail to Rail

High Output-Current Capability Sink 100 mA Typ Source 10 mA Typ

Output Fully Compatible With CMOS, TTL,

D, J, OR N PACKAGE

(TOP VIEW)

1 DISCH

1 THRES

1 CONT

1 RESET

1 OUT

1 TRIG

GND

1 2 3 4 5 6 7

13 12 11 10

9 8

2 DISCH 2 THRES 2 CONT 2 RESET 2 OUT 2 TRIG

and MOS

Low Supply Current Reduces Spikes During Output Transitions

Single-Supply Operation From 2 V to 15 V

Functionally interchangeable With the NE556; Has Same Pinout

description

The TLC556 series are monolithic timing circuits fabricated using the TI LinCMOS process, which provides full compatibility with CMOS, TTL, and MOS logic and operates at frequencies up to 2 MHz. Accurate time delays and oscillations are

1 CONT

1 RESET

1 OUT

FK PACKAGE

(TOP VIEW)

1 THRES

1 DISCH

3 2 1 20 19

4 5 6 7 8

910111213

2 DISCH

18 17 16 15 14

2 THRES NC 2 CONT NC 2 RESET

possible with smaller, less-expensive timing capacitors than the NE556 because of the high input impedance. Power consumption is low across the full range of power supply voltages.

Like the NE556, the TLC556 has a trigger level

NC–No internal connection

GND

1 TRIG

2 OUT

2 TRIG

approximately one-third of the supply voltage and a threshold level approximately two-thirds of the supply voltage. These levels can be altered by use of the control voltage terminal. When the trigger input falls below the trigger level, the flip-flop is set and the output goes high. If the trigger input is above the trigger level and the threshold input is above the threshold level, the flip-flop is reset and the output is low. The reset input can override all other inputs and can be used to initiate a new timing cycle. If the reset input is low, the flip-flop is reset and the output is low. Whenever the output is low, a low-impedance path is provided between the discharge terminal and ground.

While the CMOS output is capable of sinking over 100 mA and sourcing over 10 mA, the TLC556 exhibits greatly reduced supply-current spikes during output transitions. This minimizes the need for the large decoupling capacitors required by the NE556.

These devices have internal electrostatic-discharge (ESD) protection circuits that prevent catastrophic failures at voltages up to 2000 V as tested under MIL-STD-883C, Method 3015. However, care should be exercised in handling these devices, as exposure to ESD may result in degradation of the device parametric performance.

All unused inputs should be tied to an appropriate logic level to prevent false triggering. The TLC556C is characterized for operation from 0°C to 70°C. The TLC556I is characterized for operation from

–40°C to 85°C. The TLC556M is characterized for operation over the full military temperature range of –55°C to 125°C.

LinCMOS is a trademark of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

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Page 2

TLC556, TLC556Y

CHIP FORM

DUAL LinCMOS TIMERS

SLFS047B – FEBRUARY 1984 – REVISED SEPTEMBER 1997

AVAILABLE OPTIONS

RANGE

O°C

70°C

–4O°C

85°C

–55°C

125°C

The D package is available taped and reeled. Add the suffix R to the device type (e.g., TLC556CDR).

†

RANGE

2 V

18 V

3 V

18 V

5 V

18 V

RESET

VOLTAGE

< MIN Irrelevant Irrelevant L On

> MAX < MIN Irrelevant H Off

>MAX >MAX >MAX L On

> MAX > MAX < MIN As previously established

For conditions shown as MIN or MAX, use the appropriate value specified under electrical characteristics.

SMALL OUTLINE

(D)

TLC556CD TLC556CN TLC556Y

TLC556lD TLC556IN

TLC556MD TLC556MFK TLC556MJ TLC556MN

†

TRIGGER

VOLTAGE

CHIP CARRIER

FUNCTION TABLE

†

PACKAGE

(FK)

THRESHOLD

VOLTAGE

†

CERAMIC DIP

(J)

OUTPUT

PLASTIC DIP

(N)

DISCHARGE

SWITCH

(Y)

functional block diagram (each timer)

CONT

THRES

TRIG

RESET can override TRIG and THRES. TRIG can override THRES.

Pin numbers shown are for the D, J, or N packages.

GND

RESET

R1 RS1

OUT

DISCH

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Page 3

TLC556, TLC556Y

DUAL LinCMOS TIMERS

SLFS047B – FEBRUARY 1984 – REVISED SEPTEMBER 1997

TLC556Y chip information

These chips, properly assembled, display characteristics similar to the TLC556 (see electrical table). Thermal compression or ultrasonic bonding may be used on the doped aluminum bonding pads. Chips may be mounted with conductive epoxy or a gold-silicon preform.

BONDING PAD ASSIGNMENTS

CHIP THICKNESS: 15 TYPICAL BONDING PADS: 4 × 4 MINIMUM TJ max = 150°C

TOLERANCES ARE ±10% ALL DIMENSIONS ARE IN MILS NO BACKSIDE METALLIZATION PIN (7) INTERNALLY CONNECTED

TO BACKSIDE OF CHIP

THRESH

TRIG

FUNCTIONAL BLOCK DIAGRAM (EACH TIMER)

(2)

(6)

(14)

GND

CONT

(7)

(3)

RESET

(4)

R1 RS1

(5)

(1)

OUT

DISCH

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Page 4

TLC556, TLC556Y DUAL LinCMOS TIMERS

SLFS047B – FEBRUARY 1984 – REVISED SEPTEMBER 1997

absolute maximum ratings over operating free-air temperature (unless otherwise noted)

TLC556C TLC556I TLC556M UNIT

Supply voltage, VDD (see Note 1) 18 18 18 V Input voltage range, V Sink current, discharge or output 150 150 150 mA Source current, output 15 15 15 mA Continuous total power dissipation See Dissipation Rating Table Operating free-air temperature range 0 to 70 –40 to 85 –55 to 125 °C Storage temperature range –65 to 150 –65 to 150 –65 to 150 °C Case temperature for 60 seconds FK package 260 Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds J package 300 Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds D or N package 260 260

NOTE 1: All voltage values are with respect to network ground terminal.

PACKAGE

DISSIPATION RATING TABLE

TA ≤ 25°C

POWER RATING

950 mW

1375 mW 1375 mW 1150 mW

DERATING FACTOR

ABOVE TA = 25°C

7.6 mW/°C

11.0 mW/°C

9.2 mW/°C

TA = 70°C

POWER RATING

608 mW 880 mW 880 mW 736 mW

–0.3 to V

TA = 85°C

POWER RATING

494 mW 715 mW 715 mW 598 mW

–0.3 to V

TA = 125°C

POWER RATING

N/A 275 mW 275 mW

N/A

°C

recommended operating conditions

Supply voltage, V

Operating free-air temperature range, T

MIN MAX UNIT

2 15 V TLC556C 0 70 TLC556I –40 85 °C TLC556M –55 125

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Page 5

PARAMETER

†

UNIT

VITInput threshold voltage

Threshold current

Trigger voltage

Trigger current

Reset voltage

Reset current

VOHHigh-level output voltage

300 µA

VOLLow-level output voltage

IDDSupply current

See Note 2

TLC556, TLC556Y

DUAL LinCMOS TIMERS

SLFS047B – FEBRUARY 1984 – REVISED SEPTEMBER 1997

electrical characteristics at specified free-air temperature, VDD = 2 V for TLC556C, VDD = 3 V for TLC556I

TEST

CONDITIONS

(trigger)

(reset)

Control voltage (open circuit) as a percentage of supply voltage

Discharge switch on-state voltage

Discharge switch off-state current

†

Full range is 0°C to 70°C for TLC556C and –40°C to 85°C for TLC556I.

NOTE 2: These values apply for the expected operating configurations in which THRES is connected directly to DISCH or TRIG.

= 1

= –

= 1

25°C 0.95 1.33 1.65 1.6 2 2.4

Full range 0.85 1.75 1.5 2.5

25°C 10 10 MAX 75 150 25°C 0.4 0.67 0.95 0.71 1 1.29

Full range 0.3 1.05 0.61 1.39

25°C 10 10 MAX 75 150 25°C 0.4 1.1 1.5 0.4 1.1 1.5

Full range 0.3 1.8 0.3 1.8

25°C 10 10 MAX 75 150

MAX 66.7% 66.7% 25°C 0.04 0.2 0.03 0.2

Full range 0.25 0.375

25°C 0.1 0.1 MAX 0.5 120 25°C 1.5 1.9 1.5 1.9

Full range 1.5 2.5

25°C 0.07 0.3 0.07 0.3

Full range 0.35 0.4

25°C 130 500 130 500

Full range 800 1000

TLC556C TLC556I

MIN TYP MAX MIN TYP MAX

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Page 6

TLC556, TLC556Y

PARAMETER

†

UNIT

Tri

10 mA

1 mA

8 mA

5 mA

3.2 mA

IDDSupply current

See Note 2

µA

DUAL LinCMOS TIMERS

SLFS047B – FEBRUARY 1984 – REVISED SEPTEMBER 1997

electrical characteristics at specified free-air temperature, VDD = 5 V

TEST

CONDITIONS

(trigger)

(reset)

†

Full range is 0

NOTE 2: These values apply for the expected operating configurations in which THRES is connected directly to DISCH or to TRIG.

Input threshold voltage

reshold curren

gger voltage

gger curren

eset voltage

eset curren

Control voltage (open circuit) as a percentage of supply voltage

Discharge switch on-state voltage

Discharge switch off-state current

High-level output voltage

Low-level output voltage

= –

°C to 70°C for TLC556C, –40°C to 85°C for TLC556I, and –55°C to 125°C for TLC556M.

25°C 2.8 3.3 3.8 2.8 3.3 3.8 2.8 3.3 3.8

Full range 2.7 3.9 2.7 3.9 2.7 3.9

25°C 10 10 10 MAX 75 150 5000 25°C 1.36 1.66 1.96 1.36 1.66 1.96 1.36 1.66 1.96

Full range 1.26 2.06 1.26 2.06 1.26 2.06

25°C 10 10 10 MAX 75 150 5000 25°C 0.4 1.1 1.5 0.4 1.1 1.5 0.4 1.1 1.5

Full range 0.3 1.8 0.3 1.8 0.3 1.8

25°C 10 10 10 MAX 75 150 5000

MAX 66.7% 66.7% 66.7%

25°C 0.15 0.5 0.15 0.5 0.15 0.5

Full range 0.6 0.6 0.6

25°C 0.1 0.1 0.1 MAX 0.5 2 120 25°C 4.1 4.8 4.1 4.8 4.1 4.8

Full range 4.1 4.1 4.1

25°C 0.21 0.4 0.21 0.4 0.21 0.4

Full range 0.5 0.5 0.6

25°C 0.13 0.3 0.13 0.3 0.13 0.3

Full range 0.4 0.4 0.45

25°C 0.08 0.3 0.08 0.3 0.08 0.3

Full range 0.35 0.35 0.4

25°C 340 700 340 700 340 700

Full range 1000 1200 1400

TLC556C TLC556I TLC556M

MIN TYP MAX MIN TYP MAX MIN TYP MAX

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Page 7

PARAMETER

†

UNIT

VITInput threshold voltage

Threshold current

Trigger voltage

Trigger current

Reset voltage

Reset current

100 mA

10 mA

5 mA

1 mA

100 mA

50 mA

10 mA

IDDSupply current

See Note 2

DUAL LinCMOS TIMERS

SLFS047B – FEBRUARY 1984 – REVISED SEPTEMBER 1997

electrical characteristics at specified free-air temperature, VDD = 15 V

TEST

CONDITIONS

(trigger)

(reset)

Control voltage (open circuit) as a percentage of supply voltage

Discharge switch onstate voltage

Discharge switch offstate current

†

Full range is 0

NOTE 2: These values apply for the expected operating configurations in which THRES is connected directly to DISCH or TRIG.

High-level output voltage

Low-level output voltage

°C to 70°C for TLC556C, –40°C to 85°C for TLC556I, and –55°C to 125°C for TLC556M.

= –

25°C

Full range 9.35 10.65 9.35 10.65 9.35 10.65

25°C

MAX 75 150 5000

25°C

Full range 4.55 5.45 4.55 5.45 4.55 5.45

25°C

MAX 75 150 5000

25°C

Full range 0.3 1.8 0.3 1.8 0.3 1.8

25°C

MAX 75 150 5000

MAX 66.7% 66.7% 66.7%

25°C

Full range 1.8 1.8 1.8

25°C

MAX 0.5 2 120

25°C

Full range 12.5 12.5 12.5

25°C

Full range 13.5 13.5 13.5

25°C

Full range 14.2 14.2 14.2

25°C

Full range 3.6 3.7 3.8

25°C

Full range 1.3 1.4 1.5

25°C

Full range 0.4 0.4 0.45

25°C

Full range 1.6 1.8 2

TLC556C TLC556I TLC556M

MIN TYP MAX MIN TYP MAX MIN TYP MAX

9.45 10 10.55 9.45 10 10.55 9.45 10 10.55

10 10 10

4.65 5 5.35 4.65 5 5.35 4.65 5 5.35

10 10 10

0.4 1.1 1.5 0.4 1.1 1.5 0.4 1.1 1.5

10 10 10

0.8 1.7 0.8 1.7 0.8 1.7

0.1 0.1 0.1

12.5 14.2 12.5 14.2 12.5 14.2

13.5 14.6 13.5 14.6 13.5 14.6

14.2 14.9 14.2 14.9 14.2 14.9

1.28 3.2 1.28 3.2 1.28 3.2

0.63 1 0.63 1 0.63 1

0.12 0.3 0.12 0.3 0.12 0.3

0.72 1.2 0.72 1.2 0.72 1.2

TLC556, TLC556Y

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Page 8

TLC556, TLC556Y

DUAL LinCMOS TIMERS

SLFS047B – FEBRUARY 1984 – REVISED SEPTEMBER 1997

electrical characteristics, V

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

(trigger)

(reset)

NOTE 2: These values apply for the expected operating configurations in which THRES is connected directly to DISCH or TRIG.

Input threshold voltage 2.8 3.3 3.8 V Threshold current 10 pA Trigger voltage 1.36 1.66 1.96 V Trigger current 10 pA Reset voltage 0.4 1.1 1.5 V Reset current 10 pA Discharge switch on-state voltage IOL = 10 mA 0.15 0.5 V Discharge switch off-state current 0.1 nA High-level output voltage IOH = –1 mA 4.1 4.8 V

Low-level output voltage

Supply current See Note 2 3.40 700 µA

= 5 V, TA = 25°C

IOL = 8 mA 0.21 0.4 IOL = 5 mA IOL = 2.1 mA 0.08 0.3

0.13 0.3

operating characteristics, VDD = 5 V, TA = 25°C (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Initial error of timing interval Supply voltage sensitivity of timing interval

Output pulse rise time

Output pulse fall time

Maximum frequency in astable mode

max

†

Timing interval error is defined as the difference between the measured value and the average value of a random sample from each process run.

NOTE 3: RA, RB, and CT are as defined in Figure 3.

†

VDD = 5 V to 15 V, RA = RB = 1 kΩ to 100 kΩ 1% 3% CT = 0.1 µF, See Note 3 0.1 0.5 %/V

= 10 MΩ,

RA = 470 Ω, CT = 200 pF,

= 10

RB = 200 Ω, See Note 3

1.2 2.1 MHz

20 75 15 60

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Page 9

TLC556, TLC556Y

DUAL LinCMOS TIMERS

SLFS047B – FEBRUARY 1984 – REVISED SEPTEMBER 1997

TYPICAL CHARACTERISTICS

PROPAGATION DELAY TIMES (TO DISCHARGE

OUTPUT FROM TRIGGER AND THRESHOLD

SHORTED TOGETHER)

DISCHARGE SWITCH ON-STATE RESISTANCE

FREE-AIR TEMPERATURE

100

Ω

VDD = 2 V, IO = 1 mA

SUPPLY VOLTAGE

600

500

≥ 1 mA

O(on)

CL ≈ 0 TA = 25°C

Discharge Switch On-State Resistance –

–75 –50 –25 0 25 75 125

TA – Free-Air Temperature – °C

VDD = 5 V, IO = 10 mA

VDD = 15 V, IO = 100 mA

50 100

Figure 1

400

300

PLH

PHL

‡

200

PLH

t – Propagation Delay Times – ns

100

PHL

0 2 4 6 8 12 16

VDD – Supply Voltage – V

‡

The effects of the load resistance on these values must be taken into account separately.

10 14

Figure 2

2018

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Page 10

TLC556, TLC556Y DUAL LinCMOS TIMERS

SLFS047B – FEBRUARY 1984 – REVISED SEPTEMBER 1997

APPLICATION INFORMATION

0.1 µF

Connecting the trigger input to the threshold input, as shown in Figure 3, causes the timer to run as a multivibrator. The capacitor C V

The output is high during the charging cycle (tH) and low during the discharge cycle (tL). The duty cycle is controlled by the values of RA, and RB, and CT, as shown in the equations below.

0.1 µF

CONT V

RESET

TLC556

DISCH

THRES TRIG

CIRCUIT TRIGGER AND THRESHOLD VOLTAGE WAVEFORM

) and then discharges through RB only to the value of the trigger voltage level (approximately 0.33 VDD).

tH[

CT(RA)

GND

OUT

Output

Figure 3. Astable Operation

charges through RA and RB to the threshold voltage level (approximately 0.67

RB) In 2 (In 2+0.693)

2/3 V

1/3 V

GND

PHL

PLH

tL[

CTRBIn 2

Period+tH)

Output driver duty cycle

Output waveform duty cycle

The 0.1-µF capacitor at CONT in Figure 3 decreases the period by about 10%. The formulas shown above do not allow for any propagation delay from the trigger and threshold inputs to the

discharge output. These delay times add directly to the period and create differences between calculated and actual values that increase with frequency . In addition, the discharge output resistance r another source of error in the calculation when RB is very low or ron is very high.

The equations below provide better agreement with measured values.

tH+

tL+

CT(RA)

CT(RB)

tL[

CT(RA)

tH)

RB)Inƪ3*exp

ron)Inƪ3*exp

2RB)In2

tH)

[1*

[

CT(RB)

CT(RA)

RA)

PLH

PHL

ron)

RB)

adds to RB to provide

)

PHL

)

PLH

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Page 11

TLC556, TLC556Y

DUAL LinCMOS TIMERS

SLFS047B – FEBRUARY 1984 – REVISED SEPTEMBER 1997

APPLICATION INFORMATION

The preceding equations and those given earlier are similar in that a time constant is multiplied by the logarithm of a number or function. The limit values of the logarithmic terms must be between In 2 at low frequencies and In 3 at extremely high frequencies. For a duty cycle close to 50%, an appropriate constant for the logarithmic

terms can be substituted with good results. Duty cycles less than 50% possibly RA ≤ ron. These conditions can be difficult to obtain.

In monostable applications, the trip point of the trigger input can be set by a voltage applied to CONT. An input voltage between 10% and 80% of the supply voltage from a resistor divider with at least 500-µA bias provides good results.

tH)

will require that

< 1 and

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Page 12

TLC556, TLC556Y DUAL LinCMOS TIMERS

SLFS047B – FEBRUARY 1984 – REVISED SEPTEMBER 1997

MECHANICAL INFORMATION

D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

14 PIN SHOWN

0.069 (1,75) MAX

0.050 (1,27)

0.020 (0,51)

0.014 (0,35)

0.010 (0,25)

0.004 (0,10)

0.010 (0,25)

0.157 (4,00)

0.150 (3,81)

0.244 (6,20)

0.228 (5,80)

Seating Plane

0.004 (0,10)

PINS **

DIM

A MAX

A MIN

0.008 (0,20) NOM

Gage Plane

0°–8°

0.197

(5,00)

0.189

(4,80)

0.344 (8,75)

0.337 (8,55)

0.010 (0,25)

0.044 (1,12)

0.016 (0,40)

4040047/D 10/96

0.394

(10,00)

0.386

(9,80)

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15). D. Falls within JEDEC MS-012

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Page 13

TLC556, TLC556Y

DUAL LinCMOS TIMERS

SLFS047B – FEBRUARY 1984 – REVISED SEPTEMBER 1997

MECHANICAL INFORMATION

FK (S-CQCC-N**) LEADLESS CERAMIC CHIP CARRIER

28 TERMINAL SHOWN

A SQ

B SQ

12826 27

1314151618 17

0.020 (0,51)

0.010 (0,25)

MIN

0.342 (8,69)

0.442

0.640

0.739

0.938

1.141

0.358 (9,09)

0.458

(11,63)

0.660

(16,76)

0.761

(19,32)(18,78)

0.962

(24,43)

1.165

(29,59)

NO. OF

TERMINALS

432

0.020 (0,51)

0.010 (0,25)

(11,23)

(16,26)

(23,83)

(28,99)

MINMAX

0.307 (7,80)

0.406

(10,31)

0.495

(12,58)

0.495

(12,58)

0.850 (21,6)

1.047 (26,6)

0.080 (2,03)

0.064 (1,63)

MAX

0.358 (9,09)

0.458

(11,63)

0.560

(14,22)

0.560

(14,22)

0.858 (21,8)

1.063 (27,0)

0.055 (1,40)

0.045 (1,14)

0.028 (0,71)

0.022 (0,54)

0.050 (1,27)

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice. C. This package can be hermetically sealed with a metal lid. D. The terminals are gold plated. E. Falls within JEDEC MS-004

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0.045 (1,14)

0.035 (0,89)

0.045 (1,14)

0.035 (0,89)

4040140/D 10/96

Page 14

TLC556, TLC556Y DUAL LinCMOS TIMERS

SLFS047B – FEBRUARY 1984 – REVISED SEPTEMBER 1997

MECHANICAL INFORMATION

J (R-GDIP-T**) CERAMIC DUAL-IN-LINE PACKAGE

14 PIN SHOWN

0.065 (1,65)

0.045 (1,14)

0.100 (2,54)

0.070 (1,78)

0.020 (0,51) MIN

0.200 (5,08) MAX

PINS **

DIM

A MAX

A MIN

B MAX

B MIN

C MAX

C MIN

Seating Plane

0.310

(7,87)

0.290

(7,37)

0.785

(19,94)

0.755

(19,18)

0.280 (7,11)

0.245

(6,22)

0.310

(7,87)

0.290

(7,37)

0.785

(19,94)

0.755

(19,18)

0.300

(7,62)

0.245

(6,22)

181614

0.310

(7,87)

0.290

(7,37)

0.910

(23,10)

0.300

(7,62)

0.245

(6,22)

0.310

(7,87)

0.290

(7,37)

0.975

(24,77)

0.930

(23,62)

0.300

(7,62)

0.245

(6,22)

0.130 (3,30) MIN

0.100 (2,54)

0.023 (0,58)

0.015 (0,38)

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice. C. This package can be hermetically sealed with a ceramic lid using glass frit. D. Index point is provided on cap for terminal identification only on press ceramic glass frit seal only. E. Falls within MIL-STD-1835 GDIP1-T14, GDIP1-T16, GDIP1-T18, and GDIP1-T20

0°–15°

0.014 (0,36)

0.008 (0,20) 4040083/C 08/96

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Page 15

TLC556, TLC556Y

DUAL LinCMOS TIMERS

SLFS047B – FEBRUARY 1984 – REVISED SEPTEMBER 1997

MECHANICAL INFORMATION

N (R-PDIP-T**) PLASTIC DUAL-IN-LINE PACKAGE

16 PIN SHOWN

0.035 (0,89) MAX

PINS **

DIM

0.260 (6,60)

0.240 (6,10)

0.070 (1,78) MAX

0.020 (0,51) MIN

0.200 (5,08) MAX

A MAX

A MIN

Seating Plane

0.775

(19,69)

0.745

(18,92)

0.775

(19,69)

0.745

(18,92)

0.920

(23.37)

0.850

(21.59)

0.975

(24,77)

0.940

(23,88)

0.310 (7,87)

0.290 (7,37)

0.100 (2,54)

0.021 (0,53)

0.015 (0,38)

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice. C. Falls within JEDEC MS-001 (20 pin package is shorter then MS-001.)

0.010 (0,25)

0.125 (3,18) MIN

0°–15°

0.010 (0,25) NOM

14/18 PIN ONL Y

4040049/C 08/95

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Page 16

PACKAGE OPTION ADDENDUM

www.ti.com

29-May-2007

PACKAGING INFORMATION

Orderable Device Status

(1)

Package

Type

Package Drawing

Pins Package

Qty

Eco Plan

5962-89503022A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type

5962-8950302CA ACTIVE CDIP J 14 1 TBD A42 SNPB N / A for Pkg Type

TLC556CD ACTIVE SOIC D 14 50 Green (RoHS &

no Sb/Br)

TLC556CDG4 ACTIVE SOIC D 14 50 Green (RoHS &

no Sb/Br)

TLC556CDR ACTIVE SOIC D 14 2500 Green (RoHS &

no Sb/Br)

TLC556CDRG4 ACTIVE SOIC D 14 2500 Green (RoHS &

no Sb/Br)

TLC556CN ACTIVE PDIP N 14 25 Pb-Free

TLC556CNE4 ACTIVE PDIP N 14 25 Pb-Free

TLC556ID ACTIVE SOIC D 14 50 Green (RoHS &

no Sb/Br)

TLC556IDG4 ACTIVE SOIC D 14 50 Green (RoHS &

no Sb/Br)

TLC556IDR ACTIVE SOIC D 14 2500 Green (RoHS &

no Sb/Br)

TLC556IDRG4 ACTIVE SOIC D 14 2500 Green (RoHS &

no Sb/Br)

TLC556IN ACTIVE PDIP N 14 25 Pb-Free

TLC556INE4 ACTIVE PDIP N 14 25 Pb-Free

TLC556MD ACTIVE SOIC D 14 50 TBD CU NIPDAU Level-1-220C-UNLIM

TLC556MDR NRND SOIC D 14 2500 TBD CU NIPDAU Level-1-220C-UNLIM

TLC556MFKB ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type

TLC556MJ ACTIVE CDIP J 14 1 TBD A42 SNPB N / A for Pkg Type

TLC556MJB ACTIVE CDIP J 14 1 TBD A42 SNPB N / A for Pkg Type

TLC556MN OBSOLETE PDIP N 14 TBD Call TI Call TI

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.

(RoHS)

(2)

Lead/Ball Finish MSL Peak Temp

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU N / A for Pkg Type

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU N / A for Pkg Type

(3)

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

Addendum-Page 1

Page 17

PACKAGE OPTION ADDENDUM

www.ti.com

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

29-May-2007

Addendum-Page 2

Page 18

PACKAGE MATERIALS INFORMATION

www.ti.com

23-May-2007

TAPE AND REEL INFORMATION

Pack Materials-Page 1

Page 19

PACKAGE MATERIALS INFORMATION

www.ti.com

Device Package Pins Site Reel

Diameter

(mm)

TLC556CDR D 14 TAI 330 16 6.5 9.0 2.5 8 16 Q1 TLC556CDR D 14 FMX 330 0 6.5 9.0 2.5 8 16 Q1

TLC556IDR D 14 TAI 330 16 6.5 9.0 2.5 8 16 Q1 TLC556IDR D 14 FMX 330 0 6.5 9.0 2.5 8 16 Q1

Reel

Width

(mm)

A0 (mm) B0 (mm) K0 (mm) P1

(mm)W(mm)

23-May-2007

Pin1

Quadrant

TAPE AND REEL BOX INFORMATION

Device Package Pins Site Length (mm) Width (mm) Height (mm)

TLC556CDR D 14 TAI 346.0 346.0 33.0 TLC556CDR D 14 FMX 342.9 336.6 28.58

TLC556IDR D 14 TAI 346.0 346.0 33.0 TLC556IDR D 14 FMX 342.9 336.6 28.58

Pack Materials-Page 2

Page 20

PACKAGE MATERIALS INFORMATION

www.ti.com

23-May-2007

Pack Materials-Page 3

Page 21

Page 22

MECHANICAL DATA

MLCC006B – OCTOBER 1996

FK (S-CQCC-N**) LEADLESS CERAMIC CHIP CARRIER

28 TERMINAL SHOWN

A SQ

B SQ

12826 27

1314151618 17

0.020 (0,51)

0.010 (0,25)

MIN

0.342 (8,69)

0.442

0.640

0.739

0.938

1.141

0.358 (9,09)

0.458

(11,63)

0.660

(16,76)

0.761

(19,32)(18,78)

0.962

(24,43)

1.165

(29,59)

NO. OF

TERMINALS

432

0.020 (0,51)

0.010 (0,25)

(11,23)

(16,26)

(23,83)

(28,99)

MINMAX

0.307 (7,80)

0.406

(10,31)

0.495

(12,58)

0.495

(12,58)

0.850 (21,6)

1.047 (26,6)

0.080 (2,03)

0.064 (1,63)

MAX

0.358 (9,09)

0.458

(11,63)

0.560

(14,22)

0.560

(14,22)

0.858 (21,8)

1.063 (27,0)

0.055 (1,40)

0.045 (1,14)

0.028 (0,71)

0.022 (0,54)

0.050 (1,27)

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice. C. This package can be hermetically sealed with a metal lid. D. The terminals are gold plated. E. Falls within JEDEC MS-004

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

0.045 (1,14)

0.035 (0,89)

0.045 (1,14)

0.035 (0,89)

4040140/D 10/96

Page 23

Page 24

Page 25

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