Datasheet ICM7242 Datasheet (Intersil Corporation)

Page 1
ICM7242
November 1996
Features
• Replaces the 2242 in Most Applications
• Timing From Microseconds to Days
• Cascadable
• Wide Supply Voltage Range . . . . . . . . . . . . . . 2V to 16V
• Low Supply Current. . . . . . . . . . . . . . . . . . . 115µA at 5V
Ordering Information
PART NUMBER
(BRAND)
ICM7242IPA -25 to 85 8 Ld PDIP E8.3 ICM7242CBA
(7242CBA)
TEMP.
RANGE (oC) PACKAGE
0 to 70 8 Ld SOIC M8.15
PKG.
NO.
Long Range Fixed Timer
Description
The ICM7242 is a CMOS timer/counter circuit consisting of an RC oscillator followed by an 8-bit binary counter. It will replace the 2242 in most applications, with a significant reduction in the number of external components.
Three outputs are provided. They are the oscillator output, and buffered outputs from the first and eighth counters.
Pinout
ICM7242
(PDIP, SOIC)
TOP VIEW
V
DD
÷2 OUT
÷128/256 OUT
V
SS
1 2 3 4
8
TB I/O
7
RC
6
TRIGGER
5
RESET
Functional Diagram
R
1
50K
+
R
2
86K
7
R
3
RC
50K
1 4 8 5 6 2 3
V
DD
-
+
-
V
SS
R
Q
S
Q
R
CL
Q
Q
S
CL
CL
Q
Q
S
Q
Q
S
CL
CL
Q
Q
S
Q
Q
S
Q
CL
Q
S
Q
CL
Q
S
TRIGGERRESET ÷2 OUTTB I/O
CL
S
Q
Q
÷128/256
OUTPUT
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
8-163
File Number 2866.2
Page 2
ICM7242
Absolute Maximum Ratings Thermal Information
Supply Voltage (VDD to VSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . 18V
Input Voltage (Note 1)
Terminals (Pins 5, 6, 7, 8). . . . . . . . . .(VSS -0.3V) to (VDD +0.3V)
Continuous Output Current (Each Output). . . . . . . . . . . . . . . .50mA
Operating Conditions
Temperature Range
ICM7242I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25oC to 85oC
ICM7242C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0oC to 70oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. Due to the SCR structure inherent in the CMOS process, connecting any terminal to voltages greater than VDD or less than VSS may cause destructive device latchup. For this reason, it is recommended that no inputs from external sources not operating on the same supply be applied to the device before its supply is established and, that in m ultiple supply systems, the supply to the ICM7242 be turned on first.
2. θJA is measured with the component mounted on an evaluation PC board in free air.
Thermal Resistance (Typical, Note 2) θJA (oC/W)
PDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC
Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
Electrical Specifications V
= 5V, TA = 25oC, R = 10kΩ, C = 0.1µF, VSS = 0V, Unless Otherwise Specified
DD
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Guaranteed Supply Voltage V Supply Current I
DD
DD
Reset - 125 - µA
2 - 16 V
Operating, R = 10k, C = 0.1µF - 340 800 µA Operating, R = 1M, C = 0.1µF - 220 600 µA TB Inhibited, RC Connected to V
SS
- 225 - µA Timing Accuracy -5-% RC Oscillator Frequency Temperature
∆f/∆t Independent of RC Components - 250 - ppm/oC
Drift Time Base Output Voltage V
Time Base Output Leakage Current I Trigger Input Voltage V
OTBISOURCE
I
SINK
TBLK
TRIG
RC = Ground - - 25 µA VDD = 5V - 1.6 2.0 V
= 100µA - 3.5 - V
= 1.0mA - 0.40 - V
VDD = 15V - 3.5 4.5 V
Reset Input Voltage V
RST
VDD = 5V - 1.3 2.0 V
VDD = 15V - 2.7 4.0 V Trigger/Reset Input Current I Max Count Toggle Rate f
TRIG
, I
RST
VDD = 2V
T
VDD = 5V 2 6 - MHz
Counter/Divider Mode
-10-µA
- 1 - MHz
VDD = 15V - 13 - MHz
50% Duty Cycle Input with Peak to Peak
Output Saturation Voltage V
Output Sourcing Current I
SOURCEVDD
MIN Timing Capacitor (Note 3) C Timing Resistor Range (Note 3) R
SAT
T T
Voltages Equal to VDD and V
All Outputs Except TB Output VDD = 5V,
I
= 3.2mA
OUT
= 5V Terminals 2 and 3, V
VDD = 2 - 16V 1K - 22M
SS
- 0.22 0.4 V
= 1V - 300 - µA
OUT
10 - - pF
NOTE:
3. For design only, not tested.
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Page 3
Test Circuit
1
÷2
(RC/2) OUTPUT
8
÷2
(RC/256) OUTPUT
ICM7242
V
DD
1 2 3 4
TIME BASE INPUT/OUTPUT
8 7 6 5
C
V
R
DD
NOTE:
4. ÷21 and ÷28 outputs are inverters and have active pullups.
Application Information
Operating Considerations
Shorting the RC terminal or output terminals to V exceed dissipation ratings and/or maximum DC current limits (especially at high supply voltages).
There is a limitation of 50pF maximum loading on the TB I/O terminal if the timebase is being used to drive the counter section. If higher value loading is used, the counter sections may miscount.
For greatest accuracy, use timing component values shown in Figure 8. For highest frequency operation it will be desir­able to use very low values for the capacitor; accuracy will decrease for oscillator frequencies in excess of 200kHz.
The timing capacitor should be connected between the RC pin and the positive supply rail, V
, as shown in Figure 1.
DD
When system power is turned off, any charge remaining on the capacitor will be discharged to ground through a large internal diode between the RC node and V
. Do NOT refer-
SS
ence the timing capacitor to ground, since there is no high current path in this direction to safely discharge the capacitor when power is turned off. The discharge current from such a configuration could potentially damage the device.
When driving the counter section from an external clock, the optimum drive waveform is a square wave with an amplitude equal to the supply voltage. If the clock is a very slow ramp triangular, sine wave, etc., it will be necessary to “square up” the waveform; this can be done by using two CMOS invert­ers in series, operating from the same supply voltage as the ICM7242.
The ICM7242 is a non-programmable timer whose principal applications will be very low frequency oscillators and long range timers; it makes a much better low frequency oscilla­tor/timer than a 555 or ICM7555, because of the on-chip 8-bit counter. Also, devices can be cascaded to produce extremely low frequency signals.
DD
may
TRIGGERRESET
TIME BASE PERIOD = 1.0RC; 1s = 1M x 1µF
The timing diagram for the ICM7242 is shown in Figure 1. Assuming that the device is in the RESET mode, which occurs on power up or after a positive signal on the RESET terminal (if TRIGGER is low), a positive edge on the trigger input signal will initiate normal operation. The discharge transistor turns on, discharging the timing capacitor C, and all the flip-flops in the counter chain change states. Thus, the outputs on terminals 2 and 3 change from high to low states. After 128 negative timebase edges, the ÷2
8
output returns to
the high state.
TRIGGER INPUT (TERMINAL 6)
TIMEBASE INPUT (TERMINAL 8)
÷2 OUTPUT
(TERMINAL 2)
÷128/256 OUTPUT
(TERMINAL 3) (ASTABLE
128RC 128RC
128RC
FIGURE 1. TIMING DIAGRAMS OF OUTPUT WAVEFORMS
FOR THE ICM7242 (COMPARE WITH FIGURE 5)
V
DD
1
f
IN/2
OUTPUTS
f
IN/256
2 3 4
OR “FREE RUN” MODE)
÷128/256 OUTPUT
(TERMINAL 3) (MONOSTABLE OR “ONE SHOT” MODE)
f
IN
8 7 6
V
DD
5
≥3/4 (V+) ≤1/4 (V+)
Because outputs will not be ANDed, output inverters are used instead of open drain N-Channel transistors, and the external resistors used for the 2242 will not be required for the ICM7242. The ICM7242 will, however, plug into a socket for the 2242 having these resistors.
FIGURE 2. USING THE ICM7242 AS A RIPPLE COUNTER
(DIVIDER)
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ICM7242
To use the 8-bit counter without the timebase, Terminal 7 (RC) should be connected to ground and the outputs taken from Terminals 2 and 3.
The ICM7242 may be used for a very low frequency square wave reference. For this application the timing components are more convenient than those that would be required by a 555 timer. For very low frequencies, devices may be cas­caded (see Figure 3).
V
DD
1 2 3 4
R
8 7 6 5
C
f = RC/2
1 2
ICM7242ICM7242
3 4
16
8 7 6 5
FIGURE 3. LOW FREQUENCY REFERENCE (OSCILLATOR)
For monostable operation the ÷2
8
output is connected to the RESET terminal. A positive edge on TRIGGER initiates the cycle (NOTE: TRIGGER overrides RESET).
V
DD
OUTPUT
1 2 3 4
ICM7242
8 7 6 5
100k
S
1
RESET
R
C
TRIGGER
Comparing the ICM7242 With the 2242
ICM7242 2242
Operating Voltage 2V - 16V 4V - 15V Operating Temperature Range -25oC to 85oC0oC to 70oC Supply Current, VDD = 5V 0.7mA (Max) 7mA (Max) Pullup Resistors
TB Output No Yes
÷2 Output No Yes ÷256 Output No Yes
Toggle Rate 3.0MHz 0.5MHz Resistor to Inhibit Oscillator No Yes Resistor in Series with Reset for
No Yes
Monostable Operation Capacitor TB Terminal for HF
No Sometimes
Operation
By selection of R and C, a wide variety of sequence timing can be realized. A typical flow chart for a machine tool con­troller could be as shown in Figure 5.
TRIGGERING CAN BE OBTAINED FROM A PREVIOUS STAGE, A LIMIT SWITCH, OPER­ATOR SWITCH, ETC.
STOP
START STOP
WAIT
ENABLE
5s
START
ENABLE
5s
ICM7242 ICM7240 ICM7242
WAIT
10s
5s
ICM7242 ICM7242
WAIT
5s
COUNT
TO 185
COUNT
TO 185
ENABLE
5s
ENABLE
10s
WAIT
5s
TRIGGER
TB OUTPUT
OUTPUT TERMINAL 3
TERMINAL 6
TERMINAL 8
FIGURE 4. MONOSTABLE OPERATION
The ICM7242 is superior in all respects to the 2242 except for initial accuracy and oscillator stability. This is primarily due to the fact that high value p- resistors have been used on the ICM7242 to provide the comparator timing points.
FIGURE 5. FLOW CHART FOR MACHINE TOOL CONTROLLER
By cascading devices, use of low cost CMOS AND/OR gates and appropriate RC delays between stages, numerous sequential control variations can be obtained. Typical appli­cations include injection molding machine controllers, pho­nograph record production machines, automatic sequencers (no metal contacts or moving parts), milling machine control­lers, process timers, automatic lubrication systems, etc.
Sequence Timing
• Process Control
• Machine Automation
• Electro-Pneumatic Drivers
• Multi Operation (Serial or Parallel Controlling)
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Page 5
ICM7242
TRIGGER
V
DD
S
1
PUSH S
TO START SEQUENCE:
1
TRIGGER
OUTPUT A (NOTE)
OUTPUT B (NOTE)
50K
V
DD
R (NOTE)
63
ICM7242 A
MUST BE SHORTER THAN “ON TIME
128RC
C
5
100pF
33K
A
1µF
10K
V
DD
R (NOTE)
C
63
ICM7242
B
33K
5
100pF
128RC
V
DD
B
1µF
10K
A
R (NOTE)
63
ICM7242 C
CD
C
5
100pF
1µF
33K
10K
V
DD
R (NOTE)
C
63
ICM7242 D
33K
5
100pF
OUTPUT C (NOTE)
OUTPUT D (NOTE)
ON TIME
A
NOTE: Select RC values for desired “ON TIME” for each ICM7242.
FIGURE 6. SEQUENCE TIMER
ON TIME
128RC
128RC
ONTIME
B
C
ON TIME
D
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Page 6
Typical Performance Curves
ICM7242
260 240 220 200 180 160 140 120 100
80 60
SUPPLY CURRENT (µA)
40 20
0
0 2 4 6 8 10121416
SUPPLY VOLTAGE (V)
TA = -20oC
TA = 25oC
TA = 75oC
RESET MODE
100M
10M
1M
100k
10k
TIMING RESISTOR, R ()
1k
100
100pF 0.01 1 10 100 1000 10,000
RECOMMENDED RANGE OF
TIMING COMPONENT VALUES
0.10.001
TIMING CAPACITOR, C (µF)
TA = 25oC
FIGURE 7. SUPPLY CURRENT vs SUPPLY VOLTAGE FIGURE 8. RECOMMENDED RANGE OF TIMING COMPONENT
VALUES FOR ACCURATE TIMING
10,000µ
1,000µ
100µ
10µ
1µ
0.1µ
0.01µ
CAPACITANCE (F)
0.001µ
100p
10p
1M
1p
0.1 1 10 100 1K 10K 100K 1M 10M TIME BASE FREQUENCY (Hz)
10k
100k
10M
VDD = 5.0V
= 25oC
T
A
1k
1500 1400 1300 1200 1100 1000
900 800 700 600 500 400 300
TRIGGER PULSE WIDTH (ns)
200
VDD = 2V
100
0
012345678910
VDD = 5V
VDD = 16V
TRIGGER AMPLITUDE (V)
TA = 25oC
FIGURE 9. TIMEB ASE FREE R UNNING FREQUENCY vs R AND C FIGURE 10. MINIMUM TRIGGER PULSE WIDTH vs TRIGGER
AMPLITUDE
1500 1400 1300 1200 1100 1000
900 800 700 600 500 400
RESET PULSE WIDTH (ns)
300 200 100
0
012345678910
VDD = 5V
VDD = 2V
VDD = 16V
RESET AMPLITUDE (V)
TA = 25oC
FIGURE 11. MINIMUM RESET PULSE WIDTH vs RESET
AMPLITUDE
+10.0
+8.0 +6.0 +4.0 +2.0
0.0
-2.0
-4.0
-6.0
-8.0
-10.0
NORMALIZED FREQUENCY DEVIATION (%)
TA = 25oC
R
10k 1M 1k 100k 10k 100k
2 101214161820
864
SUPPLY VOLTAGE (V)
FIGURE 12. NORMALIZED FREQUENCY STABILITY IN THE
AST ABLE MODE vs SUPPLY V OLTAGE
C
0.001µF 100pF
0.1µF
0.001µF
0.01µF
0.01µF
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Page 7
Typical Performance Curves (Continued)
ICM7242
+5
5V VDD≤ 15V
+4 +3 +2 +1
0
-1
-2
-3
-4
NORMALIZED FREQUENCY DEVIA TION (%)
-5
-25 0 25 50 75 TEMPERATURE (oC)
R = 10M
C = 0.1µF
R = 1k C = 0.1µF
FIGURE 13. NORMALIZED FREQUENCY STABILITY IN THE
AST ABLE MODE vs TEMPERATURE
100
TA = 25oC
VDD = 15V
VDD = 5V
10
100M
10M
1M
100K
MAXIMUM DIVIDER FREQUENCY (Hz)
10K
0
2 101214161820
864
SUPPLY VOLTAGE (V)
TA = 25oC RC CONNECTED
TO GROUND
FIGURE 14. MAXIMUM DIVIDER FREQUENCY vs SUPPLY
VOLTAGE
100
TA = 25oC
10
VDD = 15V
VDD = 5V
VDD = 2V
1
DISCHARGE SINK CURRENT (mA)
0.1
0.01 0.1 1 10 DISCHARGE SATURATION VOLTAGE (V)
FIGURE 15. DISCHARGE OUTPUT CURRENT vs DISCHARGE
OUTPUT VOLTAGE
VDD = 2V
1
OUTPUT SATURATION CURRENT (mA)
0.1
0.01 0.1 1 10 OUTPUT SATURATION VOLTAGE (V)
FIGURE 16. OUTPUT SATURATION CURRENT vs OUTPUT
SATURATION VOLTAGE
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