Datasheet ICM7217, ICM7217AIPI, ICM7217IJI Datasheet (Intersil Corporation)

August 1997

ICM7217

4-Digit LED Display,

Programmable Up/Down Counter

Features

• Four Decade, Presettable Up-Down Counter with
Parallel Zero Detect

• Settable Register with Contents Continuously
Compared to Counter

• Directly Drives Multiplexed 7 Segment Common
Anode or Common Cathode LED Displays

• On-Board Multiplex Scan Oscillator

• Schmitt Trigger On Count Input

• TTL Compatible BCD I/O Port, Carry/Borrow, Equal,
and Zero Outputs

• Display Blank Control for Lower Power Operation;
Quiescent Power Dissipation <5mW

• All Terminals Fully Protected Against Static Discharge

• Single 5V Supply Operation

Description

The ICM7217 is a four digit, presettable up/down counter with
an onboard presettable register continuously compared to the
counter. The ICM7217 is intended for use in hard-wired
applications where thumbwheel switches are used for loading
data, and simple SPDT switches are used for chip control.

This circuit provides multiplexed 7 segment LED display
outputs, with common anode or common cathode
configurations available. Digit and segment drivers are
provided to directly drive displays of up to 0.8 inch
character height (common anode) at a 25% duty cycle. The
frequency of the onboard multiplex oscillator may be
controlled with a single capacitor, or the oscillator may be
allowed to free run. Leading zeros can be blanked. The
data appearing at the 7 segment and BCD outputs is
latched; the content of the counter is transferred into the
latches under external control by means of the Store pin.

The ICM7217 (common anode) and ICM7217A (common
cathode) versions are decade counters, providing a
maximum count of 9999, while the ICM7217B (common
anode) and ICM7217C (common cathode) are intended for
timing purposes, providing a maximum count of 5959.

This circuit provides 3 main outputs; a CARRY/BORROW
output, which allows for direct cascading of counters, a
ZERO output, which indicates when the count is zero, and
an

EQUAL output, which indicates when the count is equal
to the value contained in the register. Data is multiplexed to
and from the device by means of a three-state BCD I/O port.
The CARRY/BORROW,
BCD port will each drive one standard TTL load.

EQUAL, ZERO outputs, and the

To permit operation in noisy environments and to prevent
multiple triggering with slowly changing inputs, the count
input is provided with a Schmitt trigger.

Input frequency is guaranteed to 2MHz, although the device will
typically run with f
(EQUAL output) will typically run 750kHz maximum.

as high as 5MHz. Counting and comparing

IN

Ordering Information

PART

NUMBER

ICM7217AIPI -25 to 85 28 Ld PDIP Common Cathode Decade/9999 E28.6

ICM7217CIPl -25 to 85 28 Ld PDIP Common Cathode Timing/5959 E28.6

ICM7217IJI -25 to 85 28 Ld CERDIP Common Anode Decade/9999 F28.6

lCM7217BlJl -25 to 85 28 Ld CERDIP Common Anode Timing/5959 F28.6

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207

TEMP. RANGE

(oC) PACKAGE

| Copyright © Intersil Corporation 1999

DISPLAY DRIVER

9-12

TYPE

COUNT OPTION/

MAX COUNT PKG. NO.

File Number 3167.1

Pinouts

ICM7217 (PDIP)

COMMON ANODE

TOP VIEW

ICM7217

ICM7217 (CERDIP)

COMMON CATHODE

TOP VIEW

CARRY/BORROW

BCD I/O 8s
BCD I/O 4s
BCD I/O 2s
BCD I/O 1s

COUNT INPUT

UP/

LOAD REGISTER/

LOAD COUNTER/

EQUAL

STORE

I/O OFF

RESET

ZERO

DOWN

OFF

SCAN

10
11
12
13
14

1
2
3
4
5
6
7
8
9

ICM7217

ICM7217B

Functional Block Diagram

ZERO

V

DD

UP/

DN

COUNT

4

T.G.

4

D1
10

RS
ZERO
U/D

CL CARRY

T.G.

123

D2

123 4

10

ZERO
U/D

CL CARRY

28

D1
D2

27
26

D3

25

D4

24

V

DD

DISPLAY CONT.

23

SEG g

22

SEG b

21
20

V

SS

SEG e

19

SEG f

18

SEG d

17
16

SEG a
SEG c

15

4

4

RS

4

T.G.

4

D3
10

RS
ZERO
U/D

CL CARRY

ZERO
U/D
CL CARRY

CARRY/BORROW

COUNT INPUT

LOAD REGISTER/

LOAD COUNTER/

4

T.G.

4

D4
10

RS

4

4

EQUAL
BCD I/O 8s
BCD I/O 4s
BCD I/O 2s
BCD I/O 1s

STORE

UP/

I/O OFF

ZERO

DOWN

OFF

SCAN

RESET

4

4

1
2
3
4
5
6
7
8

9
10
11
12
13
14

T.G.

D1

REG.

COMP.

4

4

4

ICM7217A
ICM7217C

4

T.G.

4

D2

REG.

4

COMP.

28

SEG
SEG

27

SEG f

26

SEG c

25

V

24

DD

SEG a

23

SEG e

22

SEG g

21
20

DISPLAY CONT.
V

19

SS

D1

18
17

D2

16

D3
D4

15

4

T.G.

4

D3

REG.

4

COMP.

d
b

123

123

4

T.G.

4

D4

REG.

4

COMP.

V

SS

s

8
4s

BDC

2s
1s

I/O

SEGMENT DECODER

SEGMENT DRIVERS

A

(7)

T.G.

4

LATCH

MUX

4

LATCH

DISPLAY BLANK + OFF

DIGIT DRIVERS

GB C D E F

D4 D3 D2 D1

T.G.

4

MUX

4

(4)

T.G.

LATCH

MUX

T.G.

4

4

BCD I/O INPUTS
COM. ANODE: PULL DOWN
COM. CATHODE: PULL UP

4

LATCH

MUX

4

4

DIGIT MUX

L.R.

L.C.

RESET

4

4

CARRY/BARROW

MUX. I/O

AND

DISPLAY

CONTROL

LOGIC

MUX.

OSCILLATOR

4

4

EQUAL

V

DD

V

DD

V

DD

V

SS

V

DD

V

SS

V

DD

V

SS

4

STORE

RESET

LOAD
COUNTER

LOAD
REGISTER

DISPLAY
CONTROL

SCAN

9-13

ICM7217

Absolute Maximum Ratings Thermal Information

Supply Voltage (VDD - VSS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6V

Input Voltage (Any Terminal) . . . . . . . .(VSS- 0.3V) to (VDD + 0.3V)

(Note 1)

Operating Conditions

Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -25oC to 85oC

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

1. Due to the SCR structure inherent in the CMOS process used to fabricate these devices, connecting any terminal to a voltage greater
than VDD or less than VSS may cause destructive device latchup. For this reason it is recommended that the power supply to the device
be established before any inputs are applied and that in multiple systems the supply to the ICM7217 be turned on first.

2. θJA is measured with the component mounted on an evaluation PC board in free air.

Thermal Resistance (Typical, Note 2) θJA (oC/W) θJC (oC/W)

CERDIP Package . . . . . . . . . . . . . . . . 55 14

PDIP Package. . . . . . . . . . . . . . . . . . . 55 N/A

Maximum Junction Temperature

PDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150oC

CERDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175oC

Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

Maximum Lead Temperature (Soldering, 10s) . . . . . . . . . . . .300oC

Electrical Specifications V

= 5V, VSS = 0V, TA = 25oC, Display Diode Drop 1 .7V, Unless Otherwise Specified

DD

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Supply Current
(Lowest Power Mode), IDD (7217)

Supply Current, OPERATING, I
Supply Current, OPERATING, I
V
Digit Driver Output Current, I

SUPPLY

, V

DD

DIG

SEGment Driver

Display Off, LC, DC, UP/DN,
ST, RS, BCD I/O Floating or at V

Common Anode, Display On, all “8’s” 140 200 - mA

OP

Common Cathode, Display On, all “8’s” 50 100 - mA

OP

(Note 1)

DD

- 350 500 µA

4.5 5 5.5 V
Common Anode, V
Common Anode, V

= VDD - 2.0V 140 200 - mA

OUT

= +1.5V 20 35 - mA

OUT

Output Current, ISEG
Digit Driver, Output Current, I
SEGment Driver

Common Cathode, V

DIG

Common Cathode V

= +1.0V -50 -75 - mA

OUT

= VDD - 2V -9 -12.5 - mA

OUT

Output Current, ISEG
ST, RS, UP/DN Input

VIN = VDD - 2V (Note 1) 5 25 - µA

Pullup Current, IP
3 Level Input Impendance, ZIN 40 - 350 kΩ
BCD I/O Input, High Voltage

VBIH
BCD I/O Input, Low Voltage

VBIL
BCD I/O Input, Pullup Current

IBPU
BCD I/O Input

Pulldown Current, IBPD
BCD I/O,

ZERO, EQUAL Outputs

ICM7217 Common Anode (Note 2) 1.5 - - V
ICM7217 Common Cathode (Note 2) 4.40 - - V
ICM7217 Common Anode (Note 2) - - 0.60 V
ICM7217 Common Cathode (Note 2) - - 3.2V V
ICM7217 Common Cathode V

= VDD - 2V

IN

525-µA

(Note 2)
ICM7217 Common Anode V

= +2V (Note 2) 5 25 - µA

IN

IOH = -100µA 3.5 - - V

Output High Voltage, VOH
BCD I/O, CARRY/BORROW

IOL = 1.6mA - - 0.4 V

ZERO, EQUAL Outputs
Output Low Voltage, V

Count Input Frequency, f

OL

IN

-20oC to 70oC - 5 - MHz
Guaranteed 0 - 2 MHz

Count Input Threshold, VTH (Note 3) - 2 - V
Count Input Hysteresis, VHYS (Note 3) - 0.5 - V
Count Input LO, VCIL - - 0.40 V
Count Input HI, VCIH 3.5 - - V
Display Scan

Oscillator Frequency, f

DS

Free-running (SCAN Terminal Open Circuit) - 2.5 10 kHz

PEAK
PEAK

PEAK
PEAK

9-14

ICM7217

Switching Specifications V

= 5V, VSS = 0V, TA = 25oC

DD

PARAMETER MIN TYP MAX UNIT

UP/DOWN Setup Time, t
UP/DOWN Hold Time, t
COUNT Pulse Width High, t
COUNT Pulse Width Low, t

UCS

UCH

CWH

CWI

COUNT to CARRY/BORROW Delay, t
CARRY/BORROW Pulse Width t
COUNT to EQUAL Delay, t
COUNT to ZERO Delay, t
RESET Pulse Width, t

RST

BW

CE

CZ

CB

300 - - ns

1500 750 - ns

250 100 - ns
250 100 - ns

- 750 - ns

- 100 - ns

- 500 - ns

- 300 - ns

1000 500 - ns

NOTES:

1. In the ICM7217 the UP/DOWN,ST ORE,RESET and the BCD I/O as inputs hav e pullup or pulldown de vices which consume power when
connected to the opposite supply. Under these conditions, with the display off, the device will consume typically 750µA.

2. These voltages are adjusted to allow the use of thumbwheel switches for the ICM7217. Note that a high level is taken as an input logic
zero for ICM7217 common-cathode versions.

3. Parameters not tested (Guaranteed by Design).

Timing Waveforms

SCAN

INTERNAL OSC

OUTPUT

D4

INTERNAL

(BCD AND
SEGMENT

ENABLE)

INTERNAL
(COMMON

ANODE

DIGIT

STROBES)

D3

D2
D1

D4

D3

D2
D1

10µs TYP 400µs TYP

FREE-RUNNING

FREE-RUNNING

INTERDIGIT BLANK

FIGURE 1. MULTIPLEX TIMING

9-15

Timing Waveforms

ICM7217

LOAD COUNTER

(OR LOAD REGISTER)

UP/

DOWN

COUNT INPUT

CARRY/BORROW

EQUAL

ZERO

t

UCS

t

CWH

t

t

t

CB

CEL

CZL

t

UCH

t

BW

FIGURE 2. COUNT AND OUTPUTS TIMING

t

CWL

t

CZH

t

CEH

SCAN

D4

D3

D2

D1

INTERNAL

OPERATING

MODE

BCD I/O

= HIGH IMPEDANCE
= THREE-STATE W/PULLDOWN

OUTPUT

OUT

D

N

INPUT

D4

IN

D3
IN

D2

IN

FIGURE 3. BCD I/O AND LOADING TIMING

COUNT INHIBITED IF
LOAD COUNTER

D1

IN

D4 OUT D3 OUT

9-16

Typical Performance Curves

300

4.5 ≤ VDD ≤ 6V

ICM7217
ICM7217B

200

IDIG (mA)

100

85oC

25oC

-20oC

ICM7217

80

60

40

ISEG (mA)

20

TA= 25oC

V+ = 5.5V

ICM7217
ICM7217B

V+ = 4.5V

V+ = 5V

0

0123

VDD - V

OUT

(V)

0

012 3

FIGURE 4. TYPICAL IDIG vs V+ FIGURE 5. TYPICAL ISEG vs V

80

V+ = 5V

-20oC

ICM7217

60

ICM7217B

40

OUT

25oC

(V)

OUT

ISEG (mA)

20

0

0123

85oC

V

FIGURE 6. TYPICAL ISEG vs V

200

TA= 25oC

200

150

100

IDIGIT (mA)

50

V+ = 5V

ICM7217A
ICM7217C

0

0123

FIGURE 7. TYPICAL IDIGIT vs V

30

4.5 ≤ VDD − VSS≤ 6V

V

OUT

-20oC

85oC

V

OUT

(V)

OUT

25oC

(V)

OUT

-20oC

150

100

IDIGIT (mA)

50

0

0123

FIGURE 8. TYPICAL IDIGIT vs V

V+ = 5.5V

ICM7217A
ICM7217C

V+ = 5V

V

OUT

V+ = 4.5V

(V)

OUT

9-17

25oC

ICM7217A

20

ICM7217C

85oC

ISEG (mA)

10

0

0123

FIGURE 9. TYPICAL ISEG vs VDD - V

VDD - V

OUT

(V)

OUT

Detailed Description

ICM7217

Control Outputs

The CARRY/BORROW output is a positive going pulse
occurring typically 500ns after the positive going edge of the
COUNT INPUT. It occurs when the counter is clocked from
9999 to 0000 when counting up and from 0000 to 9999 when
counting down. This output allows direct cascading of
counters. The CARRY/BORROW output is not valid during
load counter and reset operation. When the count is 6000 or
higher, a reset generates a CARRY/BORROW pulse.

The

EQUAL output assumes a negative level when the

contents of the counter and register are equal.
The

ZERO output assumes a negative level when the

content of the counter is 0000.
The CARRY/BORROW,

EQUAL and ZERO outputs will drive
a single TTL load over the full range of supply voltage and
ambient temperature; for a logic zero, these outputs will sink

1.6mA at 0.4V and for a logic one, the outputs will source
>60µA. A 10kΩ pull-up resistor to V

on the EQUAL or

DD

ZERO outputs is recommended for highest speed operation,
and on the CARRY/BORROW output when it is being used
for cascading. Figure 2 shows control outputs timing
diagram.

Display Outputs and Control

The Digit and SEGment drivers provide a decoded
7-segment display system, capable of directly driving com­mon anode LED displays at typical peak currents of
35mA/seg. This corresponds to average currents of
8mA/seg at 25% multiplex duty cycle. For the common cath­ode versions, peak segment currents are 12.5mA, corre­sponding to average segment currents of 3.1mA. Figure 1
shows the multiplex timing. The DISPLAY pin controls the
display output using three level logic. The pin is self-biased
to a voltage approximately
normal operation. When this pin is connected to V
segments are disabled and when connected to V

1

/2 (VDD); this corresponds to

, the

DD

, the

SS

leading zero blanking feature is inhibited. For nor mal opera­tion (display on with leading zero blanking) the pin should be
left open. The display may be controlled with a 3 position
SPDT switch; see Test Circuit.

Multiplex SCAN Oscillator

The on-board multiplex scan oscillator has a nominal free­running frequency of 2.5kHz. This may be reduced by the
addition of a single capacitor between the SCAN pin and the
positive supply. Capacitor values and corresponding nominal
oscillator frequencies, digit repetition rates, and loading
times are shown in Table 1.

R1

10kΩ

1MΩ 0.01µF

R2
20kΩ

C

FIGURE 10A. FIGURE 10B.

10kΩ

200Ω

SCAN INPUT
ICM7217

0.05µF

748

ICM7555

2
61 8s

3

0.05µF

500Ω

1MΩ 0.01µF

3kΩ

500Ω

= 5V

V

DD

SCAN INPUT
ICM7217

0V

SCAN INPUT
ICM7217

FIGURE 10C.

FIGURE 10. BRIGHTNESS CONTROL CIRCUITS

9-18

ICM7217

TABLE 1. ICM7217 MULTIPLEXED RATE CONTROL

SCAN

NOMINAL

SCAN

CAPACITOR

None 2.5kHz 625Hz 1.6ms
20pF 1.25kHz 300Hz 3.2ms
90pF 600Hz 150Hz 8ms

OSCILLATOR

FREQUENCY

DIGIT

REPETITION

RATE

CYCLE

TIME

(4 DIGITS)

The internal oscillator output has a duty cycle of
approximately 25:1, providing a short pulse occurring at the
oscillator frequency. This pulse clocks the four-state counter
which provides the four multiplex phases. The shor t pulse
width is used to delay the digit driver outputs, thereb y pro vid­ing inter-digit blanking which prevents ghosting. The digits
are scanned from MSD (D4) to LSD (D1). See Figure 1 for
the display digit multiplex timing.

During load counter and load register operations, the
multiplex oscillator is disconnected from the SCAN input and
is allowed to free-run. In all other conditions, the oscillator
may be directly overdriven to about 20kHz, however the
external oscillator signal should have the same duty cycle as
the internal signal, since the digits are blanked during the
time the external signal is at a positive level (see Figure 1).
To insure proper leading zero blanking, the interdigit blank­ing time should not be less than about 2µs. Overdriving the
oscillator at less than 200Hz may cause display flickering.

The display brightness may be altered by var ying the duty
cycle. Figure 10 shows several variable-duty-cycle oscilla­tors suitable for brightness control at the ICM7217 SCAN
input. The inverters should be CMOS CD4000 series and
the diodes may be any inexpensive device such as lN914.

Counting Control,

STORE, RESET

As shown in Figure 2, the counter is incremented by the
rising edge of the COUNT INPUT signal when UP/
high. It is decremented when UP/

DOWN is low. A Schmitt

DOWN is

trigger on the COUNT INPUT provides hysteresis to prevent
double triggering on slow rising edges and permits operation
in noisy environments. The COUNT INPUT is inhibited dur­ing reset and load counter operations.

The

STORE pin controls the internal latches and
consequently the signals appearing at the 7-Segment and
BCD outputs. Bringing the

STORE pin low transfers the con-

tents of the counter into the latches.
The counter is asynchronously reset to 0000 by bringing the

RESET pin low. The circuit performs the reset operation by
forcing the BCD input lines to zero, and “presetting” all four
decades of counter in parallel. This affects register loading; if
LOAD REGISTER is activated when the
the register will also be set to zero. The
UP/

DOWN pins are provided with pullup resistors of appro xi-

RESET input is low,

STORE, RESET and

mately 75kΩ.

BCD I/O Pins

The BCD I/O port provides a means of transferring data to
and from the device. The ICM7217 versions can multiplex
data into the counter or register via thumbwheel switches,

depending on inputs to the LOAD COUNTER or LOAD
REGISTER pins; (see below). When functioning as outputs,
the BCD I/O pins will drive one standard TTL load. Common
anode versions have internal pull down resistors and com­mon cathode versions have internal pull up resistors on the
four BCD I/O lines when used as inputs.

LOADing the COUNTER and REGISTER

The BCD I/O pins, the LOAD COUNTER (LC), and LOAD
REGISTER (LR) pins combine to provide presetting and
compare functions. LC and LR are 3-level inputs, being self­biased at approximately

1

/2VDD for normal operation. With
both LC and LR open, the BCD I/O pins provide a multi­plexed BCD output of the latch contents, scanned from MSD
to LSD by the display multiplex.

When either the LOAD COUNTER (Pin 12) or LOAD
REGISTER (Pin 11) is taken low, the dr ivers are turned off
and the BCD pins become high-impedance inputs. When LC
is connected to V

, the count input is inhibited and the lev-

DD

els at the BCD pins are multiplexed into the counter. When
LR is connected to V

, the levels at the BCD pins are mul-

DD

tiplexed into the register without disturbing the counter.
When both are connected to V

, the count is inhibited and

DD

both register and counter will be loaded.
The LOAD COUNTER and LOAD REGISTER inputs are

edge-triggered, and pulsing them high for 500ns at room
temperature will initiate a full sequence of data entry cycle
operations (see Figure 3). When the circuit recognizes that
either or both of the LC or LR pins input is high, the multiplex
oscillator and counter are reset (to D4). The internal
oscillator is then disconnected from the SCAN pin and the
preset circuitry is enabled. The oscillator starts and runs with
a frequency determined by its internal capacitor, (which may
vary from chip to chip). When the chip finishes a full 4-digit
multiplex cycle (loading each digit from D4 to D3 to D2 to D1
in turn), it again samples the LOAD REGISTER and LOAD
COUNTER inputs. If either or both is still high, it repeats the
load cycle, if both are floating or low, the oscillator is
reconnected to the SCAN pin and the chip returns to normal
operation. Total load time is digit “on” time multiplied by 4. lf
the Digit outputs are used to strobe the BCD data into the
BCD I/O inputs, the input must be synchronized to the
appropriate digit (Figure 3). Input data must be valid at the
trailing edge of the digit output.

When LR is connected to GROUND, the oscillator is
inhibited, the BCD I/O pins go to the high impedance state,
and the segment and digit drivers are turned off. This allows
the display to be used for other purposes and minimizes
power consumption. In this display off condition, the circuit
will continue to count, and the CARRY/BORROW,

EQUAL,
ZERO, UP/DOWN, RESET and STORE functions operate
as normal. When LC is connected to ground, the BCD I/O
pins are forced to the high impedance state without disturb­ing the counter or register. See “Control Input Definitions”
(Table 2) for a list of the pins that function as three-state self­biased inputs and their respective operations.

Note that the ICM7217 and ICM7217B have been designed
to drive common anode displays. The BCD inputs are high
true, as are the BCD outputs.

9-19

ICM7217

INPUT

CD4069 1N4148

OUTPUT INPUT

CD4069

1N4148

INPUT OUTPUT INPUT OUTPUT

High High High Disconnected

Low Disconnected Low High

FIGURE 11A. CMOS INVERTER FIGURE 11B. CMOS INVERTER

CD4502B

INPUT A

INPUT B

CD74HC03

OUTPUT

INPUT A

INPUT B

INPUT B INPUT A OUTPUT INPUT B INPUT A OUTPUT

High High Low High High Disconnected
High Low Disconnected High Low Disconnected

Low High Disconnected Low High High
Low Low Disconnected Low Low Low

FIGURE 11C. CMOS OPEN DRAIN FIGURE 11D. CMOS THREE-STATE BUFFER

FIGURE 11. DRIVING 3-LEVEL INPUTS OF ICM7217

OUTPUT

OUTPUT

DN DIGIT LINE

DIGIT

DRIVE

ICM7217

ICM7217B

SEGMENT

DRIVE

DISPLAY

50kΩ

CONTROL

ICM7217
ICM7217B

FIGURE 12A. COMMON ANODE

FIGURE 12. FORCING LEADING ZERO DISPLAY

V

DD

2N2219
OR SIMILAR

V

SS

V

DD

2N6034
OR SIMILAR

V

DN DIGIT LINE

V

DD

50kΩ

50kΩ

DD

DISPLAY
CONTROL

ICM7217A
ICM7217C

FIGURE 12B. COMMON CATHODE

V

DD

SEGMENT

DRIVE

ICM7217

ICM7217C

DIGIT

DRIVE

V

SS

V

DD

2N2219
OR SIMILAR

2N6034
OR SIMILAR

V

SS

V

SS

FIGURE 13A. COMMON ANODE DISPLAY FIGURE 13B. COMMON CATHODE DISPLAY

FIGURE 13. DRIVING HIGH CURRENT DISPLAYS

9-20

LCD DISPLAY

28 SEGMENTS

AND BACKPLANE

37 - 40

2 - 26

ICM7211

D4
D3
D2

D1
DB3
DB2
DB1
DB0

35
34
33
32
31
30
29
28
27

ICM7217

VDD = 5VVDD = 5V

4

8s

5

4s

6

2s

7

1s

24

V

DD

23

DC

20

2

4

8

1

C

2

4

8

1

C

2

4

8

1

C

FIGURE 14. LCD DISPLAY INTERFACE (WITH THUMBWHEEL SWITCHES)

The lCM7217A and the ICM7217C are used to drive com­mon cathode displays, and the BCD inputs are low true.
BCD outputs are high true.

Notes on Thumbwheel Switches and Multiplexing

As it was mentioned, the ICM7217 is basically designed to
be used with thumbwheel switches for loading the data to
the device. See Figure 14 and Figure 17.

The thumbwheel switches used with these circuits (both
common anode and common cathode) are TRUE BCD
coded; i.e. all switches open corresponds to 0000. Since the
thumbwheel switches are connected in parallel, diodes must
be provided to prevent crosstalk between digits. In order to
maintain reasonable noise margins, these diodes should be
specified with low forward voltage drops (IN914). Similar ly, if
the BCD outputs are to be used, resistors should be inserted
in the Digit lines to avoid loading problems.

Output and Input Restrictions

LOAD COUNTER and LOAD REGISTER operations take

1.6ms typical (5ms maximum) after LC or LR are released.
During this load period the

EQUAL and ZERO outputs are
not valid (see Figure 3). Since the Counter and register are
compared by XOR gates, loading the counter or register can

COUNT

STORE

UP/DN

RESET

2

4

8

1

C

10kΩ - 20kΩ

8

9
10
14

cause erroneous glitches on the

ICM7217

IJI

EQUAL and ZERO outputs

D1
D2
D3
D4

28
27
26
25

when codes cross.
LOAD COUNTER or LOAD REGISTER, and

RESET input
can not be activated at the same time or within a short
period of each other. Operation of each input must be
delayed 1.6ms typical (5ms f or guar anteed proper oper ation)
relating to the preceding one.

Counter and register can be loaded together with the same
value if LC and LR inputs become activated exactly at the
same time.

Notice the setup and hold time of UP/DOWN input when it is
changing during counting operation. Violation of UP/

DOWN
hold time will result in incrementing or decrementing the
counter by 1000, 100 or 10 where the preceding digit is
transitioning from 5 to 6 or 6 to 5.

The

RESET input may be susceptible to noise if its input rise
time is greater than about 500µs This will present no prob­lems when this input is driven by active devices (i.e., TTL or
CMOS logic) but in hardwired systems adding virtually any
capacitance to the

RESET input can cause trouble. A simple
circuit which provides a reliable power-up reset and a fast
rise time on the

RESET input is shown on Figure 15.

9-21

ICM7217

When using the circuit as a programmable divider (÷ by n
with equal outputs) a short time delay (about 1µs) is needed
from the

EQUAL output to the RESET input to establish a

pulse of adequate duration. (See Figure 16).
When the circuit is configured to reload the counter or regis-

ter with a new value from the BCD lines (upon reaching
EQUAL), loading time will be digit “on” time multiplied by
four. If this load time is longer than one period of the input
count, a count can be lost. Since the circuit will retain data in
the register, the register need only be updated when a new
value is to be entered.

RESET will not clear the register.

Test Circuit

COMMON ANODE DISPLAY

a

f

b

g

e

c

d

V

DD

V

SS

N.O.

0.047µF
10Ω

RESET INPUT

ICM7217

10kΩ 5kΩ

FIGURE 15. POWER ON RESET

V

DD

33K

47pF

RESETEQUAL

FIGURE 16. EQUAL TO RESET DELAY

c

a

f

b

g

e

c

d

D3 D2D4

a

f

b

g

e

c

d

a

f

g

e

c

d

D1

a

d

b

f

e

b

g

THUMBWHEEL SWITCHES

BCD I/O 8s
BCD I/O 4s
BCD I/O 2s
BCD I/O 1s

COUNT INPUT

V

DD

+5V

D3 D2D4

D1

9999

CARRY

ZERO

EQUAL

STORE

DOWN

UP/

LOAD REGISTER

LOAD COUNTER

SCAN

RESET

N.O.

10
11
12
13
14

1
2
3
4
5
6
7
8
9

ICM7217

ICM7217B

V

DD

V

SS

28
27
26
25
24
23
22
21
20
19
18
17
16
15

DISPLAY
CONTROL

9-22

ICM7217

Applications

3-Level Inputs

ICM7217 has three inputs with 3-level logic states; High, Low
and Disconnected. These inputs are: LOAD REGISTER/OFF,
LOAD COUNTER/

The circuits illustrated on Figure 11 can be used to drive
these inputs in different applications.

Fixed Decimal Point

In the common anode versions, a fixed decimal point may be
activated by connecting the DP segment lead from the appro­priate digit (with separate digit displays) through a 39Ω series
resistor to Ground. With common cathode devices, the DP
segment lead should be connected through a 75Ω series
resistor to V

To force the device to display leading zeroes after a fixed
decimal point, use a bipolar transistor and base resistor in a
configuration like that shown in Figure 12 with the resistor
connected to the digit output driving the DP for left hand DP
displays, and to the next least significant digit output for right
hand DP display.

Driving Larger Displays

For displays requiring more current than the ICM7217 can
provide, the circuits of Figure 13 can be used.

LCD Display Interface

The low-power operation of the ICM7217 makes an LCD
interface desirable. The Intersil ICM7211 4-digit, BCD-to-LCD
display driver easily interfaces to the ICM7217 as shown in
Figure 14. Total system power consumption is less than 5mW.
System timing margins can be improved by using capacitance
to ground to slow down the BCD lines.

The 10kΩ - 20kΩ resistors on the switch BCD lines serve to
isolate the switches during BCD output.

Unit Counter with BCD Output

The simplest application of the ICM7217 is a 4-digit unit
counter (Figure 18). All that is required is an ICM7217, a
power supply and a 4 digit display. Add a momentary switch
for reset, an SPDT center-off switch to blank the display or
view leading zeroes, and one more SPDT switch for up/
down control. Using an ICM7217A with a common-cathode
calculator-type display results in the least expensive digital
counter/display system available.

Inexpensive Frequency Counter/ Tachometer

This circuit uses the low power ICM7555 (CMOS 555) to
generate the gating,
in Figure 19. To provide the gating signal, the timer is con­figured as an a stable multivibrator, using R
provide an output that is positive for approximately one sec­ond and negative for approximately 300µs - 500µs. The pos­itive waveform time is given by t
while the negative waveform is given by two = 0.693 R
The system is calibrated by using a 5MΩ potentiometer for
R

as a “coarse” control and a 1kΩ potentiometer for RB as

A

I/O OFF and DISPLAY CONT.

.

DD

STORE and RESET signals as shown

, RB and C to

A

= 0.693 (RA + RB)C

WP

C.

B

a “fine” control. CD40106Bs are used as a monostable
multivibrator and reset time delay.

Tape Recorder Position Indicator/controller

The circuit in Figure 20 shows an application which uses the
up/down counting feature of the ICM7217 to keep track of
tape position. This circuit is representative of the many
applications of up/down counting in monitoring dimensional
position.

In the tape recorder application, the LOAD REGISTER,
EQUAL and ZERO outputs are used to control the recorder.
To make the recorder stop at a particular point on the tape,
the register can be set with the stop point and the
output used to stop the recorder either on fast forward, play
or rewind.

To make the recorder stop before the tape comes free of the
reel on rewind, a leader should be used. Resetting the
counter at the starting point of the tape, a few feet from the
end of the leader, allows the
the recorder on rewind, leaving the leader on the reel.

The 1MΩ resistor and 0.0047µF capacitor on the COUNT
INPUT provide a time constant of about 5ms to debounce
the reel switch. The Schmitt trigger on the COUNT INPUT of
the ICM7217 squares up the signal before applying it to the
counter. This technique may be used to debounce
switch-closure inputs in other applications.

Precision Elapsed Time/Countdown Timer

The circuit in Figure 21 uses an ICM7213 precision one
minute/one second timebase generator using a 4.1943MHz
crystal for generating pulses counted by an ICM7217B. The
thumbwheel switches allow a starting time to be entered into
the counter for a preset-countdown type timer, and allow the
register to be set for compare functions. For instance, to
make a 24-hour clock with BCD output the register can be
preset with 2400 and the
counter. Note the 10K resistor connected between the LO AD
COUNTER terminal and Ground. This resistor pulls the
LOAD COUNTER input low when not loading, thereby
inhibiting the BCD output drivers. This resistor should be
eliminated and SW4 replaced with an SPDT center-off
switch if the BCD outputs are to be used.

This technique may be used on any 3-le v el input. The 100kΩ
pullup resistor on the count input is used to ensure proper
logic voltage swing from the ICM7213. For a less expensive
(and less accurate) timebase, an ICM7555 timer may be
used in a configuration like that shown in Figure 19 to
generate a 1Hz reference.

8-Digit Up/Down Counter

This circuit (Figure 22) shows how to cascade counters and
retain correct leading zero blanking. The NAND gate detects
whether a digit is active since one of the two segments
is active on any unblanked number. The flip flop is clocked
by the least significant digit of the high order counter, and if
this digit is not blanked, the Q output of the flip flop goes high
and turns on the NPN transistor, thereby inhibiting leading
zero blanking on the low order counter.

ZERO output to be used to stop

EQUAL output used to reset the

EQUAL

a or b

9-23

ICM7217

It is possible to use separate thumbwheel switches for
presetting, but since the devices load data with the oscillator
free-running, the multiplexing of the two devices is difficult to
synchronize.

Precision Frequency Counter/Tachometer

The circuit shown in Figure 23 is a simple implementation of
a four digit frequency counter , using an ICM7207A to provide
the one second gating window and the

STORE and RESET
signals. In this configuration, the display reads hertz directly.
With Pin 11 of the ICM7027A connected to V

, the gating

DD

time will be 0.1s; this will display tens of hertz at the least
significant digit. For shorter gating times, an ICM7207 may
be used (with a 6.5536MHz crystal), giving a 0.01s gating
with Pin 11 connected to V

, and a 0.1s gating with Pin 11

DD

open.
To implement a four digit tachometer, the ICM7207A with

one second gating should be used. To get the display to read
directly in RPM, the rotational frequency of the object to be

TABLE 2. CONTROL INPUT DEFINITIONS ICM7217

INPUT TERMINAL VOLTAGE FUNCTION

STORE 9 VDD (or floating)

V

measured must be multiplied by 60. This can be done
electronically using a phase-locked loop, or mechanically by
using a disc rotating with the object with the appropriate
number of holes drilled around its edge to interrupt the light
from an LED to a photo-dector. For faster updating, use 0.1s
gating, and multiply the rotational frequency by 600.

Auto-Tare System

This circuit uses the count-up and count-down functions of
the ICM7217, controlled via the
to count in SYNC with an ICL7109A and ICL7109D Con­verter as shown in Figure 24. By
a “tare” value conversion, and
value conversion, an automatic fare subtraction occurs in the
result.

The ICM7217 stays in step with the ICL7109 by counting up
and down between 0 and 4095, for 8192 total counts, the
same number as the ICL7109 cycle. See applications note
No. A047 for more details.

SS

EQUAL and ZERO outputs,

RESETing the ICM7217 on

STORE-ing the result of a true

Output Latches Not Updated
Output Latches Updated

UP/DOWN 10 VDD (or floating)

V

SS

RESET 14 VDD (or floating)

V

SS

LOAD COUNTER/
I/O OFF

LOAD REGlSTER/
OFF

DISPLAY CONTrol 23 Common Anode

20 Common Cathode

12 Unconnected

V

DD

V

SS

11 Unconnected

V

DD

V

SS

Unconnected

V

DD

V

SS

Counter Counts Up
Counter Counts Down

Normal Operation
Counter Reset

Normal Operation
Counter Loaded with BCD data
BCD Port Forced to Hi-Z Condition

Normal Operation
Register Loaded with BCD Data
Display Drivers Disabled; BCD Port
Forced to Hi-Z Condition, mpx Counter
Reset to D4; mpx Oscillator Inhibited

Normal Operation
Segment Drivers Disabled
Leading Zero Blanking Inhibited

9-24

ICM7217

TO D4 STROBE TO D1 STROBE

C

8

1

4

2

TO BCD INPUTS OF ICM7217, ICM7217B

C

8

1

4

2

8421

FIGURE 17. THUMBWHEEL SWITCH/DIODE CONNECTIONS

CARRY

ZERO

BCD I/O

COUNT INPUT

STORE

1
2

4
5
6
7
8
9

EQUIVALENT

ICM7217A

IN914 OR

21 - 23
25 - 28

24

20

TO D4 STROBE TO D1 STROBE

8

COMMON CATHODE

LED DISPLAY

DISPLAY
CONTROL

C

1

4

2

TO BCD INPUTS OF ICM7217A, ICM7217C

7 SEGMENTS

V

DD

BLANK
NORMAL
INHIBIT LZB

C

8

4

8421

1

2

RESET

19

14

15 - 18

FIGURE 18. UNIT COUNTER

4-DIGIT

9-25

5M

1K

R

A

V

7

DIS OUT

R

B

2

TR

6

TH

DD

ICM7217

8

RS

4

3

3K 10K

0.047µF

GATE

9

8

STORE

ICM7217

COUNT

24

V

DD

LED DISPLAY

V

SS

0.47µF

INVERTERS: CD40106B
NANDS: CD4011B

GATE

STORE

RESET

REEL SWITCH

CLOSED ONCE/REV

1

C

1M

0.0047µF

CV

5

GND

COUNT INPUT

14

RESET

V

SS

20

FIGURE 19A.

300µs1s

50µs

FIGURE 19B.

FIGURE 19. INEXPENSIVE FREQUENCY COUNTER

STOP

LOGIC TO GENERATE

RECORDER CONTROL

SIGNALS

THUMBWHEEL SWITCHES

ZERO
EQ

128

CARRY
ZERO
EQUAL

d
b

f

7 SEGMENTS

COMMON CATHODE

LED DISPLAY

c

V

V

DD

9999

4 DIGIT

BCD I/O

DD

a
e

V

DD

V

DD

FORWARD
REWIND

N.O.

RESET

N.O.

SET PT

COUNT IN
STORE

UP/DOWN
LOAD REG

LOAD CTR
SCAN
RESET

D1
D2
D3
D4

g

BLANK
NORMAL
INHIBIT LZB

V

DD

4 DIGITS

FIGURE 20. TAPE RECORDER POSITION INDICATOR

9-26

RUN MIN/SEC

ICM7217

V

DD

100K

1
2
3
4

30pF

30pF 4.1943MHz

CRYSTAL

< 75Ω

R

S

THUMBWHEEL SWITCHES

ELAPSED

COUNTDOWN
LOAD SET PT.

DISPLAY OFF

ICM7213
5
6
7

14
13
12
11
10

9
8

5959

V

DD

V

DD

PRESET

V

DD

RESET

STOP

RUN HRS/MIN

V

DD

(4V MAX)

SW2

SW3
10K

SW4

SW5

SW1

4

EQUAL
ZERO

CARRY
ZERO
EQUAL

BCD

4

I/O

DIS. CONT.

COUNT IN
STORE

UP/DOWN

LOAD REG

LOAD CTR
SCAN

RESET

ICM7217

TO LOGIC GENERATING
SIGNALS FOR CONTROL OF
EXTERNAL EQUIPMENT

D1
D2
D3
D4

V

DD

V

DD

g
b

V

SS

4

BLANK
SW6
INHIBIT

LZB

e

f
d
a
c

V

DD

COMMON ANODE

LED DISPLAY

7

SEGMENTS

DIGITS

FIGURE 21. PRECISION TIMER

9-27

COUNT INPUT

ICM7217

COMMON-ANODE

LED DISPLAY

CARRY OUT

BCD OUTPUTS
HIGH ORDER DIGITS

UP/DOWN

V+

RESET

N.O.

1
4 - 7

4

8
9

10

14

25 - 28

ICM7217

15 - 19

21, 22

HIGH ORDER

4 DIGITS

D1

24
20

50kΩ 3kΩ

V+

V+ D

CARRY/BORROW

BCD OUTPUTS
HIGH ORDER DIGITS

7 SEGMENTS

1A

1B

1

/

4

CD4011

1

/

2

CD4013

CL

4 DIGITS

1

4

Q

4 - 7

8
9
10
14

50kΩ

25 - 28

24
20

ICM7217

23

15 - 19

21, 22

LOW ORDER

7 SEGMENTS

V+

NPN
TRANSISTOR

FIGURE 22. 8-DIGIT UP/DOWN COUNTER

9-28

ICM7217

10kΩ

CRYSTAL

f = 5.24288MHz

R

= 75Ω

S

GND

1

STATUS

2

POL

3

OR

4

B12

5

B11

6

B10

7

B9

8

B8

9

B7

10
11
12
13
14
15
16
17
18
19
20

ICM7109

B6
B5
B4
B3
B2
B1
TEST
LBEN
HBEN
CE/LOAD

BUF OSC OUT

2

4
5
6

V

DD

REF IN -

REF CAP -

REF CAP +

REF IN +

IN HI

IN LO

COMMON

INT

AZ

BUF

REF OUT

V

SEND

RUN/

HOLD

OSC SEL

OSC OUT

OSC IN

MODE

ICM7207A

INPUT

40
39
38
37
36
35
34
33
32
31
30
29
28

SS

27
26
25
24
23
22
21

10kΩ22pF22pF

4

BCD
14
13

10

1

/

4

CD4011

OUT

COUNT
STORE

RESET

5
6
7

8
9

14

25 - 28

24

ICM7217

15 - 19

21, 22

20

FIGURE 23. PRECISION FREQUENCY COUNTER (MHz MAXIMUM)

10µF

TARE

+5V

270

LED

MINUS SIGN

5 x 1N4148

4 DIGIT COMMON ANODE

CARRY/

1

BORROW

2

ZERO

3

EQUAL
BCD 8

4

BCD 4

5

BCD 2

6

BCD 1

7
8

COUNT
STORE

9

10

UP/

11

LOAD REG.

12

LOAD CTR.

13

SCAN
RESET

14

FULL SCALE

+5V

1µF

47K

+5V

+5V

400mV

INPUT

+

0.1µF

0.1µF

0.22µF

100pF

100K

-

100K

10K

+5V

100K

+5V

SS

QDQD
QQ

RR

LED DISPLAY

DOWN

ICM7217

V+ = 5V

4 DIGITS

7 SEGMENTS

28

D0
D1

27
26

D2
D3

25

V

24

DD

DISP.

23

CONT.

22

G

21

B

20

V

SS

19

E

18

F

17

D

16

A

15

C

COMMON ANODE

LED DISPLAY

7

7

47µF

+5V

FIGURE 24. AUTO-TARE SYSTEM FOR A/D CONVERTER

9-29

ICM7217

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.

Intersil products are sold by description only. Intersil Cor poration reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under an y patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see web site http://www.intersil.com

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9-30

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