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Important notice: This document contains information of a new product. IC
Media Corp reserves the right to make any changes without further notice to any
product herein to improve design, function or quality and reliability. No
responsibility is assumed by IC Media Corp for its use, nor for any infringements
of patents of third parties which may result from its use.
IC Media Technology Corporation
6F, No. 61, ChowTze Street., NeiHu District
Taipei, Taiwan, R.O.C.
Phone: 886-2-2657-7898
Fax: 886-2-2657-8751
Email: Ap.Sales@IC-Media.Com.tw
Web Site: www.ic-media.com.tw
• 1 mega pixels (1152x864) format, used with 1/2” optical system
• Support sub-sampling at quarter (1/4) mega pixel resolution for higher video frame rate
• Progressive readout
• Output data format: 10-bit raw data
• Input interface: SIF
• Electronic exposure control
• On-chip 11-bit ADC
• On-chip PLL
• Correlated double sampling
• Video mode and DSC mode
• Dead pixel removal
• Flash control
• Power down mode
• Automatic optical black compensation
• Horizontal and veritcal images
• Single 3.3V power supply
General Description
ICM-107B is a single-chip digital color-imaging device. It incorporates a 1152x864 sensor array capable
of operating at up to 30 frames per second and sub-sampled quarter mega pixel resolution, operating at
higher frame rate in progressive manner. Each pixel is covered by a color filter, which formed a so-called
Bayer pattern. Correlated double sampling is performed by the internal ADC and timing circuitry. The
gains for raw data can be adjusted separately for the 4 Bayer pattern pixels. The output format is 10-bit raw
data that can be fed to other DSP, color processing, or compression chips.
Applications
• Digital camcorder
• Digital still camera
• Video phone
• Video conferencing
• Video mail
• Video cellular phone
• PC camera
• Security system
• Visual toy
• Industrial image capture/analysis
• Environment monitor system
Key Parameters
• Number of pixels: 1152x864
• Number of physical pixels: 1,015,588, (1162x874)
Pin # Name Class* Function
14 CLKSEL D, I, N Clock source selection
0: clocks pass PLL, use XIN (pin 12)
1: bypass PLL, use CLKIN (pin 11)
11 CLKIN D, I, N External clock source; bypass PLL
12 XIN A, I Crystal oscillator in, or external clock in; if external
clocks used, leave Xout (pin 13) unconnected
13 XOUT A, O Crystal oscillator out
33 PCLK D, O Pixel clock output
35 OEN D, I, N Output enable. 0: enable, 1: disable
31 SIF ID D, I, N LSB of SIF slave address
32 MSSEL D, I, U SIF master/slave selection. 0: slave, 1: master
2 SCL D, I/O SIF clock
1 SDA D, I/O SIF data
10 POWERDN D, I, N Power down control, 0: power down, 1: active
17 RSET A, I
8 RSTN D, I, U Chip reset, active low
48 DOUT[10] D, I/O Data output bit 10
47 DOUT[9] D, I/O Data output bit 9
46 DOUT[8] D, I/O Data output bit 8
45 DOUT[7] D, O Data output bit 7
44 DOUT[6] D, I/O Data output bit 6; if pulled up/down, the initial value
43 DOUT[5] D, I/O Data output bit 5; if pulled up/down, the initial value
40 DOUT[4] D, I/O Data output bit 4; if pulled up/down, the initial value
39 DOUT[3] D, I/O Data output bit 3; if pulled up/down, the initial value
38 DOUT[2] D, I/O Data output bit 2; if pulled up/down, the initial value
37 DOUT[1] D, I/O Data output bit 1; if pulled up/down, the initial value
36 DOUT[0] D, I/O Data output bit 0; if pulled up/down, the
3 HSYNC D, I/O Horizontal sync signal
5 VSYNC D, I/O Vertical sync signal
34 FLASH D, O Flash light control
15 RAMP A, O Analog ramp output
30,7 VDDA P Sensor analog power
29,9 GNDA P Sensor analog ground
19 VDDD P Sensor digital power
18 GNDD P Sensor digital ground
41,4 VDDK P Digital power
synchronization mode is in master/slave mode which
requires HSYNC and VSYNC operating in
output/input mode
Page 5
ICM107B Mega pixel CMOS sensor
Data Sheet Version 1.0 July 2002
42,6 GNDK P Digital ground
Class Code: A – Analog signal, D – Digital signal, I – Input, O – Output, P – Power or ground, U – Internal
pull-up, N – Internal pull-down
ICM-107B is a single-chip digital color imaging device. It includes a 1152x864 sensor array, 1152
column-level ADC, and correlated double sampling circuitry. All the programmable parameters are set by
writing into the SIF interface which can address the register file consisting of 8-bit registers. The output
format is 10-bit raw data, together with horizontal and vertical sync signals.
SIF
Interface
Timing & Function
Control
Sensor Array
1152 x 864
Column-Level
ADC
Correlated
Double
Sampling
Individual
RGB gain control
RGB Bayer Pattern
Output Control
Figure 1. Block diagram
2.1 Image Array
The image array consists of 1152x864 pixels. Each pixel has a light sensitive photo diode and a set of
control transistors. At the beginning of the cycle, a row of pixels is pre-charged to its maximum value.
Then the row is exposed to light for several lines worth of time and sampled by the ADC. A “Correlated
Double Sampling (CDS)” process is performed with subtracting the reset value (sampled right before
sampling the signal) from the signal value. The purpose of CDS is to eliminate the point-wise fixed pattern
noise (FPN). The output of CDS is approximately proportional to the amount of received light, ranging
from 0 to 1023.
Each pixel is covered by a color filter. They form the Bayer Pattern as shown in Figure 2. (Row 0,
Column 0) is covered by a Red filter, (Row 0, Column 1) and (Row 1, Column 0) by Green filters, and
(Row 1, Column 1) by a Blue filter. Since each pixel only gets part of the frequency band, the data need
further processing (i.e., color interpolation and color correction) in order to approximate the full visible
spectrum.
R G
G B
R G R G R G R G
G B G B G B G B
R G R G R G
G B G B G B
Figure 2. Color filter Bayer pattern
2.3 Exposure and Gain Control
The brightness of the scene may change by a great amount that renders the captured image either overexposed or under-exposed. To accommodate for different brightness, the user may change the exposure
time by adjusting the AD_EXPOSE_TIMEH, and AD_EXPOSE_TIMEL. The exposure time is measured
in terms of the time to read out one line of data, which is equal to 31.25 µs (assuming the line length is
1500 @ 48 MHz). If the number of lines per frame is set at 1100 (the default), the exposure time can vary
from 1 to 1100 lines. In addition, users can adjust registers AD_M1_L, AD_M1_H, AD_M2_L,
AD_M2_H, AD_M3_L, AD_M3_H, AD_M4_L, AD_M4_H, to optimize the individual R/G1/G2/B gain
(default at 3.8 format for 1/256 to 8) of the 4 Bayer pattern pixels separately.
2.4 Timing Control
Timing control is performed with programming a 32-entry wave table. Its content can be filled by external
circuitry after power up if other than default values are desirable. Bits 19 to 11 are the control signals. Bits
10 to 0 are the change position. Whenever the change position equals the column counter, a new set of
signal values are applied. Please see the Wave Table Programming section for details.
During normal operation, the output format is 10-bit raw data that ranges from 0 to 1023. It may be used
for off-chip color processing or compression. A typical configuration is to connect ICM-107B to a USB1,
a USB2, or a 1394/Compression combo chip. At 30 fps, the PCLK and main clock are both operating at 48
MHz.
In addition to the data pins, the chip also output VSYNC, HSYNC, and PCLK. The length and polarity of
VSYNC and HSYNC can be adjusted through registers. The line and frame timing can be adjusted through
registers AD_WIDTH and AD_HEIGHT.
2.6 SIF Interface
Register programming is through SIF interface (SCL and SDA pins). The default 7-bit SIF device address
is 0x20, meanwhile the last bit can be configured by the SIF ID pin. ICM-107B can operate in either SIF
master mode or slave mode right after power up, depending on the pull-up or pull-down of the MSSEL pin.
When MSSEL is pulled low during power-up, ICM-107B’s SIF interface is operated as an SIF slave
device, waiting to be controlled by an external SIF master such as a microprocessor. When MSSEL is
pulled high during power-up, the SIF interface is first acting as an SIF master device trying to read from an
external SIF EEPROM. After that, it will fall back to behave like an SIF slave.
[0] 0: normal video mode, 1: single frame
mode
[1] Slope adjustment enable
[2] Exposure time control, writing a 1 will
activate the new value set in
AD_EXPOSE_TIME, when read back from it,
0 means either the exposure time change is
finished (in video mode) or the entire frame
is transmitted (in single frame mode), 1
means either the exposure time change is still
in progress (in video mode) or the frame is
yet to finish (in single frame mode)
[3] 0: normal mode, 1:sub-sampling mode
[6:4] Frame rate,
0: 30 fps
1: 15 fps
2: 10 fps
3: 5 fps
4: 4 fps
5: 3 fps
6: 2 fps
7: 1 fps
[7] Latent change, writing a 1 means the
changed latent registers now starts taking
effect, when the entire operation is done, the
read back value of this bit will change from 1
In different frame rate mode (controlled by PART_CONTROL [6:4]), the duty cycle (high time / clock
period) of the PCLK signal is described in the following table: