Datasheet ICL7662 Datasheet (Intersil Corporation)

ICL7662

Data Sheet April 1999

CMOS Voltage Converter

The Intersil ICL7662 is a monolithic high-voltage CMOS
power supply circuit which offers unique performance ad­vantages over previously available devices. The ICL7662
performs supply voltage conversionfrompositivetonegative
for an input range of +4.5V to +20.0V, resulting in
complementary output voltages of -4.5V to -20V. Only 2
noncritical external capacitors are needed for the charge
pump and charge reservoir functions. The ICL7662 can also
function as a voltage doubler, and will generate output
voltages up to +38.6V with a +20V input.

Contained on chip are a series DC power supply regulator,
RC oscillator,voltage leveltranslator, fouroutput power MOS
switches. A unique logic element senses the most negative
voltage in the device and ensures that the output N-Channel
switch source-substrate junctions are not forward biased.
This assures latchup free operation.

The oscillator, when unloaded, oscillates at a nominal
frequency of 10kHz for an input supply voltage of 15.0V. This
frequency can be lowered by the addition of an external
capacitor to the “OSC” terminal, or the oscillator may be
overdriven by an external clock.

The “LV” terminal may be tied to GROUND to bypass the
internal series regulator and improve low voltage (LV)
operation. At medium to high voltages (+10V to +20V), the
LV pin is left floating to prevent device latchup.

File Number

3181.3

Features

• No External Diode Needed Over Entire Temperature
Range

• Pin Compatible With ICL7660

• Simple Conversion of +15V Supply to -15V Supply

• Simple Voltage Multiplication (V

OUT

= (-)nVIN)

• 99.9% Typical Open Circuit Voltage Conversion
Efficiency

• 96% Typical Power Efficiency

• Wide Operating Voltage Range 4.5V to 20.0V

• Easy to Use - Requires Only 2 External Non-Critical
Passive Components

Applications

• On Board Negative Supply for Dynamic RAMs

• Localized µProcessor (8080 Type) Negative Supplies

• Inexpensive Negative Supplies

• Data Acquisition Systems

• Up to -20V for Op Amps

Pinouts

ICL7662CBD-0 (SOIC)

TEST

NC

CAP+

NC

GND

NC

CAP-

TOP VIEW

1
2
3
4
5
6
7

14
13
12
11
10

9
8

3-45

V+
OSC
NC
LV
NC
NC
V

OUT

ICL7662CBD AND IBD (SOIC)

TOP VIEW

NC

TEST

NC

CAP+

GND

NC
NC

1
2
3
4
5
6
7

V+

14
13

NC
OSC

12
11

LV

10

NC

9

V
CAP-

8

CAP+

OUT

ICL7662 (CAN)

TEST

1

2

3

GND

TOP VIEW

V+

8

4

OSC

7

LV

6

5

V

OUT

ICL7662 (PDIP)

TOP VIEW

TEST

1

CAP+

2

GND

3
4

CAP-

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

8

V+
OSC

7

LV

6
5

V

OUT

http://www.intersil.com or 407-727-9207

| Copyright © Intersil Corporation 1999

Ordering Information

ICL7662

PART

NUMBER

TEMP. RANGE

(oC) PACKAGE PKG. NO.

ICL7662CTV 0 to 70 8 Pin Metal Can T8.C
ICL7662CPA 0to 70 8 Ld PDIP E8.3
ICL7662CBD-0 0 to 70 14 Ld SOIC (N) M14.15
ICL7662CBD 0 to 70 14 Ld SOIC (N) M14.15
ICL7662ITV -40 to 85 8 Pin Metal Can T8.C
ICL7662IPA -40to 85 8 Ld PDIP E8.3
ICL7662IBD -40 to 85 14 Ld SOIC (N) M14.15
ICL7662MTV

-55 to 125 8 Pin Metal Can T8.C

(Note 1)

NOTE:

1. Add /883 to part number if /883B processing is required.

Functional Block Diagram

RC

OSCILLATOR

÷ 2

VOLTAGE

LEVEL

TRANSLATOR

V+

CAP+

CAP-

TEST

P

N

OSC LV

VOLTAGE

REGULATOR

LOGIC

NETWORK

V

OUT

3-46

ICL7662

Absolute Maximum Ratings Thermal Information

Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22V

Oscillator Input Voltage . . . . . . . . -0.3V to (V+ +0.3V) for V+ < 10V

. . . . . . . . . . . . . . . . . (Note 2) (V+ -10V) to (V+ +0.3V) for V+ > 10V

Current Into LV (Note 2). . . . . . . . . . . . . . . . . . . . 20µA for V+ > 10V

Output Short Duration . . . . . . . . . . . . . . . . . . . . . . . . . . .Continuous

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationofthe
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

2. Connecting any terminal to voltages greater than V+ or less than GND may cause destructive latchup. It is recommended that no inputs from
sources operating from external supplies be applied prior to “power up” of ICL7660S.

3. θJA is measured with the component mounted on an evaluation PC board in free air.

Thermal Resistance (Typical, Note 3) θJA(oC/W) θJC (oC/W)

PDIP Package . . . . . . . . . . . . . . . . . . . 150 N/A

Plastic SOIC Package . . . . . . . . . . . . . 120 N/A

Metal Can. . . . . . . . . . . . . . . . . . . . . . . 156 68

Maximum Lead Temperature (Soldering, 10s). . . . . . . . . . . . .300oC

(SOIC - Lead Tips Only)

Electrical Specifications V+ = 15V, T

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Supply Voltage Range - Lo V+L R
Supply Voltage Range - Hi V+H RL = 10kΩ, LV = Open Min < TA < Max 9 - 20 V
Supply Current I+ RL = ∞, LV = Open TA = 25oC - 0.25 0.60 mA

Output Source Resistance R

Supply Current I+ V+ = 5V, RL = ∞,

Output Source Resistance R

Oscillator Frequency FOSC - 10 - kHz
Power Efficiency P

Voltage Conversion Efficiency VoEf RL = ∞ Min < TA < Max 97 99.9 - %
Oscillator Sink or Source

Current

NOTE:

4. Pin 1 is a Test pin and is not connected in normal use. When the TEST pin is connected to V+, an internal transmission gate disconnects any
external parasitic capacitance from the oscillator which would otherwise reduce the oscillator frequency from its nominal value.

EFF

I

OSC

= 25oC, C

A

= 10kΩ, LV = GND Min < TA < Max 4.5 - 11 V

L

IO = 20mA,

O

LV = Open

LV = GND

V+ = 5V, IO = 3mA,

O

LV = GND

RL = 2kΩ TA = 25oC9396-%

V+ = 5V (V
V+ = 15V (V

= 0, Unless Otherwise Specified. Refer to Figure 14.

OSC

0oC < TA < 70oC

-40oC < TA < 85oC

-55oC < TA < 125oC - 0.40 1.0 mA
TA = 25oC - 60 100 Ω
0oC < TA < 70oC

-40oC < TA < 85oC

-55oC < TA < 125oC - 90 150 Ω
TA = 25oC - 20 150 µA
0oC < TA < 70oC

-40oC < TA < 85oC

-55oC < TA < 125oC - 30 250 µA
TA = 25oC - 125 200 Ω
0oC < TA < 70oC

-40oC < TA < 85oC

-55oC < TA < 125oC - 200 350 Ω

Min < TA < Max 90 95 - %

= 0V to +5V) - 0.5 - µA

OSC

= +5V to +15V) - 4.0 - µA

OSC

- 0.30 0.85 mA

- 70 120 Ω

- 25 200 µA

- 150 250 Ω

3-47

ICL7662

Typical Performance Curves

190

170

150

130

110

90

70

OUTPUT RESISTANCE (Ω)

50

30

FIGURE 1. OUTPUTSOURCE RESISTANCEAS A

180
170
160
150
140
130
120
110
100

90
80

OUTPUT RESISTANCE (Ω)

70
60
50

-55 -20 0 25 70 125

FIGURE 3. OUTPUTSOURCE RESISTANCEAS A

LV = GND

0 2 4 6 8 10 12 14 16 18 20

V+ (V)

FUNCTION OF SUPPLY VOLTAGE

TEMPERATURE (oC)

FUNCTION OF TEMPERATURE

(See Figure 14, Test Circuit)

IL = 20mA
T

= 25oC

A

C

= 0pF

OSC

LV = OPEN

V+ = 5V
I

= 3mA

L

V+ = 15V
I

= 20mA

L

190

170

150

130

110

90

70

OUTPUT RESISTANCE (Ω)

50

30

0 2 4 6 8 10 12 14 16 18 20

LV = GND

V+ (V)

IL = 3mA

= 25oC

T

A

= 0pF

C

OSC

LV = OPEN

FIGURE 2. OUTPUTSOURCE RESISTANCEAS A

FUNCTION OF SUPPLY VOLTAGE

100

95

90

P

EFF

85

80

75

70

POWER CONVERSION EFFICIENCY (%)

65

100 1K 10K 100K

F

(Hz)

OSC

R

O

V+ = 5V

= 3mA

I

L

T

= 25oC

A

FIGURE 4. POWER CONVERSIONEFFICIENCY AND

OUTPUT SOURCE RESISTANCE AS A
FUNCTION OF OSCILLATOR FREQUENCY

350

300

250

200

150

100

50

OUTPUT RESISTANCE (Ω)

11

RL = ∞
TA = 25oC

10

C

= 0pF

OSC

9
8
7
6
5

LV = GND

4

OSCILLATOR FREQUENCY (kHz)

3
2

02468101214161820

LV = OPEN

SUPPLY VOLTAGE (V)

FIGURE 5. OSClLLATOR FREQUENCY vs SUPPLY VOLTAGE

NOTE: All typical values have been characterized but are not tested.

3-48

10K

1K

100

OSCILLATOR FREQUENCY (Hz)

10

1 10 100 1000 10K

C

(pF)

OSC

V+ = 15V
T

= 25oC

A

= ∞

R

L

FIGURE 6. FREQUENCYOF OSCILLATIONAS A FUNCTION

OF EXTERNAL OSCILLATOR CAPACITANCE

ICL7662

Typical Performance Curves

15K
14K
13K
12K
11K
10K

9K
8K
7K

OSCILLATOR FREQUENCY (Hz)

6K
5K

-55 -20 0 25 70 125
TEMPERATURE (oC)

(See Figure 14, Test Circuit) (Continued)

FIGURE 7. UNLOADED OSClLLATORFREQUENCY

AS A FUNCTION OF TEMPERATURE

2

V+ = 5V
T

= 25oC

A

1

LV = GND

0

-1

-2

V+ = 15V

= 0pF

C

OSC

-1

-2

V+ = 15V

-3

TA = 25oC

-4

(V)

O

OUTPUT VOLTAGE V

-5

-6

-7

-8

-9

-10

-11

-12

-13

-14

-15

LV = OPEN

SLOPE = 65Ω

10 20 30 40 50 60 70 80 90 100

LOAD CURRENT IL (mA)

FIGURE 8. OUTPUTVOLTAGE AS A FUNCTION

OF LOAD CURRENT

100

95

90

85

80

PBFF

V+ = 5V
T

= 25oC

A

I+

40

32

24

-3

OUTPUT VOLTAGE VO (V)

-4

-5
02468101214161820

LOAD CURRENT I

SLOPE = 14Ω

(mA)

L

FIGURE 9. OUTPUTVOLTAGE AS A FUNCTION

OF LOAD CURRENT

100

95

90

85

80

75

70

POWER CONVERSION EFFICIENCY (%)

65

0102030405060708090100

PBFF

LOAD CURRENT I

(mA)

L

V+ = 15V

= 25oC

T

A

I+

200

160

120

80

SUPPLY CURRENT I+ (mA)

40

75

70

POWER CONVERSION EFFICIENCY (%)

65

0 2 4 6 8101214161820

LOAD CURRENT I

(mA)

L

16

8

FIGURE 10. SUPPLY CURRENT AND POWER CONVERSION

EFFICIENCY AS A FUNCTION OF LOAD

RL = ∞
TA = 25oC

= 0pF

C

OSC

11
10

9
8
7
6
5

OSCILLATOR FREQUENCY (kHz)

4
3
2

0 2 4 6 8101214161820

LV = OPEN

SUPPLY VOLTAGE (V)

LV = GND

SUPPLY CURRENT I+ (mA)

FIGURE 11. SUPPLY CURRENT AND POWERCONVERSION

EFFICIENCY AS A FUNCTION OF LOAD
CURRENT

3-49

FIGURE 12. FREQUENCYOF OSCILLATION AS A

FUNCTION OF SUPPLY VOLTAGE

ICL7662

Typical Performance Curves

NOTE:

5. These curves include in the supply current that current fed directly into the load RLfrom the V+ (See Figure 14). Thus, approximately half the
supply current goes directly to the positive side of the load, and the other half, through the ICL7662, to the negative side of the load. Ideally,
V

∼ 2VIN, IS∼ 2IL, so VIN x IS∼ V

OUT

(See Figure 14, Test Circuit) (Continued)

150
140
130
120
110
100

90
80
70
60
50

SUPPLY CURRENT I+ (µA)

40
30
20
10

10 100 1K 10K

FIGURE 13. SUPPLY CURRENT AS A FUNCTION OF

x IL.

OUT

OSCILLATOR FREQUENCY (Hz)

OSCILLATOR FREQUENCY

Circuit Description

The ICL7662 contains all the necessary circuitry to complete
a negative voltageconverter, with the exceptionof 2 external
capacitors which may be inexpensive 10µF polarized
electrolytic capacitors. The mode of operation of the device
may be best understood by considering Figure 15, which
shows an idealized negative voltage converter.Capacitor C
is charged to a voltage, V+, for the half cycle when switches
S

and S3 are closed. (Note: Switches S2 and S4 are open

1

during this half cycle.) During the second half cycle of
operation, switches S
open, thereby shifting capacitor C1 negatively by V+ volts.
Charge is then transferred from C
voltage on C
load on C

is exactly V+, assuming ideal switches and no

2

. The lCL7662 approaches this ideal situation

2

more closely than existing non-mechanical circuits.
In the lCL7662, the 4 switches of Figure 15 are MOS power

switches; S

is a P-Channel device and S2, S3 and S4 are

1

N-Channel devices. The main difficulty with this approach is
that in integrating the switches, the substrates of S
must always remain reverse biased with respect to their
sources, but not so much as to degrade their “ON”
resistances. In addition, at circuit startup, and under output
short circuit conditions (V
be sensed and the substrate bias adjusted accordingly.
Failure to accomplish this would result in high power losses
and probable device latchup.

and S4 are closed, with S1 and S

2

to C2 such that the

1

and S

3

= V+), the output voltage must

OUT

3

This problem is eliminated in the ICL7662 by a logic network
which senses the output voltage (V
leveltranslators, and switches the substrates of S

) together with the

OUT

and S4to

3

the correct level to maintain necessary reverse bias.
The voltage regulator portion of the ICL7662 is an integral

1

part of the anti-latchup circuitry, howe ver its inherent voltage
drop can degrade operation at low voltages . Therefore, to
improve low v oltage oper ation the “LV” pin should be
connected to GROUND, disabling the regulator. For supply
voltages greaterthan 10V the LV terminal must be left open to
insure latchup proof operation, and prevent device damage.

I

V+

S

1
2

+

C

1

-

ICL7662

3
4

4

NOTE: For large valueof C
should be increased to 100µF.

FIGURE 14. ICL7662 TEST CIRCUIT

8
7
6
5

C

OSC

(NOTE)

-

C

2

+

10µF

(> 1000pF) the values of C1and C

OSC

(+5V)

I

L

R

L

-V

OUT

2

3-50

ICL7662

S

8

V

IN

FIGURE 15. IDEALIZED NEGATIVE CONVERTER

1

S

3

7

S

2

4

2

C

1

S

4

33

C

2

V

= -V

OUT

5

Theoretical Power Efficiency
Considerations

In theory a voltage multipliercanapproach100% efficiency if
certain conditions are met:

1. The drive circuitry consumes minimal power.

2. The output switches have extremely low ON resistance
and virtually no offset.

3. Theimpedancesofthe pumpandreservoircapacitorsare
negligible at the pump frequency.

The ICL7662 approaches these conditions for negative
voltage multiplication if large values of C

ENERGY IS LOST ONLY INTHE TRANSFER OF CHARGE
BETWEEN CAPACITORS IF A CHANGE IN VOLTAGE
OCCURS. The energy lost is defined by:

2

E = 1/2C

(V

1

2

- V

1

)

2

where V1 and V2 are the voltages on C1 during the pump
and transfer cycles. If the impedances of C
relatively high at the pump frequency (refer to Figure 15)
compared to the value of R
difference in the voltages V
desirabletomakeC

2

, there will be a substantial

L

and V2. Therefore it is not only

1

as large as possible to eliminate output
voltage ripple, but also to employ a correspondingly large
value for C

in order to achieve maximum efficiency of

1

operation.

Do’s and Don’ts

1. Do not exceed maximum supply voltages.

2. Do notconnect LVterminal toGROUND forsupply voltag­es greater than 10V.

3. When using polarizedcapacitors, the + terminal of C
must be connected to pin 2 of the ICL7662 and the + ter­minal of C

4. If the voltage supply driving the 7662 has a large source
impedance (25Ω -30Ω), then a 2.2µF capacitor from pin
8 to ground may be required to limit rate of rise of input
voltage to less than 2V/µs.

5. User should insure that the output (pin 5) does not go
morepositivethan GND(pin 3). Devicelatch up willoccur
under these conditions.

must be connected to GROUND.

2

and C2 are used.

1

and C2 are

1

1

A 1N914 or similar diode placed in parallel with C

2

will
prevent the device from latching up under these conditions.
(Anode pin 5, Cathode pin 3).

Typical Applications

Simple Negative Voltage Converter

IN

The majority of applications will undoubtedly utilize the
ICL7662 for generation of negative supply voltages. Figure
16 shows typical connections to provide a negative supply
where a positive supply of +4.5V to 20.0V is available. Keep
in mind that pin 6 (LV) is tied to the supply negative (GND)
for supply voltages below 10V.

The output characteristics of the circuit in Figure 16A can be
approximated by an ideal voltage source in series with a
resistance as shown in Figure 16B. The voltage source has
a value of -(V+). The output impedance (R

) is a function of

O

the ON resistance of the internal MOS switches (shown in
Figure 2), the switching frequency, the value of C
and the ESR (equivalent series resistance) of C
good first order approximation for R

RO≅ 2(R

+ 2(R

(f

PUMP

Combining the four R

RO≅ 2 x RSW +

SW1

SW2

=

+ R

+ R

f

SW4

OSC

2

SW3

,

f

+ ESRC1)

+ ESRC1) +

R

= MOSFET switch resistance)

SWX

terms as RSW, we see that

SWX

1

x C

PUMP

is:

O

1

f

x C

PUMP

+ 4 x ESRC1 + ESRC2Ω

1

and C2,

1

and C2. A

1

+ ESRC

1

RSW, the total switch resistance, is a function of supply
voltageand temperature (See the Output Source Resistance
graphs), typically 24Ω at +25
and 5V. Careful selection of C

o

C and 15V, and 53Ω at +25oC

and C2 will reduce the

1

remaining terms, minimizing the output impedance. High
value capacitors will reduce the 1/(f

x C1) component,

PUMP

and low FSR capacitors will lower the ESR term. Increasing
the oscillator frequency will reduce the 1/(f

PUMPxC1

) term,
but may have the side effect of a net increase in output
impedance when C

> 10µF and there is no longer enough

1

time to fully charge the capacitors every cycle. In a typical
application where f

= 10kHz and C = C1 = C2 = 10µF:

OSC

1

RO≅ 2 x 23 +

+ 4 ESRC1 + ESRC

(5 x 103 x 10 x 10-6)

≅ 46 + 20 + 5 x ESRCΩ

R

O

Since the ESRs of the capacitors are reflected in the output
impedance multiplied by a factor of 5, a high value could
potentially swamp out a low 1/(f

x C1) term, rendering

PUMP

an increase in switching frequency or filter capacitance
ineffective.Typicalelectrolytic capacitors may have ESRs as
high as 10Ω.

2

2

3-51

ICL7662

V+

10µF

C

1

1
2

+

-

ICL7662

3
4

8
7
6
5

10µF

R

O

V

OUT

-

-

V

OUT

C

+

2

= -V+

V+

+

16A. 16B.

FIGURE 16. SIMPLENEGATIVE CONVERTER AND ITS

OUTPUT EQUIVALENT

Output Ripple

ESR also affects the ripple voltage seen at the output. The
total ripple is determined by 2V,A and B, as shown in Figure

16. Segment A is the voltage drop across the ESR of C
the instant it goes from being charged by C
into C

) to being discharged through the load (current

2

flowing out of C
xI

, hence the total drop is 2 x I

OUT

B is the voltage change across C
the cycle when C
I

OUTxt2/C2

). The magnitude of this current change is 2

2

OUT

during time t2, the half of

supplies current the load. The drop at B is

2

2

V. The peak-to-peak ripple voltage is the sum of

(current flowing

1

x ESRC2V. Segment

these voltage drops:

1



V

RIPPLE

----------------------------------------- 2 ESRC

≅



2f

××

PUMPC2

×+

2IOUT

at

2

Again, a low ESR capacitor will result in a higher
performance output.

Paralleling Devices

Any number of ICL7662 voltage converters may be
paralleled (Figure 18) to reduce output resistance. The
reservoir capacitor, C
requires its own pump capacitor, C

, serves all devices while each device

2

. The resultant output

1

resistance would be approximately:

R

(of ICL7662)

R

OUT

OUT

=

n (number of devices)

Cascading Devices

The ICL7662 may be cascaded as shown in Figure 19 to
produce larger negative multiplication of the initial supply
voltage. However, due to the finite efficiency of each device,
the practical limit is 10 devices for light loads. The output
voltage is defined by:

V

= -n(VIN),

OUT

where n is an integer representing the number of devices
cascaded. The resulting output resistance would be
approximately the weighted sum of the individual ICL7662
R

values.

OUT

t

1

-(V+)

t

2

B

0

V

A

FIGURE 17. OUTPUT RIPPLE

V+
1
2

ICL7662

C

1

3

“1”

4

8
7
6
5

C

1

1
2
3
4

ICL7662

“N”

8
7
6
5

­+

R

L

C

2

FIGURE 18. PARALLELING DEVICES

3-52

ICL7662

10µF

1
2

+

-

3
4

ICL7662

“1”

8
7
6
5

10µF

FIGURE 19. CASCADING DEVICES FOR INCREASED OUTPUT VOLTAGE

Changing the ICL7662 Oscillator Frequency

It may be desirable in some applications , due to noise or other
considerations, to increase the oscillator frequency. This is
achievedby overdriving the oscillator from an external clock, as
shown in Figure 20. In order to prevent possibledevicelatchup,
a 1kΩ resistor must be used in series with the clock output. In
the situation where the designer has generated the external
clock frequency using TTL logic, the addition of a 10kΩ pullup
resistor to V+ supply is required. Note that the pump frequency
with external clocking, as with internal clocking, will be 1/2 of
the clock frequency. Output transitions occur on the positive­going edge of the clock.

+

V

10µF

1
2

+

-

ICL7662

3
4

8

1kΩ

7
6
5

-

10µF

+

FIGURE 20. EXTERNAL CLOCKING

It is also possible to increase the conversion efficiency of the
ICL7662 at low load levels b y lo wering the oscillator frequency.
This reduces the switching losses, and is achie v ed b y
connecting an additional capacitor, COSC , as shown in Figure

21. Howev er, lowering the oscillator frequency will cause an
undesirable increase in the impedance of the pump (C
reservoir (C
values of C

) capacitors; this is overcome by increasing the

2

and C2 by the same factor that the frequency has

1

been reduced. For example , the addition of a 100pF capacitor
between pin 7 (OSC) and V+ will lower the oscillator frequency
to 1kHz from its nominal frequency of 10kHz (a multiple of 10),
and thereby necessitate a corresponding increase in the value
of C

and C2 (from 10mF to 100mF).

1

V

V

OUT

+

CMOS
GATE

) and

1

V+

-

10µF

+

1
2
3
4

ICL7662

“N”

C

+

-

8
7
6

V

ICL7662

OUT

+

V

8
7
6
5

C

OSC

­C

2

+

5

+

1

-

-

10µF

+

1
2
3
4

FIGURE 21. LOWERING OSCILLATOR FREQUENCY

Positive Voltage Doubling

The ICL7662 may be employed to achieve positive voltage
doubling using the circuit shown in Figure 22. In this
application, the pump inverter switches of the ICL7662 are
used to charge C
the supply voltage and V
diode D

). On the transfer cycle, the voltage on C1 plus the

1

supply voltage (V+) is applied through diode C
C

. The voltage thus created on C2becomes (2V+) (2VF)or

2

twice the supply voltageminus the combined forward voltage
drops of diodes D

The source impedance of the output (V
the output current, but for V+ = 15V and an output current of
10mA it will be approximately 70Ω.

1
2
3
4

NOTE: D1 and D2 can be any suitable diode.

FIGURE 22. POSITIVE VOLTAGE DOUBLER

to a voltage level of V+ -VF (where V+ is

1

1

ICL7662

is the forward voltage drop of

F

and D2.

OUT

V+

8
7
6
5

D

1

D

2

+

-

) will depend on

C

1

V

OUT

to capacitor

2

V

=

OUT

(2V+) - (2V

+

C

2

-

)

F

3-53

ICL7662

V+

1
2

+

-

C

1

ICL7662

3
4

-

C

8
7
6
5

+

2

D

1

D

2

-

+

V
(V

+

-

V

OUT

- (nV

C

OUT

FD1

C

=

- V

IN

3

= (2V+) -

) - (V

4

FDX

FD2

FIGURE 23. COMBINED NEGATIVE CONVERTER

AND POSITIVE DOUBLER

Combined Negative Voltage Conversion and Posi­tive Supply Doubling

Figure 23 combines the functions shown in Figure 16 and
Figure 22 to provide negative voltage conversion and
positive voltage doubling simultaneously. This approach
would be, for example, suitable for generating +9V and -5V
from an existing +5V supply. In this instance capacitors C

1

and C3 perform the pump and reservoir functions
respectively for the generation of the negative voltage, while
capacitors C

and C4 are pump and reservoir respectively

2

for the doubled positive voltage. There is a penalty in this
configuration which combines both functions, however, in
that the source impedances of the generated supplies will be
somewhat higher due to the finite impedance of the common
charge pump driver at pin 2 of the device.

Voltage Splitting

The bidirectional characteristics can also be used to split a
higher supply in half, as shown in Figure 24. The combined
load will be evenly shared between the two sides and, a high
value resistor to the LV pin ensures start-up. Because the
switches share the load in parallel, the output impedance is
much lower than in the standard circuits, and higher currents
can be drawn from the device. By using this circuit, and then
the circuit of Figure 19, +30V can be converted (via +15V,
and -15V) to a nominal -30V, although with rather high series
output resistance (~250Ω).

Regulated Negative Voltage Supply

In some cases, the output impedance of the ICL7662 can be a
problem, particularly if the load current varies substantially.The
circuit of Figure 25 can be used to overcome this by controlling

the input voltage, via an ICL7611 low-pow er CMOS op amp , in

)

such a way as to maintain a nearly constant output voltage.
Direct feedbackis inadvisable,since the ICL7662s output does
not respond instantaneously to a change in input, but only after
the switchingdelay. The circuit shown supplies enough delay to
accommodate the ICL7662, while maintaining adequate
feedback. An increase in pump and storage capacitors is

)

desirable,and the values shown provides an output impedance
of less than 5Ω to a load of 10mA.

Other Applications

Further information on the operation and use of the ICL7662
may be found in AN051 “Principles and Applications of the
ICL7660 CMOS Voltage Converter”.

-

10µF

+

-

100µF

+

V+

V-

V

OUT

+

V+ - V-

=

2

50µF

50µF

50µF

­1

2

+

-

+

-

ICL7662

3
4

8
7
6
5

R

V

R

L1

OUT

L2

FIGURE 24. SPLITTING A SUPPLY IN HALF

+8V

56K

50K

100K

ICL8069

50K

-

ICL7611

+

100µF

+8V

+

-

800K

1
2
3
4

100Ω

ICL7662

250K

VOLTAGE

ADJUST

8
7
6
5

FIGURE 25. REGULATING THE OUTPUT VOLTAGE

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.

Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with­out notice. Accordingly,the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see web site http://www.intersil.com

3-54