Datasheet ICL7660SCPAZ Specification

®

ICL7660, ICL7660A

Data Sheet October 10, 2005

CMOS Voltage Converters

The Intersil ICL7660 and ICL7660A are monolithic CMOS
power supply circuits which offer unique performance
advantages over previously available devices. The ICL7660
performs supply voltage conversions from positive to
negative for an input range of +1.5V to +10.0V resulting in
complementary output voltages of -1.5V to -10.0V and the
ICL7660A does the same conversions with an input range of
+1.5V to +12.0V resulting in complementary output voltages
of -1.5V to -12.0V. Only 2 noncritical external capacitors are
needed for the charge pump and charge reservoir functions.
The ICL7660 and ICL7660A can also be connected to
function as voltage doublers and will generate output
voltages up to +18.6V with a +10V input.

Contained on the chip are a series DC supply regulator, RC
oscillator, voltage level translator, and four output power
MOS switches. A unique logic element senses the most
negative voltage in the device and ensures that the output
N-Channel switch source-substrate junctions are not forward
biased. This assures latchup free operation.

The oscillator, when unloaded, oscillates at a nominal
frequency of 10kHz for an input supply voltage of 5.0V. This
frequency can be lowered by the addition of an external
capacitor to the “OSC” terminal, or the oscillator may be
overdriven by an external clock.

FN3072.7

Features

• Simple Conversion of +5V Logic Supply to ±5V Supplies

• Simple Voltage Multiplication (V

= (-) nVIN)

OUT

• Typical Open Circuit Voltage Conversion Efficiency 99.9%

• Typical Power Efficiency 98%

• Wide Operating Voltage Range

- ICL7660 . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5V to 10.0V

- ICL7660A . . . . . . . . . . . . . . . . . . . . . . . . . 1.5V to 12.0V

• ICL7660A 100% Tested at 3V

• Easy to Use - Requires Only 2 External Non-Critical
Passive Components

• No External Diode Over Full Temp. and Voltage Range

• Pb-Free Plus Anneal Available (RoHS Compliant)

Applications

• On Board Negative Supply for Dynamic RAMs

• Localized µProcessor (8080 Type) Negative Supplies

• Inexpensive Negative Supplies

• Data Acquisition Systems

The “LV” terminal may be tied to GROUND to bypass the
internal series regulator and improve low voltage (LV)
operation. At medium to high voltages (+3.5V to +10.0V for
the ICL7660 and +3.5V to +12.0V for the ICL7660A), the LV
pin is left floating to prevent device latchup.

Pinouts

ICL7660, ICL7660A

(8 LD PDIP, SOIC)

TOP VIEW

NC

CAP+

GND

CAP-

1
2
3
4

8

V+

7

OSC

6

LV

5

V

OUT

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

Copyright © Intersil Americas Inc. 1999-2004, 2005. All Rights Reserved

All other trademarks mentioned are the property of their respective owners.

ICL7660, ICL7660A

Ordering Information

PART NUMBER TEMP. RANGE (°C) PACKAGE PKG. DWG. #

ICL7660CBA* 7660CBA 0 to 70 8 Ld SOIC (N) M8.15

ICL7660CBAZ* (See Note) 7660CBAZ 0 to 70 8 Ld SOIC (N) (Pb-free) M8.15

ICL7660CBAZA* (See Note) 7660CBAZ 0 to 70 8 Ld SOIC (N) (Pb-free) M8.15

ICL7660CPA 7660CPA 0 to 70 8 Ld PDIP E8.3

ICL7660CPAZ ( See Note) 7660CPAZ 0 to 70 8 Ld PDIP** (Pb-free) E8.3

ICL7660ACBA* 7660ACBA 0 to 70 8 Ld SOIC (N) M8.15

ICL7660ACBAZA* (See Note) 7660ACBAZ 0 to 70 8 Ld SOIC (N) (Pb-free) M8.15

ICL7660ACPA 7660ACPA 0 to 70 8 Ld PDIP E8.3

ICL7660ACPAZ (See Note) 7660ACPAZ 0 to 70 8 Ld PDIP** (Pb-free) E8.3

ICL7660AIBA* 7660AIBA -40 to 85 8 Ld SOIC (N) M8.15

ICL7660AIBAZA* (See Note) 7660AIBAZ -40 to 85 8 Ld SOIC (N) (Pb-free) M8.15

*Add “-T” suffix to part number for tape and reel packaging.

**Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications.

NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

2

FN3072.7

October 10, 2005

ICL7660, ICL7660A

C

Absolute Maximum Ratings Thermal Information

Supply Voltage

ICL7660 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +10.5V

ICL7660A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +13.0V

LV and OSC Input Voltage. . . . . . -0.3V to (V+ +0.3V) for V+ < 5.5V

(Note 2) . . . . . . . . . . . . . . (V+ -5.5V) to (V+ +0.3V) for V+ > 5.5V

Current into LV (Note 2). . . . . . . . . . . . . . . . . . . 20µA for V+ > 3.5V

Output Short Duration (V

≤ 5.5V) . . . . . . . . . . . .Continuous

SUPPLY

Operating Conditions

Temperature Range

ICL7660C, ICL7660AC. . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C

ICL7660AI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to 85°C

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

is measured with the component mounted on an evaluation PC board in free air.

1. θ

JA

Thermal Resistance (Typical, Note 1) θ

(°C/W) θJC (°C/W)

JA

PDIP Package* . . . . . . . . . . . . . . . . . . 110 N/A

SOIC Package . . . . . . . . . . . . . . . . . . . 160 N/A

Maximum Storage Temperature Range. . . . . . . . . . . -65°C to 150°C

Maximum Lead Temperature (Soldering, 10s). . . . . . . . . . . . . 300°C

(SOIC - Lead Tips Only)

*Pb-free PDIPs can be used for through hole wave solder processing
only. They are not intended for use in Reflow solder processing
applications.

Electrical Specifications ICL7660 and ICL7660A, V+ = 5V, T

Unless Otherwise Specified

PARAMETER SYMBOL TEST CONDITIONS

Supply Current I+ R

Supply Voltage Range - Lo V

Supply Voltage Range - Hi V

Output Source Resistance R

Oscillator Frequency f

Power Efficiency P

Voltage Conversion Efficiency V

Oscillator Impedance Z

ICL7660A, V+ = 3V, T

= 25°C, OSC = Free running, Test Circuit Figure 11, Unless Otherwise Specified

A

+MIN ≤ TA ≤ MAX, RL = 10kΩ, LV to GND 1.5 - 3.5 1.5 - 3.5 V

L

+MIN ≤ TA ≤ MAX, RL = 10kΩ, LV to Open 3.0 - 10.0 3 - 12 V

H

OUTIOUT

OSC

EF

OUT EFRL

OSC

Supply Current (Note 3) I+ V+ = 3V, R

Output Source Resistance R

Oscillator Frequency (Note 3) f

OUT

OSC

= ∞ - 170 500 - 80 165 µA

L

= 20mA, TA = 25°C - 55 100 - 60 100 Ω

= 20mA, 0°C ≤ TA ≤ 70°C - - 120 - - 120 Ω

I

OUT

= 20mA, -55°C ≤ TA ≤ 125°C - - 150 - - - Ω

I

OUT

= 20mA, -40°C ≤ TA ≤ 85°C - - - - - 120 Ω

I

OUT

+

= 2V, I

V
0°C ≤ T

V+ = 2V, I

-55°C ≤ T

= 3mA, LV to GND

OUT

≤ 70°C

A

= 3mA, LV to GND,

OUT

≤ 125°C

A

RL = 5kΩ 95 98 - 96 98 - %

= ∞ 97 99.9 - 99 99.9 - %

V+ = 2V - 1.0 - - 1 - MΩ

V = 5V - 100 - - - - kΩ

= ∞, 25°C - - - - 26 100 µA

L

0°C < T

-40°C < T

V+ = 3V, I

0°C < T

-40°C < T

< 70°C - - - - - 125 µA

A

< 85°C - - - - - 125 µA

A

= 10mA - - - - 97 150 Ω

OUT

< 70°C - - - - - 200 Ω

A

< 85°C - - - - - 200 Ω

A

V+ = 3V (same as 5V conditions) - - - 5.0 8 - kHz

0°C < T

-40°C < T

< 70°C ---3.0--kHz

A

< 85°C ---3.0--kHz

A

= 25°C, C

A

= 0, Test Circuit Figure 11

OSC

ICL7660 ICL7660A

- - 300 - - 300 Ω

- - 400 - - - Ω

-10- -10-kHz

UNITSMIN TYP MAX MIN TYP MAX

3

FN3072.7

October 10, 2005

ICL7660, ICL7660A

Electrical Specifications ICL7660 and ICL7660A, V+ = 5V, T

Unless Otherwise Specified (Continued)

= 25°C, C

A

= 0, Test Circuit Figure 11

OSC

ICL7660 ICL7660A

PARAMETER SYMBOL TEST CONDITIONS

Voltage Conversion Efficiency V

OUT

Power Efficiency P

EFF V+ = 3V, RL = ∞ ---99--%

< TA < T

T

MIN

V+ = 3V, RL = 5kΩ ---96--%

EFF

< TA < T

T

MIN

MAX

MAX

---99--%

---95--%

UNITSMIN TYP MAX MIN TYP MAX

NOTES:

2. Connecting any input terminal to voltages greater than V+ or less than GND may cause destructive latchup. It is recommended that no inputs
from sources operating from external supplies be applied prior to “power up” of the ICL7660, ICL7660A.

3. Derate linearly above 50°C by 5.5mW/°C.

4. In the test circuit, there is no external capacitor applied to pin 7. However, when the device is plugged into a test socket, there is usually a very
small but finite stray capacitance present, of the order of 5pF.

5. The Intersil ICL7660A can operate without an external diode over the full temperature and voltage range. This device will function in existing
designs which incorporate an external diode with no degradation in overall circuit performance.

Functional Block Diagram

V+

CAP+

RC

OSCILLATOR

÷2

VOLTAGE

LEVEL

TRANSLATOR

CAP-

OSC LV

VOLTAGE

REGULATOR

Typical Performance Curves (Test Circuit of Figure 11)

10

8

6

4

SUPPLY VOLTAGE (V)

2

0

-55 -25 0 25 50 100 125

FIGURE 1. OPERATING VOLTAGE AS A FUNCTION OF

TEMPERATURE

SUPPLY VOLTAGE RANGE

(NO DIODE REQUIRED)

TEMPERATURE (

°C)

V

OUT

LOGIC

NETWORK

10K

TA = 25°C

1000

100

OUTPUT SOURCE RESISTANCE (Ω)

10

01 234 56 7 8

SUPPLY VOLTAGE (V+)

FIGURE 2. OUTPUT SOURCE RESISTANCE AS A FUNCTION

OF SUPPLY VOLTAGE

4

FN3072.7

October 10, 2005

ICL7660, ICL7660A

Typical Performance Curves (Test Circuit of Figure 11) (Continued)

350

300

250

200

150

100

50

OUTPUT SOURCE RESISTANCE (Ω)

0

-55 -25 0 25 50 75 100 125

I

= 1mA

OUT

TEMPERATURE (

V+ = +2V

V+ = 5V

°C)

FIGURE 3. OUTPUT SOURCE RESISTANCE AS A FUNCTION

OF TEMPERATURE

10K

(Hz)

OSC

1K

100

TA = 25°C

98

96

94

92

90

88

86

84

82

POWER CONVERSION EFFICIENCY (%)

80

100 1K 10K

V+ = +5V

I

= 1mA

OUT

OSC. FREQUENCY f

I

OUT

= 15mA

OSC

(Hz)

FIGURE 4. POWER CONVERSION EFFICIENCY AS A

FUNCTION OF OSC. FREQUENCY

20

18

(kHz)

OSC

16

14

100

V+ = 5V

OSCILLATOR FREQUENCY f

= 25°C

T

A

10

1.0 10 100 1000 10K

C

(pF)

OSC

FIGURE 5. FREQUENCY OF OSCILLATION AS A FUNCTION

OF EXTERNAL OSC. CAPACITANCE

5

TA = 25°C

4

V+ = +5V

3

2

1

0

-1

-2

OUTPUT VOLTAGE

-3

-4

-5

0 1020304050607080

SLOPE 55Ω

LOAD CURRENT IL (mA)

FIGURE 7. OUTPUT VOLTAGE AS A FUNCTION OF OUTPUT

CURRENT

12

10

8

OSCILLATOR FREQUENCY f

V+ = +5V

6

-50 -25 0 25 50 75 100 125

TEMPERATURE (°C)

FIGURE 6. UNLOADED OSCILLATOR FREQUENCY AS A

FUNCTION OF TEMPERATURE

100

90

80

70

60

50

40

30

20

10

POWER CONVERSION EFFICIENCY (%)

0

P

EFF

TA = 25°C
V+ = +5V

0 102030405060

LOAD CURRENT IL (mA)

100

90

+

I

80

70

60

50

40

30

20

10

0

FIGURE 8. SUPPLY CURRENT AND POWER CONVERSION

EFFICIENCY AS A FUNCTION OF LOAD
CURRENT

SUPPLY CURRENT I+ (mA)

5

FN3072.7

October 10, 2005

ICL7660, ICL7660A

Typical Performance Curves (Test Circuit of Figure 11) (Continued)

+2

TA = 25°C
V+ = 2V

+1

0

OUTPUT VOLTAGE

-1

SLOPE 150Ω

-2
012345678

LOAD CURRENT I

L

(mA)

FIGURE 9. OUTPUT VOLTAGE AS A FUNCTION OF OUTPUT

CURRENT

100

90

80

70

60

50

40

30

20

10

POWER CONVERSION EFFICIENCY (%)

0

0 1.5 3.0 4.5 6.0 7.5 9.0

P

EFF

TA = 25°C
V+ = 2V

LOAD CURRENT IL (mA)

I+

FIGURE 10. SUPPLY CURRENT AND POWER CONVERSION

EFFICIENCY AS A FUNCTION OF LOAD
CURRENT

NOTE:

6. These curves include in the supply current that current fed directly into the load R

from the V+ (See Figure 11). Thus, approximately half the

L

supply current goes directly to the positive side of the load, and the other half, through the ICL7660/ICL7660A, to the negative side of the load.
Ideally, V

∼ 2VIN, IS ∼ 2IL, so VIN x IS ∼ V

OUT

C

10µF

x IL.

OUT

ISV+

1
2

+

1

-

3
4

ICL7660

ICL7660A

8
7
6
5

C

OSC

(NOTE)

(+5V)

I

L

R

L

-V

OUT

20.0

18.0

16.0

14.0

12.0

10.0

8.0

6.0

4.0

2.0

0

SUPPLY CURRENT (mA) (NOTE 6)

NOTE: For large values of C

(>1000pF) the values of C1 and C2 should be increased to 100µF.

OSC

FIGURE 11. ICL7660, ICL7660A TEST CIRCUIT

Detailed Description

The ICL7660 and ICL7660A contain all the necessary
circuitry to complete a negative voltage converter, with the
exception of 2 external capacitors which may be inexpensive
10µF polarized electrolytic types. The mode of operation of
the device may be best understood by considering Figure
12, which shows an idealized negative voltage converter.
Capacitor C
when switches S
and S
half cycle of operation, switches S
S

and S3 open, thereby shifting capacitor C1 negatively by

1

V+ volts. Charge is then transferred from C
the voltage on C
no load on C
more closely than existing non-mechanical circuits.

is charged to a voltage, V+, for the half cycle

1

and S3 are closed. (Note: Switches S2

are open during this half cycle.) During the second

4

1

and S4 are closed, with

2

to C2 such that

is exactly V+, assuming ideal switches and

2

. The ICL7660 approaches this ideal situation

2

1

-

C

2

10µF

+

In the ICL7660 and ICL7660A, the 4 switches of Figure 12
are MOS power switches; S
S

and S4 are N-Channel devices. The main difficulty with

3

is a P-Channel device and S2,

1

this approach is that in integrating the switches, the
substrates of S

and S4 must always remain reverse biased

3

with respect to their sources, but not so much as to degrade
their “ON” resistances. In addition, at circuit start-up, and
under output short circuit conditions (V

= V+), the output

OUT

voltage must be sensed and the substrate bias adjusted
accordingly. Failure to accomplish this would result in high
power losses and probable device latchup.

This problem is eliminated in the ICL7660 and ICL7660A by a
logic network which senses the output voltage (V
with the level translators, and switches the substrates of S
S

to the correct level to maintain necessary reverse bias.

4

OUT

) together

and

3

6

FN3072.7

October 10, 2005

ICL7660, ICL7660A

The voltage regulator portion of the ICL7660 and ICL7660A is
an integral part of the anti-latchup circuitry, however its inherent
voltage drop can degrade operation at low voltages. Therefore,
to improve low voltage operation the “LV” pin should be
connected to GROUND, disabling the regulator. For supply
voltages greater than 3.5V the LV terminal must be left open to
insure latchup proof operation, and prevent device damage.

8

V

IN

3

FIGURE 12. IDEALIZED NEGATIVE VOLTAGE CONVERTER

S

1

S

3

7

2

S

2

C

1

S

4

3

C

2

5

V

= -V

OUT

IN

Theoretical Power Efficiency
Considerations

In theory a voltage converter can approach 100% efficiency
if certain conditions are met.

1. The driver circuitry consumes minimal power.

2. The output switches have extremely low ON resistance
and virtually no offset.

3. The impedances of the pump and reservoir capacitors
are negligible at the pump frequency.

The ICL7660 and ICL7660A approach these conditions for
negative voltage conversion if large values of C
are used.

and C2

1

ENERGY IS LOST ONLY IN THE TRANSFER OF
CHARGE BETWEEN CAPACITORS IF A CHANGE IN
VOLTAGE OCCURS. The energy lost is defined by:

E =

1

/2 C1 (V

2

2

- V

1

)

2

where V1 and V2 are the voltages on C1 during the pump and
transfer cycles. If the impedances of C

and C2 are relatively

1

high at the pump frequency (refer to Figure 12) compared to
the value of R
voltages V
C

as large as possible to eliminate output voltage ripple, but

2

also to employ a correspondingly large value for C

, there will be a substantial difference in the

L

and V2. Therefore it is not only desirable to make

1

in order to

1

achieve maximum efficiency of operation.

Do’s And Don’ts

1. Do not exceed maximum supply voltages.

2. Do not connect LV terminal to GROUND for supply
voltages greater than 3.5V.

3. Do not short circuit the output to V+ supply for supply
voltages above 5.5V for extended periods, however,
transient conditions including start-up are okay.

4. When using polarized capacitors, the + terminal of C
must be connected to pin 2 of the ICL7660 and ICL7660A
and the + terminal of C

must be connected to GROUND.

2

5. If the voltage supply driving the ICL7660 and ICL7660A
has a large source impedance (25Ω - 30Ω), then a 2.2µF
capacitor from pin 8 to ground may be required to limit
rate of rise of input voltage to less than 2V/µs.

6. User should insure that the output (pin 5) does not go
more positive than GND (pin 3). Device latch up will occur
under these conditions. A 1N914 or similar diode placed
in parallel with C2 will prevent the device from latching up
under these conditions. (Anode pin 5, Cathode pin 3).

1

10µF

V+

1
2

+

-

ICL7660

ICL7660A

3
4

FIGURE 13A. CONFIGURATION FIGURE 13B. THEVENIN EQUIVALENT

8
7
6
5

10µF

V

= -V+

-

+

OUT

FIGURE 13. SIMPLE NEGATIVE CONVERTER

V+

R

O

-

+

7

V

OUT

FN3072.7

October 10, 2005

ICL7660, ICL7660A

10µF

t

1

V

0

-(V+)

t

2

B

A

FIGURE 14. OUTPUT RIPPLE

1
2

ICL7660

ICL7660A

C

1

3

“1”

4

8
7
6
5

V+

1
2

ICL7660

C

1

3
4

ICL7660A

“n”

8

R

7
6
5

-

C

2

+

L

FIGURE 15. PARALLELING DEVICES

1

ICL7660

2

+

-

3
4

ICL7660A

“1”

V+

8
7
6

10µF

10µF

+

-

-

+

5

1
2
3
4

ICL7660

ICL7660A

“n”

8
7
6
5

10µF

= -nV+

V

-

+

OUT

FIGURE 16. CASCADING DEVICES FOR INCREASED OUTPUT VOLTAGE

Typical Applications

Simple Negative Voltage Converter

The majority of applications will undoubtedly utilize the ICL7660
and ICL7660A for generation of negative supply voltages.
Figure 13 shows typical connections to provide a negative
supply negative (GND) for supply voltages below 3.5V.

The output characteristics of the circuit in Figure 13A can be
approximated by an ideal voltage source in series with a
resistance as shown in Figure 13B. The voltage source has
a value of -V+. The output impedance (R
the ON resistance of the internal MOS switches (shown in
Figure 12), the switching frequency, the value of C
and the ESR (equivalent series resistance) of C1 and C2. A
good first order approximation for R

2(R

RO ≅

2(R

SW1

SW2

+ R

+ R

+ ESRC1) +

SW3

+ ESRC1) +

SW4

8

) is a function of

O

is:

O

and C2,

1

2(R

(f

PUMP

RO ≅

SW1

(f

PUMP

f

=

OSC

Combining the four R

RO ≅

2 (RSW) +

+ R

1

2

+ ESRC1) +

SW3

+ ESR

) (C1)

terms as RSW, we see that:

SWX

C2

, R

= MOSFET switch resistance)

SWX

1

(f

) (C1)

PUMP

+ 4 (ESRC1) + ESR

C2

RSW, the total switch resistance, is a function of supply
voltage and temperature (See the Output Source Resistance
graphs), typically 23Ω at 25°C and 5V. Careful selection of
C

and C2 will reduce the remaining terms, minimizing the

1

output impedance. High value capacitors will reduce the
1/(f

• C1) component, and low ESR capacitors will

PUMP

lower the ESR term. Increasing the oscillator frequency will
reduce the 1/(f
of a net increase in output impedance when C

• C1) term, but may have the side effect

PUMP

1

> 10µF and

there is no longer enough time to fully charge the capacitors

FN3072.7

October 10, 2005

ICL7660, ICL7660A

every cycle. In a typical application where f
C = C

= C2 = 10µF:

1

2 (23) +

≅

R

O

R

≅ 46 + 20 + 5 (ESRC)

O

1

(5 • 103) (10-5)

+ 4 (ESRC1) + ESR

= 10kHz and

OSC

C2

Since the ESRs of the capacitors are reflected in the output
impedance multiplied by a factor of 5, a high value could
potentially swamp out a low 1/(f

• C1) term, rendering an

PUMP

increase in switching frequency or filter capacitance ineffective.
Typical electrolytic capacitors may have ESRs as high as 10Ω.

2 (23) +

RO ≅

R

≅ 46 + 20 + 5 (ESRC)

O/

1

(5 • 103) (10-5)

+ 4 (ESRC1) + ESR

C2

Since the ESRs of the capacitors are reflected in the output
impedance multiplied by a factor of 5, a high value could
potentially swamp out a low 1/(f

• C1) term, rendering an

PUMP

increase in switching frequency or filter capacitance ineffective.
Typical electrolytic capacitors may have ESRs as high as 10Ω.

Output Ripple

ESR also affects the ripple voltage seen at the output. The
total ripple is determined by 2 voltages, A and B, as shown in
Figure 14. Segment A is the voltage drop across the ESR of
C

at the instant it goes from being charged by C1 (current

2

flow into C
flowing out of C
2• I

OUT

B is the voltage change across C
the cycle when C
is l

OUT

of these voltage drops:

V

RIPPLE

) to being discharged through the load (current

2

). The magnitude of this current change is

, hence the total drop is 2• I

2

supplies current to the load. The drop at B

2

• eSRC2V. Segment

OUT

during time t2, the half of

2

• t2/C2V. The peak-to-peak ripple voltage is the sum

1

2 (f

[

≅

PUMP

) (C2)

+ 2 (ESR

C2

)]I

OUT

Cascading Devices

The ICL7660 and ICL7660A may be cascaded as shown to
produced larger negative multiplication of the initial supply
voltage. However, due to the finite efficiency of each device,
the practical limit is 10 devices for light loads. The output
voltage is defined by:

V

= -n (VIN),

OUT

where n is an integer representing the number of devices
cascaded. The resulting output resistance would be
approximately the weighted sum of the individual ICL7660
and ICL7660A R

OUT

values.

Changing the ICL7660/ICL7660A Oscillator
Frequency

It may be desirable in some applications, due to noise or
other considerations, to increase the oscillator frequency.
This is achieved by overdriving the oscillator from an
external clock, as shown in Figure 17. In order to prevent
possible device latchup, a 1kΩ resistor must be used in
series with the clock output. In a situation where the
designer has generated the external clock frequency using
TTL logic, the addition of a 10kΩ pullup resistor to V+ supply
is required. Note that the pump frequency with external
clocking, as with internal clocking, will be
frequency. Output transitions occur on the positive-going
edge of the clock.

10µF

1
2
3
4

ICL7660

ICL7660A

+

-

FIGURE 17. EXTERNAL CLOCKING

8
7
6
5

1

/2 of the clock

V+

1kΩ

-

10µF

+

V

V+

OUT

CMOS
GATE

Again, a low ESR capacitor will reset in a higher
performance output.

Paralleling Devices

Any number of ICL7660 and ICL7660A voltage converters
may be paralleled to reduce output resistance. The reservoir
capacitor, C
its own pump capacitor, C
would be approximately:

R

OUT

, serves all devices while each device requires

2

R

(of ICL7660/ICL7660A)

OUT

=

n (number of devices)

. The resultant output resistance

1

9

It is also possible to increase the conversion efficiency of the
ICL7660 and ICL7660A at low load levels by lowering the
oscillator frequency. This reduces the switching losses, and is
shown in Figure 18. However, lowering the oscillator
frequency will cause an undesirable increase in the
impedance of the pump (C
this is overcome by increasing the values of C

) and reservoir (C2) capacitors;

1

and C2 by the

1

same factor that the frequency has been reduced. For
example, the addition of a 100pF capacitor between pin 7
(OSC) and V+ will lower the oscillator frequency to 1kHz from
its nominal frequency of 10kHz (a multiple of 10), and thereby
necessitate a corresponding increase in the value of C
C

(from 10µF to 100µF).

2

and

1

FN3072.7

October 10, 2005

ICL7660, ICL7660A

V+

1
2
3
4

ICL7660

ICL7660A

+

C

1

-

8
7
6
5

C

OSC

V

-

+

OUT

C

2

FIGURE 18. LOWERING OSCILLATOR FREQUENCY

Positive Voltage Doubling

The ICL7660 and ICL7660A may be employed to achieve
positive voltage doubling using the circuit shown in Figure

19. In this application, the pump inverter switches of the
ICL7660 and ICL7660A are used to charge C
level of V+ -V
forward voltage drop of diode D
voltage on C
diode D

(where V+ is the supply voltage and VF is the

F

plus the supply voltage (V+) is applied through

1

to capacitor C2. The voltage thus created on C2

2

). On the transfer cycle, the

1

becomes (2V+) - (2VF) or twice the supply voltage minus the
combined forward voltage drops of diodes D

The source impedance of the output (V
the output current, but for V+ = 5V and an output current of
10mA it will be approximately 60Ω.

V+

1
2
3
4

ICL7660

ICL7660A

8
7
6
5

D

D

+

-

FIGURE 19. POSITIVE VOLT DOUBLER

to a voltage

1

and D2.

1

) will depend on

OUT

1

V

2

C

(2V+) - (2V

1

+

-

OUT

C

=

)

F

2

V+

1
2
3
4

ICL7660

ICL7660A

+

-

C

1

-

C

8
7
6
5

+

2

D

1

D

2

V

- (nV

-

+

V
(V

+

-

OUT

OUT

IN

C

3

= (2V+) -

) - (V

FD1

C

4

=

- V

FDX

FD2

FIGURE 20. COMBINED NEGATIVE VOLTAGE CONVERTER

AND POSITIVE DOUBLER

Voltage Splitting

The bidirectional characteristics can also be used to split a
higher supply in half, as shown in Figure 21. The combined
load will be evenly shared between the two sides. Because
the switches share the load in parallel, the output impedance
is much lower than in the standard circuits, and higher
currents can be drawn from the device. By using this circuit,
and then the circuit of Figure 16, +15V can be converted (via
+7.5, and -7.5) to a nominal -15V, although with rather high
series output resistance (

R

L1

V

OUT

R

L2

50µF

V+ - V-

=

2

50µF

50µF

FIGURE 21. SPLITTING A SUPPLY IN HALF

+

-

+

-

+

-

~250Ω).

1
2
3
4

ICL7660

ICL7660A

V+

8
7
6
5

V

-

)

)

Combined Negative Voltage Conversion
and Positive Supply Doubling

Figure 20 combines the functions shown in Figures 13 and
Figure 19 to provide negative voltage conversion and
positive voltage doubling simultaneously. This approach
would be, for example, suitable for generating +9V and -5V
from an existing +5V supply. In this instance capacitors C
and C

perform the pump and reservoir functions

3

respectively for the generation of the negative voltage, while
capacitors C

and C4 are pump and reservoir respectively

2

for the doubled positive voltage. There is a penalty in this
configuration which combines both functions, however, in
that the source impedances of the generated supplies will be
somewhat higher due to the finite impedance of the common
charge pump driver at pin 2 of the device.

10

1

Regulated Negative Voltage Supply

In some cases, the output impedance of the ICL7660 and
ICL7660A can be a problem, particularly if the load current
varies substantially. The circuit of Figure 22 can be used to
overcome this by controlling the input voltage, via an ICL7611
low-power CMOS op amp, in such a way as to maintain a
nearly constant output voltage. Direct feedback is inadvisable,
since the ICL7660s and ICL7660As output does not respond
instantaneously to change in input, but only after the switching
delay. The circuit shown supplies enough delay to
accommodate the ICL7660 and ICL7660A, while maintaining
adequate feedback. An increase in pump and storage
capacitors is desirable, and the values shown provides an
output impedance of less than 5Ω to a load of 10mA.

FN3072.7

October 10, 2005

ICL7660, ICL7660A

Other Applications

Further information on the operation and use of the ICL7660
and ICL7660A may be found in AN051 “Principals and
Applications of the ICL7660 and ICL7660A CMOS Voltage
Converter”.

+5V LOGIC SUPPLY

TTL DATA

INPUT

+

10µF

-

1
2
3
4

ICL7660

ICL7660A

8
7
6
5

10µF

16

4

15

-

+

12 11

IH5142

13

+8V

56K

50K

50K

+8V

100Ω

-

100K

ICL8069

FIGURE 22. REGULATING THE OUTPUT VOLTAGE

14

ICL7611

+

1
2

+5V

-5V

3
4

ICL7660

ICL7660A

250K

VOLTAGE

ADJUST

100µF

1

3

+

-

800K

RS232
DATA
OUTPUT

-

10µF

+

8
7
6
5

-

100µF

+

V

OUT

FIGURE 23. RS232 LEVELS FROM A SINGLE 5V SUPPLY

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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
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11

FN3072.7

October 10, 2005