Datasheet ICL7136CPLZ Specification

®

ICL7136

Data Sheet July 21, 2005

31/2 Digit LCD, Low Power Display, A/D
Converter with Overrange Recovery

The Intersil ICL7136 is a high performance, low power 31/2
digit, A/D converter. Included are seven segment decoders,
display drivers, a reference, and a clock. The ICL7136 is
designed to interface with a liquid crystal display (LCD) and
includes a multiplexed backplane drive.

The ICL7136 brings together a combination of high
accuracy, versatility, and true economy. It features auto-zero
to less than 10µV, zero drift of less than 1µV/
current of 10pA (Max), and rollover error of less than one
count. True differential inputs and reference are useful in all
systems, but give the designer an uncommon advantage
when measuring load cells, strain gauges and other bridge
type transducers. Finally, the true economy of single power
supply operation, enables a high performance panel meter
to be built with the addition of only 10 passive components
and a display.

The ICL7136 is an improved version of the ICL7126,
eliminating the overrange hangover and hysteresis effects,
and should be used in its place in all applications. It can also
be used as a plug-in replacement for the ICL7106 in a wide
variety of applications, changing only the passive
components.

o

C, input bias

FN3086.6

Features

• First Reading Overrange Recovery in One Conversion
Period

• Guaranteed Zero Reading for 0V Input on All Scales

• True Polarity at Zero for Precise Null Detection

• 1pA Typical Input Current

• True Differential Input and Reference, Direct Display Drive

- LCD ICL7136

• Low Noise - Less Than 15µV

P-P

• On Chip Clock and Reference

• No Additional Active Circuits Required

• Low Power - Less Than 1mW

• Surface Mount Package Available

• Drop-In Replacement for ICL7126, No Changes Needed

• Pb-Free Plus Anneal Available (RoHS Compliant)

Ordering Information

TEMP.

PART NUMBER

ICL7136CPL 0 to 70 40 Ld PDIP E40.6

ICL7136CPLZ
(Note 1)

ICL7136CM44 0 to 70 44 Ld MQFP Q44.10x10

ICL7136CM44Z
(Note 1)

ICL7136CM44ZT
(Note 1)

NOTES:

1. Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and
100% matte tin plate termination finish, which are RoHS
compliant and compatible with both SnPb and Pb-free soldering
operations. Intersil Pb-free products are MSL classified at
Pb-free peak reflow temperatures that meet or exceed the
Pb-free requirements of IPC/JEDEC J STD-020.

2. Pb-free PDIPs can be used for through hole wave solder
processing only. They are not intended for use in Reflow solder
processing applications.

RANGE (°C) PACKAGE

0 to 70 40 Ld PDIP

(Pb-free) (Note 2)

0 to 70 44 Ld MQFP

(Pb-free)

44 Ld MQFP Tape and Reel
(Pb-free)

PKG.

DWG. #

E40.6

Q44.10x10

Q44.10x10

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

Copyright Intersil Americas Inc. 2002, 2004, 2005. All Rights Reserved

All other trademarks mentioned are the property of their respective owners.

Pinouts

(100’s)

(MINUS) POL

(1’s)

(10’s)

(1000) AB4

V+
D1
C1
B1
A1
F1
G1
E1
D2
C2
B2
A2
F2
E2
D3
B3
F3
E3

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20

(PDIP)

TOP VIEW

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

OSC 1
OSC 2
OSC 3
TEST
REF HI
REF LO
C

+

REF

C

-

REF

COMMON
IN HI
IN LO
A-Z
BUFF
INT
V­G2 (10’s)
C3

(100’s)

A3
G3
BP/GND

ICL7136

NC

NC

TEST

OSC 3

NC

OSC 2

OSC 1

V+

D1

C1

B1

(MQFP)

TOP VIEW

+

-

REF

REF

C

REF HI

REF LO

44 43 42 41 40

1

2

3

4

5

6

7

8

9

10

11

12 13 14 15 16 17

A1 F1 G1 E1 D2 C2

COMMON

C

IN HI

IN LO

A-Z

BUFF

INT

39 38 37 36 35 34

2221201918

B2 A2 F2 E2 D3

V-

33

32

31

30

29

28

27

26

25

24

23

NC

G2

C3

A3

G3

BP/GND

POL

AB4

E3

F3

B3

2

FN3086.6

July 21, 2005

ICL7136

Absolute Maximum Ratings Thermal Information

Supply Voltage

ICL7136, V+ to V-. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15V

Analog Input Voltage (Either Input) (Note 1) . . . . . . . . . . . . V+ to V-

Reference Input Voltage (Either Input). . . . . . . . . . . . . . . . . V+ to V-

Clock Input

ICL7136 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TEST to V+

Thermal Resistance (Typical, Note 2)

PDIP Package* . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

MQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150°C

Maximum Storage Temperature Range . . . . . . . . . . .-65

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C

(MQFP - Lead Tips Only)

Operating Conditions

Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

1. Input voltages may exceed the supply voltages provided the input current is limited to ±100µA.

is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

2. θ

JA

*Pb-free PDIPs can be used for through hole wave solder
processing only. They are not intended for use in Reflow solder
processing applications.

Electrical Specifications (Note 3)

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

SYSTEM PERFORMANCE

Zero Input Reading V

Ratiometric Reading V

Rollover Error -V

Linearity Full Scale = 200mV or Full Scale = 2V Maximum

Common Mode Rejection Ratio V

Noise V

Leakage Current Input V

Zero Reading Drift V

Scale Factor Temperature Coefficient V

COMMON Pin Analog Common Voltage 25kΩ Between Common and Positive Supply (With Respect

Temperature Coefficient of Analog
Common

SUPPLY CURRENT

V+ Supply Current V

DISPLAY DRIVER

Peak-To-Peak Segment Drive Voltage and
Peak-To-Peak Backplane Drive Voltage

NOTES:

3. Unless otherwise noted, specifications apply to the ICL7136 at TA = 25°C, f

4. Back plane drive is in phase with segment drive for “off“ segment, 180 degrees out of phase for “on“ segment. Frequency is 20 times conversion rate.
Average DC component is less than 50mV.

5. Not tested, guaranteed by design.

6. 48kHz oscillator increases current by 20µA (Typ).

= 0V, Full Scale = 200mV -000.0 ±000.0 +000.0 Digital

IN

= V

, V

lN

REF

= +VlN ≅ 200mV Difference in Reading for Equal Positive

IN

= 100mV 999 999/

REF

- ±0.2 ±1 Counts

1000

and Negative Inputs Near Full Scale

- ±0.2 ±1 Counts

Deviation from Best Straight Line Fit (Note 5)

= ±1V, VIN = 0V, Full Scale = 200mV (Note 5) - 50 - µV/V

CM

= 0V, Full Scale = 200mV (Peak-To-Peak Value Not

IN

Exceeded 95% of Time) (Note 5)

= 0V (Note 5) - 1 10 pA

lN

= 0V, 0°C To 70°C (Note 5) - 0.2 1 µV/°C

lN

= 199mV, 0°C To 70°C, (Ext. Ref. 0ppm/×°C) (Note 5) - 1 5 ppm/°C

IN

-15-µV

2.4 3.0 3.2 V

to + Supply)

25kΩ Between Common and Positive Supply (With Respect

- 150 - ppm/°C

to + Supply) (Note 5)

= 0 (Does Not Include Common Current) 16kHz

IN

Oscillator (Note 6)

- 70 100 µA

V+ to V- = 9V (Note 4) 4 5.5 6 V

= 48kHz. ICL7136 is tested in the circuit of Figure 1.

CLOCK

θ

(°C/W)

JA

o

C to 150°C

Reading

1000 Digital

Reading

3

FN3086.6

July 21, 2005

Typical Applications and Test Circuits

ICL7136

IN

C

5

C

2

IN HI

IN LO

101112

9V

+

-

R

2

C

3

28

29

27262524232221

V-

INT

A-Z

BUFF

13

14151617181920

DISPLAY

G2

C1= 0.1µF
C

= 0.47µF

2

C

= 0.047µF

3

C

C3

A3

G3

BP

E3

AB4

POL

4

C

5

R

1

R

2

R

3

R

4

R

5

= 50pF
= 0.01µF
= 240kΩ
= 180kΩ
= 180kΩ
= 10kΩ
= 1MΩ

+ -

R

C

+

REF

C

5

1

-

REF

COM

C

R

1

R

C

4

OSC 3

4

TEST

REF HI

REF LO

R

3

4039383736353433323130

OSC 1

OSC 2

ICL7136

V+D1C1B1A1F1G1E1D2C2B2A2F2E2D3B3F3
123456789

DISPLAY

FIGURE 1. ICL7136 TEST CIRCUIT AND TYPICAL APPLICATION WITH LCD DISPLAY COMPONENTS SELECTED FOR 200mV FULL SCALE

4

FN3086.6

July 21, 2005

Design Information Summary Sheet

• OSCILLATOR FREQUENCY

= 0.45/RC

f

OSC

C

> 50pF; R

OSC

(Typ) = 48kHz

f

OSC

• OSCILLATOR PERIOD

= RC/0.45

t

OSC

• INTEGRATION CLOCK FREQUENCY

= f

f

CLOCK

OSC

• INTEGRATION PERIOD

= 1000 x (4/f

t

INT

• 60/50Hz REJECTION CRITERION

t

INT/t60Hz

or t

• OPTIMUM INTEGRATION CURRENT

= 1µA

I

INT

• FULL SCALE ANALOG INPUT VOLTAGE

(Typ) = 200mV or 2V

V

lNFS

• INTEGRATE RESISTOR

V

INFS

INT

-----------------

=

I

INT

R

• INTEGRATE CAPACITOR

t

()I

()

INT

INT

--------------------------------

=

V

INT

C

• INTEGRATOR OUTPUT VOLTAGE SWING

t

()I

()

INT

--------------------------------

=

V

INT

C

INT

> 50kΩ

OSC

/4

OSC

lNT/t50Hz

INT

INT

)

= Integer

ICL7136

• DISPLAY COUNT

V

IN

---------------

COUNT 1000

• CONVERSION CYCLE

= t

t

CYC

t

= t

CYC

when f

OSC

• COMMON MODE INPUT VOLTAGE

(V- + 1V) < V

• AUTO-ZERO CAPACITOR

0.01µF < C

• REFERENCE CAPACITOR

0.1µF < C

•V

COM

Biased between V+ and V-.

•V

≅ V+ - 2.8V

COM

Regulation lost when V+ to V- < ≅6.8V.
If V

COM

the V

COM

• POWER SUPPLY: SINGLE 9V

V+ - V- = 9V
Digital supply is generated internally

≅ V+ - 4.5V

V

TEST

•DISPLAY:LCD

Type: Direct drive with digital logic supply amplitude.

×=

V

REF

x 4000

CL0CK

x 16,000

OSC

= 48kHz; t

< (V+ - 0.5V)

lN

< 1µF

AZ

< 1µF

REF

is externally pulled down to (V + to V -)/2,

circuit will turn off.

CYC

= 333ms

•V

MAXIMUM SWING:

INT

(V- + 0.5V) < V

< (V+ - 0.5V), V

INT

(Typ) = 2V

INT

Typical Integrator Amplifier Output Waveform (INT Pin)

AUTO ZERO PHASE

(COUNTS)
2999 - 1000

5

SIGNAL INTEGRATE

PHASE FIXED

1000 COUNTS

TOTAL CONVERSION TIME = 4000 x t

CLOCK

DE-INTEGRATE PHASE

0 - 1999 COUNTS

= 16,000 x t

OSC

FN3086.6

July 21, 2005

ICL7136

Pin Descriptions

PIN NUMBER

44 PIN

FLATPACK

1 8 V+ Supply Power Supply.
2 9 D1 Output Driver Pin for Segment “D” of the display units digit.
3 10 C1 Output Driver Pin for Segment “C” of the display units digit.
4 11 B1 Output Driver Pin for Segment “B” of the display units digit.
5 12 A1 Output Driver Pin for Segment “A” of the display units digit.
6 13 F1 Output Driver Pin for Segment “F” of the display units digit.
7 14 G1 Output Driver Pin for Segment “G” of the display units digit.
8 15 E1 Output Driver Pin for Segment “E” of the display units digit.

9 16 D2 Output Driver Pin for Segment “D” of the display tens digit.
10 17 C2 Output Driver Pin for Segment “C” of the display tens digit.
11 18 B2 Output Driver Pin for Segment “B” of the display tens digit.
12 19 A2 Output Driver Pin for Segment “A” of the display tens digit.
13 20 F2 Output Driver Pin for Segment “F” of the display tens digit.
14 21 E2 Output Driver Pin for Segment “E” of the display tens digit.
15 22 D3 Output Driver pin for segment “D” of the display hundreds digit.
16 23 B3 Output Driver pin for segment “B” of the display hundreds digit.
17 24 F3 Output Driver pin for segment “F” of the display hundreds digit.
18 25 E3 Output Driver pin for segment “E” of the display hundreds digit.
19 26 AB4 Output Driver pin for both “A” and “B” segments of the display thousands digit.
20 27 POL Output Driver pin for the negative sign of the display.
21 28 BP/GND Output Driver pin for the LCD backplane/Power Supply Ground.
22 29 G3 Output Driver pin for segment “G” of the display hundreds digit.
23 30 A3 Output Driver pin for segment “A” of the display hundreds digit.
24 31 C3 Output Driver pin for segment “C” of the display hundreds digit.
25 32 G2 Output Driver pin for segment “G” of the display tens digit.
26 34 V
27 35 INT Output Integrator amplifier output. To be connected to integrating capacitor.
28 36 BUFF Output Input buffer amplifier output. To be connected to integrating resistor.
29 37 A-Z Input Integrator amplifier input. To be connected to auto-zero capacitor.
30

31

32 40 COMMON Supply/

33
34

35
36

37 3 TEST Input Display test. Turns on all segments when tied to V+.
38

39
40

38
39

41
42

43
44

4
6
7

NAME FUNCTION DESCRIPTION40 PIN DIP

-

IN LO

IN HI

C

REF

C

REF

REF LO

REF HI

OSC3
OSC2
OSC1

Supply Negative power supply.

Input Differential inputs. To be connected to input voltage to be measured. LO and HI

designators are for reference and do not imply that LO should be connected to lower
potential, e.g., for negative inputs IN LO has a higher potential than IN HI.

Internal voltage reference output.

Output

-

+

Input Input pins for reference voltage to the device. REF HI should be positive reference to

Output
Output

Input

Connection pins for reference capacitor.

REF LO.

Device clock generator circuit connection pins.

Detailed Description

Analog Section

Figure 2 shows the Analog Section for the ICL7136. Each
measurement cycle is divided into four phases. They are (1)
auto-zero (A-Z), (2) signal integrate (INT) and (3) de­integrate (DE), (4) zero integrate (ZI).

Auto-Zero Phase

During auto-zero three things happen. First, input high and low
are disconnected from the pins and internally shorted to analog

6

COMMON. Second, the reference capacitor is charged to the
reference voltage. Third, a feedback loop is closed around the
system to charge the auto-zero capacitor C

to compensate

AZ

for offset voltages in the buffer amplifier, integrator, and
comparator. Since the comparator is included in the loop, the A­Z accuracy is limited only by the noise of the system. In any
case, the offset referred to the input is less than 10µV.

Signal Integrate Phase

During signal integrate, the auto-zero loop is opened, the
internal short is removed, and the internal input high and low

FN3086.6

July 21, 2005

ICL7136

are connected to the external pins. The converter then
integrates the differential voltage between IN HI and IN LO
for a fixed time. This differential voltage can be within a wide
common mode range: up to 1V from either supply. If, on the
other hand, the input signal has no return with respect to the
converter power supply, IN LO can be tied to analog
COMMON to establish the correct common mode voltage. At
the end of this phase, the polarity of the integrated signal is
determined.

De-Integrate Phase

The final phase is de-integrate, or reference integrate. Input
low is internally connected to analog COMMON and input
high is connected across the previously charged reference
capacitor. Circuitry within the chip ensures that the capacitor
will be connected with the correct polarity to cause the
integrator output to return to zero. The time required for the
output to return to zero is proportional to the input signal.
Specifically the digital reading displayed is:

V



IN

DISPLAY READING = 1000

---------------

V

.

REF




Zero Integrator Phase

The final phase is zero integrator. First, input low is shorted to
analog COMMON. Second, the reference capacitor is charged
to the reference voltage. Finally, a feedback loop is closed
around the system to IN HI to cause the integrator output to
return to zero. Under normal conditions, this phase lasts for
between 11 to 140 clock pulses, but after a “heavy” overrange
conversion, it is extended to 740 clock pulses.

Differential Input

The input can accept differential voltages anywhere within the
common mode range of the input amplifier, or specifically from

0.5V below the positive supply to 1V above the negative supply.
In this range, the system has a CMRR of 86dB typical.
However, care must be exercised to assure the integrator
output does not saturate. A worst case condition would be a
large positive common mode voltage with a near full scale
negative differential input voltage. The negative input signal
drives the integrator positive when most of its swing has been
used up by the positive common mode voltage. For these
critical applications the integrator output swing can be reduced
to less than the recommended 2V full scale swing with little loss
of accuracy. The integrator output can swing to within 0.3V of
either supply without loss of linearity.

Differential Reference

The reference voltage can be generated anywhere within the
power supply voltage of the converter. The main source of
common mode error is a roll-over voltage caused by the
reference capacitor losing or gaining charge to stray
capacity on its nodes. If there is a large common mode
voltage, the reference capacitor can gain charge (increase
voltage) when called up to de-integrate a positive signal but
lose charge (decrease voltage) when called up to de­integrate a negative input signal. This difference in reference
for positive or negative input voltage will give a roll-over
error. However, by selecting the reference capacitor such
that it is large enough in comparison to the stray
capacitance, this error can be held to less than 0.5 count
worst case. (See Component Value Selection.)

IN HI

COMMON

IN LO

STRAY STRAY

+

REF

A-Z

REF HI

34

C

V+

10µA

31

INT

32

INT

30

C

REF

36

A-Z, A-Z,
ZI ZI

DE- DE+

DE-DE+

A-Z AND DE(±)
AND ZI

REF LO

35

33

N

FIGURE 2. ANALOG SECTION OF ICL7136

C

V-

REF

-

-

+

INPUT

HIGH

26

R

INT

BUFFER

28 29 27

-

+

V+

1

2.8V

C

AZ

A-Z INT

INTEGRATOR

6.2V

INPUT
LOW

-

+

A-Z

COMPARATOR

ZI

C

INT

-

+

TO
DIGITAL
SECTION

7

FN3086.6

July 21, 2005

ICL7136

Analog COMMON

This pin is included primarily to set the common mode
voltage for battery operation or for any system where the
input signals are floating with respect to the power supply.
The COMMON pin sets a voltage that is approximately 2.8V
more negative than the positive supply. This is selected to
give a minimum end-of-life battery voltage of about 6.8V.
However, analog COMMON has some of the attributes of a
reference voltage. When the total supply voltage is large
enough to cause the zener to regulate (>7V), the COMMON
voltage will have a low voltage coefficient (0.001%/V), low
output impedance (≅15Ω), and a temperature coefficient
typically less than 150ppm/

The limitations of the on chip reference should also be
recognized, however. Due to their higher thermal resistance,
plastic parts are poorer in this respect than ceramic. The
combination of reference Temperature Coefficient (TC), internal
chip dissipation, and package thermal resistance can increase
noise near full scale from 25µV to 80µV
going from a high dissipation count such as 1000 (20 segments
on) to a low dissipation count such as 1111 (8 segments on) can
suffer by a count or more. Devices with a positive TC reference
may require several counts to pull out of an over range
condition. This is because over-range is a low dissipation
mode, with the three least significant digits blanked. Similarly,
units with a negative TC may cycle between over range and a
non-over range count as the die alternately heats and cools. All
these problems are of course eliminated if an external
reference is used.

The ICL7136, with its negligible dissipation, suffers from
none of these problems. In either case, an external
reference can easily be added, as shown in Figure 3.

Analog COMMON is also used as the input low return during
auto-zero and de-integrate. If IN LO is different from analog
COMMON, a common mode voltage exists in the system
and is taken care of by the excellent CMRR of the converter.
However, in some applications IN LO will be set at a fixed
known voltage (power supply common for instance). In this
application, analog COMMON should be tied to the same
point, thus removing the common mode voltage from the
converter. The same holds true for the reference voltage. If
reference can be conveniently tied to analog COMMON, it
should be since this removes the common mode voltage
from the reference system.

Within the lC, analog COMMON is tied to an N-Channel FET
that can sink approximately 3mA of current to hold the
voltage 2.8V below the positive supply (when a load is trying
to pull the common line positive). However, there is only
10µA of source current, so COMMON may easily be tied to a
more negative voltage thus overriding the internal reference.

o

C.

. Also the linearity in

P-P

V+

V

REF HI

REF LO

ICL7136

FIGURE 3A.

V

ICL7136

REF HI

REF LO

COMMON

FIGURE 3. USING AN EXTERNAL REFERENCE

20kΩ

FIGURE 3B.

6.8V
ZENER

I

V-

V+

6.8kΩ

ICL8069

1.2V
REFERENCE

Z

TEST

The TEST pin serves two functions. On the ICL7136 it is
coupled to the internally generated digital supply through a
500Ω resistor. Thus it can be used as the negative supply for
externally generated segment drivers such as decimal points
or any other presentation the user may want to include on
the LCD display. Figures 4 and 5 show such an application.
No more than a 1mA load should be applied.

V+

ICL7136

BP

21

TEST

37

FIGURE 4. SIMPLE INVERTER FOR FIXED DECIMAL POINT

The second function is a “lamp test”. When TEST is pulled
high (to V+) all segments will be turned on and the display
should read “-1888”. The TEST pin will sink about 5mA
under these conditions.

CAUTION: On the ICL7136, in the lamp test mode, the segments have a

constant DC voltage (no square-wave) and may burn the LCD
display if left in this mode for several minutes.

1MΩ

TO LCD
DECIMAL
POINT

TO LCD
BACKPLANE

8

FN3086.6

July 21, 2005

CD4030

GND

V+

TO LCD
DECIMAL
POINTS

V+

ICL7136

TEST

BP

DECIMAL

POINT

SELECT

FIGURE 5. EXCLUSIVE “OR” GATE FOR DECIMAL POINT DRIVE

ICL7136

Digital Section

Figures 6 shows the digital section for the ICL7136. In the
ICL7136, an internal digital ground is generated from a 6V
Zener diode and a large P-Channel source follower. This
supply is made stiff to absorb the relatively large capacitive
currents when the back plane (BP) voltage is switched. The
BP frequency is the clock frequency divided by 800. For
three readings/second this is a 60Hz square wave with a
nominal amplitude of 5V. The segments are driven at the
same frequency and amplitude and are in phase with BP
when OFF, but out of phase when ON. In all cases negligible
DC voltage exists across the segments.

The polarity indication is “on” for negative analog inputs. If IN
LO and IN HI are reversed, this indication can be reversed
also, if desired.

TYPICAL SEGMENT OUTPUT

INTERNAL DIGITAL GROUND

†

THREE INVERTERS
ONLY ONE INVERTER SHOWN
FOR CLARITY

0.5mA

2mA

V+

SEGMENT

OUTPUT

a

b

1000’s 100’s 10’s 1’s

COUNTER

FROM COMPARATOR OUTPUT

TO SWITCH DRIVERS

CLOCK

†

40 39 38

a

f

b

g

e

c

d

LCD PHASE DRIVER

7

SEGMENT

DECODE

LATCH

COUNTER COUNTER COUNTER

÷4

INTERNAL

DIGITAL

GROUND

f

c

e

SEGMENT

DECODE

a

b

g

c

d

7

LOGIC CONTROL

a

f

g

e

c

d

7

SEGMENT

DECODE

V

= 1V

TH

b

BACKPLANE

21

÷200

1

V+

6.2V

500Ω

TEST

37

26

V-

OSC 1

OSC 2

OSC 3

FIGURE 6. ICL7136 DIGITAL SECTION

9

FN3086.6

July 21, 2005

ICL7136

System Timing

Figure 7 shows the clocking arrangement used in the
ICL7136. Two basic clocking arrangements can be used:

1. Figure 9A, an external oscillator connected to DIP pin 40.

2. Figure 9B, an R-C oscillator using all three pins.

The oscillator frequency is divided by four before it clocks
the decade counters. It is then further divided to form the
three convert-cycle phases. These are signal integrate
(1000 counts), reference de-integrate (0 to 2000 counts) and
auto-zero (1000 to 3000 counts). For signals less than full
scale, auto-zero gets the unused portion of reference de­integrate. This makes a complete measure cycle of 4,000
counts (16,000 clock pulses) independent of input voltage.
For three readings/second, an oscillator frequency of 48kHz
would be used.

To achieve maximum rejection of 60Hz pickup, the signal
integrate cycle should be a multiple of 60Hz. Oscillator
frequencies of 240kHz, 120kHz, 80kHz, 60kHz, 48kHz,
40kHz, 33
rejection, Oscillator frequencies of 200kHz, 100kHz,

2

66
40kHz (2.5 readings/sec.) will reject both 50Hz and 60Hz
(also 400Hz and 440Hz).

TEST

1

/3kHz, etc., should be selected. For 50Hz

/3kHz, 50kHz, 40kHz, etc. would be suitable. Note that

INTERNAL TO PART

40 39

FIGURE 7A. EXTERNAL OSCILLATOR

INTERNAL TO PART

40 39

R

FIGURE 7B. RC OSCILLATOR

FIGURE 7. CLOCK CIRCUITS

³4

38

³4

38

C

CLOCK

CLOCK

Component Value Selection

Integrating Resistor

Both the buffer amplifier and the integrator have a class A
output stage with 100µA of quiescent current. They can
supply 1µA of drive current with negligible nonlinearity. The
integrating resistor should be large enough to remain in this
very linear region over the input voltage range, but small
enough that undue leakage requirements are not placed on
the PC board. For 2V full scale, 1.8MΩ is near optimum and
similarly a 180kΩ for a 200mV scale.

Integrating Capacitor

The integrating capacitor should be selected to give the
maximum voltage swing that ensures tolerance buildup will
not saturate the integrator swing (approximately 0.3V from
either supply). In the ICL7136, when the analog COMMON
is used as a reference, a nominal +2V full-scale integrator
swing is fine. For three readings/second (48kHz clock)
nominal values for C
respectively. Of course, if different oscillator frequencies are
used, these values should be changed in inverse proportion
to maintain the same output swing.

An additional requirement of the integrating capacitor is that
it must have a low dielectric absorption to prevent roll-over
errors. While other types of capacitors are adequate for this
application, polypropylene capacitors give undetectable
errors at reasonable cost.

Auto-Zero Capacitor

The size of the auto-zero capacitor has some influence on
the noise of the system. For 200mV full scale where noise is
very important, a 0.47µF capacitor is recommended. On the
2V scale, a 0.047µF capacitor increases the speed of
recovery from overload and is adequate for noise on this
scale.

Reference Capacitor

A 0.1µF capacitor gives good results in most applications.
However, where a large common mode voltage exists (i.e.,
the REF LO pin is not at analog COMMON) and a 200mV
scale is used, a larger value is required to prevent roll-over
error. Generally 1µF will hold the roll-over error to 0.5 count
in this instance.

Oscillator Components

For all ranges of frequency a 180kΩ resistor is
recommended and the capacitor is selected from the
equation:

0.45

-------------

f

RC

For 48kHz Clock (3 Readings/s.),=

are 0.047µF and 0.5µF,

lNT

10

C50pF.=

FN3086.6

July 21, 2005

ICL7136

Reference Voltage

The analog input required to generate full scale output (2000
counts) is: V
V

should equal 100mV and 1V, respectively. However, in

REF

many applications where the A/D is connected to a
transducer, there will exist a scale factor other than unity
between the input voltage and the digital reading. For
instance, in a weighing system, the designer might like to
have a full scale reading when the voltage from the
transducer is 0.662V. Instead of dividing the input down to
200mV, the designer should use the input voltage directly
and select V
resistor and capacitor would be 330kΩ and 0.047µF. This
makes the system slightly quieter and also avoids a divider
network on the input. Another advantage of this system
occurs when a digital reading of zero is desired for V
Temperature and weighing systems with a variable fare are
examples. This offset reading can be conveniently
generated by connecting the voltage transducer between
IN HI and COMMON and the variable (or fixed) offset
voltage between COMMON and IN LO.

= 2V

lN

REF

. Thus, for the 200mV and 2V scale,

REF

= 0.341V. Suitable values for integrating

IN

≠ 0.

Typical Applications

The ICL7136 may be used in a wide variety of
configurations. The circuits which follow show some of the
possibilities, and serve to illustrate the exceptional versatility
of these A/D converters.

The following application notes contain very useful
information on understanding and applying this part and are
available from Intersil.

Application Notes

NOTE # DESCRIPTION

AN016 “Selecting A/D Converters”

AN017 “The Integrating A/D Converter”

AN018 “Do’s and Don’ts of Applying A/D Converters”

AN023 “Low Cost Digital Panel Meter Designs”

AN032 “Understanding the Auto-Zero and Common Mode

Performance of the ICL7136/7/9 Family”

AN046 “Building a Battery-Operated Auto Ranging DVM with

the ICL7106”

AN052 “Tips for Using Single Chip 3

1

/2 Digit A/D Converters”

OSC 1
OSC 2
OSC 3

TEST

REF HI

REF LO

C

REF

C

REF

COMMON

IN HI

IN LO

A-Z

BUFF

INT

V -

G2

C3

A3

G3

BP

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

0.47µF

0.047µF

TO DISPLAY

180kΩ

50pF

0.1µF

180kΩ

TO BACKPLANE

TO PIN 1

20kΩ 240kΩ

0.01µF

SET V

REF

= 100mV

1MΩ

+

IN

-

+

9V

-

Values shown are for 200mV full scale, 3 readings/sec., floating
supply voltage (9V battery).

OSC 1
OSC 2
OSC 3

TEST

REF HI

REF LO

C

REF

C

REF

COMMON

IN HI

IN LO

A-Z

BUFF

INT

V -

G2

C3

A3

G3

BP/GND

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

180kΩ

50pF

0.01µF

0.047µF

TO DISPLAY

0.1µF

1.8M

TO PIN 1

250kΩ 240kΩ

0.01µF

SET V

REF

= 100mV

1MΩ

V+

+

IN

-

V-

FIGURE 8. ICL7136 USING THE INTERNAL REFERENCE FIGURE 9. RECOMMENDED COMPONENT VALUES FOR 2V

FULL SCALE

11

FN3086.6

July 21, 2005

ICL7136

OSC 1

40

OSC 2

39

OSC 3

38

TEST

37

REF HI

36

REF LO

COMMON

A silicon diode-connected transistor has a temperature coefficient
of about -2mV/

35

C

34

REF

C

IN HI

IN LO

BUFF

0.1µF

33

REF

32
31
30

A-Z

29
28

INT

27
26

V -

G2

25

C3

24

A3

23

G3

22

BP

21

o

C. Calibration is achieved by placing the sensing

TO PIN 1

†

50pF

0.01µF

0.47µF
390kΩ

†

TO DISPLAY

SCALE
FACTOR
ADJUST

100kΩ 1MΩ
200kΩ 470kΩ

ZERO
ADJUST

TO BACKPLANE

22kΩ

SILICON NPN
MPS 3704 OR
SIMILAR

+

9V

-

transistor in ice water and adjusting the zeroing potentiometer for a

000.0 reading. The sensor should then be placed in boiling water
and the scale-factor potentiomete r adju ste d f or a 1 00. 0 re ad in g.

† Value depends on clock frequency.

FIGURE 10. ICL7136 USED AS A DIGITAL CENTIGRADE

THERMOMETER

V+

OSC 1
OSC 2
OSC 3

TEST

REF HI

C

REF

C

REF

IN HI

IN LO

A-Z

BUFF

INT

G2
C3
A3
G3

BP

40
39
38
37
36
35

LOGIC

34
33
32
31
30
29
28
27
26

V-

25
24
23
22
21

O /RANGE

U /RANGE

CD4023 OR

74C10

TO LOGIC

V

CC

CD4077

1

V+

D1

2

C1

3

B1

4

A1

5

F1

6

G1

7

E1

8

D2

9

C2

10

B2

11

A2

12

F2

13

E2

14

D3

15

B3

16

F3

17

E3

18

AB4

19

POL

20

REF LO

COMMON

FIGURE 11. CIRCUIT FOR DEVELOPING UNDERRANGE AND

OVERRANGE SIGNAL FROM ICL7136 OUTPUTS

TO

GND

V-

OSC 1
OSC 2
OSC 3

TEST

REF HI

REF LO

C

REF

C

REF

COMMON

IN HI

IN LO

A-Z

BUFF

INT

V

G2

C3

A3

G3

BP

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26

-

25
24
23
22
21

TO PIN 1

180kΩ

50pF

0.1µF

0.47µF

180kΩ

0.047µF

TO DISPLAY

20kΩ 220kΩ

10µF

TO BACKPLANE

10µF

SCALE FACTOR ADJUST
(V

= 100mV FOR AC TO RMS)

REF

470kΩ

1µF

4.3kΩ

+

9V

-

100pF

(FOR OPTIMUM

BANDWIDTH)

10kΩ

1µF

1N914

10kΩ

Test is used as a common-mode reference level to ensure compatibility with most op amps.

5µF

1µF

0.22µF

CA3140

2.2MΩ

+

-

100kΩ

AC IN

12

FIGURE 12. AC TO DC CONVERTER WITH ICL7136

FN3086.6

July 21, 2005

Die Characteristics

ICL7136

DIE DIMENSIONS:

127 mils x 149 mils

METALLIZATION:

Type: Al
Thickness: 10k

Å ±1kÅ

Metallization Mask Layout

D

(15)

3

B

(16)

3

F

(17)

3

(18)

E

3

AB

(19)

4

POL (20)

BP/GND (21)

E

(14)

PAS SIVATI ON:

Type: PSG Nitride
Thickness: 15kÅ ±3kÅ

ICL7136

F

G

E

D

C

A

(12)

B

2

(11)

2

2

(10)

(9)

1

2

(8)

(7)

1

1

(6)

(5)

A

1

(4) B

1

(3) C

1

(2) D

1

(1) V+

(40) OSC 1

F

2

2

(13)

(22)

G

3

A

(23)

3

(24)

C

3

(25)

G

2

V- (26)

(27)

INT

(28)

BUFF

(29)

A/Z

(30)

IN LO

(31)

IN HI

(32)

COMM

C

(33)

REF-

(34)

C

REF+

(35)

LO HI

REF

(39) OSC 2

(38) OSC 3

(37) TEST

(36)

REF

13

FN3086.6

July 21, 2005

Dual-In-Line Plastic Packages (PDIP)

ICL7136

N

D1

-C-

E1

-B-

A1

A2

E

A

L

e

C

C

L

e

A

C

e

B

INDEX

AREA

BASE

PLANE

SEATING

PLANE

D1

B1

12 3 N/2

-A­D

e

B

0.010 (0.25) C AM BS

NOTES:

1. Controlling Dimensions: INCH. In case of conflict between English
and Metric dimensions, the inch dimensions control.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Symbols are defined in the “MO Series Symbol List” in Section 2.2
of Publication No. 95.

4. Dimensions A, A1 and L are measured with the package seated in
JEDEC seating plane gauge GS-3.

5. D, D1, and E1 dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).

6. E and are measured with the leads constrained to be per-

7. e

e

pendicular to datum .

A

and eC are measured at the lead tips with the leads uncon-

B

strained. e

must be zero or greater.

C

-C-

8. B1 maximum dimensions do not include dambar protrusions. Dam­bar protrusions shall not exceed 0.010 inch (0.25mm).

9. N is the maximum number of terminal positions.

10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).

E40.6 (JEDEC MS-011-AC ISSUE B)

40 LEAD DUAL-IN-LINE PLASTIC PACKAGE

INCHES MILLIMETERS

SYMBOL

A-0.250 - 6.35 4
A1 0.015 - 0.39 -4
A2 0.125 0.195 3.18 4.95 -

B 0.014 0.022 0.356 0.558 ­B1 0.030 0.070 0.77 1.77 8

C 0.008 0.015 0.204 0.381 -

D 1.980 2.095 50.3 53.2 5
D1 0.005 - 0.13 -5

E 0.600 0.625 15.24 15.87 6
E1 0.485 0.580 12.32 14.73 5

e 0.100 BSC 2.54 BSC -

e

A

e

B

0.600 BSC 15.24 BSC 6

- 0.700 - 17.78 7

L 0.115 0.200 2.93 5.08 4

N40 409

NOTESMIN MAX MIN MAX

Rev. 0 12/93

14

FN3086.6

July 21, 2005

ICL7136

Metric Plastic Quad Flatpack Packages (MQFP)

D

D1

-D-

E

E1

0.40

0.016

0o MIN

0o-7

-H-

-A-

o

MIN

PIN 1

o

12o-16

0.20

0.008

A2

A1

o

L

12o-16

0.005/0.007

BASE METAL

A-B SD SCM

0.13/0.17

WITH PLATING

-B-

e

SEATING

PLANE

A

0.076

0.003

-C-

b

b1

0.13/0.23

0.005/0.009

Q44.10x10 (JEDEC MS-022AB ISSUE B)

44 LEAD METRIC PLASTIC QUAD FLATPACK PACKAGE

INCHES MILLIMETERS

SYMBOL

A-0.096 - 2.45 -

A1 0.004 0.010 0.10 0.25 ­A2 0.077 0.083 1.95 2.10 -

b 0.012 0.018 0.30 0.45 6

b1 0.012 0.016 0.30 0.40 -

D 0.515 0.524 13.08 13.32 3

D1 0.389 0.399 9.88 10.12 4, 5

E 0.516 0.523 13.10 13.30 3

E1 0.390 0.398 9.90 10.10 4, 5

L 0.029 0.040 0.73 1.03 -

N44 44 7

e 0.032 BSC 0.80 BSC -

NOTES:

1. Controlling dimension: MILLIMETER. Converted inch
dimensions are not necessarily exact.

2. All dimensions and tolerances per ANSI Y14.5M-1982.

3. Dimensions D and E to be determined at seating plane .

4. Dimensions D1 and E1 to be determined at datum plane

.

-H-

5. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is 0.25mm (0.010 inch) per side.

6. Dimension b does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08mm (0.003 inch) total.

7. “N” is the number of terminal positions.

NOTESMIN MAX MIN MAX

Rev. 2 4/99

-C-

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

15

FN3086.6

July 21, 2005