Datasheet ICL7137, ICL7136 Datasheet (Intersil Corporation)

December 1997

ICL7136, ICL7137

31/2 Digit LCD/LED, Low Power Display,

A/D Converters with Overrange Recovery

Features

• First Reading Overrange Recovery in One Conversion
Period

• Guaranteed Zero Reading for 0V Input on All Scales

• True Polarity at Zero for Precise Null Detection

• 1pA Typical Input Current

• True Differential Input and Reference, Direct Displa y Drive

- LCD ICL7136

- LED lCL7137

• Low Noise - Less Than 15µV

P-P

• On Chip Clock and Reference

• No Additional Active Circuits Required

• Low Power - Less Than 1mW

• Surface Mount Package Available

• Drop-In Replacement for ICL7126, No Changes Needed

Ordering Information

TEMP.

PART NUMBER

ICL7136CPL 0 to 70 40 Ld PDIP E40.6
ICL7136RCPL 0 to 70 40 Ld PDIP (Note) E40.6
ICL7136CM44 0 to 70 44 Ld MQFP Q44.10x10
ICL7137CPL 0 to 70 40 Ld PDIP E40.6
ICL7137RCPL 0 to 70 40 Ld PDIP (Note) E40.6
ICL7137CM44 0 to 70 44 Ld MQFP Q44.10x10

NOTE: “R” indicates device with reversed leads.

RANGE (oC) PACKAGE PKG. NO.

Description

The Intersil ICL7136 and ICL7137 are high performance, low
power 31/2 digit, A/D converters. Included are seven seg­ment decoders, display drivers, a reference, and a clock.
The ICL7136 is designed to interface with a liquid crystal dis­play (LCD) and includes a multiplexed backplane drive; the
ICL7137 will directly drive an instrument size, light emitting
diode (LED) display.

The ICL7136 and ICL7137 bring together a combination of
high accuracy, versatility, and true economy. It features auto­zero to less than 10µV, zero drift of less than 1µV/
bias current of 10pA (Max), and rollover error of less than
one count. True differential inputs and reference are useful in
all systems, but give the designer an uncommon advantage
when measuring load cells, strain gauges and other bridge
type transducers. Finally, the true economy of single power
supply operation (ICL7136), enables a high performance
panel meter to be built with the addition of only 10 passive
components and a display.

The ICL7136 and ICL7137 are improved versions of the
ICL7126, eliminating the overrange hangover and hysteresis
effects, and should be used in its place in all applications. It
can also be used as a plug-in replacement for the ICL7106
in a wide variety of applications, changing only the passive
components.

o

C, input

Pinouts

(PDIP)

TOP VIEW

1

V+

2

D1

3

C1

4

B1

(1’s)

(10’s)

(100’s)

(1000) AB4

(MINUS)

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207

A1
F1
G1
E1
D2
C2
B2
A2
F2
E2
D3
B3
F3
E3

POL

5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20

| Copyright © Intersil Corporation 1999

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

OSC 1
OSC 2
OSC 3
TEST
REF HI
REF LO

+

C

REF

C

-

REF

COMMON
IN HI
IN LO
A-Z
BUFF
INT
V­G2 (10’s)
C3

(100’s)

A3
G3
BP/GND

NC
NC

TEST

OSC 3

NC
OSC 2
OSC 1

V+
D1
C1
B1

1

44 43 42 41 40

1

2
3
4
5

6
7
8
9

10
11

12 13 14 15 16 17

A1 F1 G1 E1 D2 C2

REF HI

REF LO

+

REF

C

-

C

(MQFP)

TOP VIEW

REF

COMMON

IN HI

IN LO

39 38 37 36 35 34

B2 A2 F2 E2 D3

A-Z

BUFF

INT

V-

33
32
31
30
29

28
27
26
25
24
23

2221201918

File Number 3086.2

NC
G2
C3
A3
G3

BP/GND
POL
AB4
E3
F3
B3

ICL7136, ICL7137

Absolute Maximum Ratings Thermal Information

Supply Voltage

ICL7136, V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15V

ICL7137, V+ to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6V

ICL7137, V- to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-9V

Analog Input Voltage (Either Input) (Note 1). . . . . . . . . . . . . V+ to V-

Reference Input Voltage (Either Input) . . . . . . . . . . . . . . . . . V+ to V-

Clock Input

ICL7136 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TEST to V+

ICL7137 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .GND to V+

Operating Conditions

Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . .0oC to 70oC

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

1. Input voltages may exceed the supply voltages provided the input current is limited to ±100µA.

2. θJA is measured with the component mounted on an evaluation PC board in free air.

Electrical Specifications (Note 3)

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

SYSTEM PERFORMANCE

Zero Input Reading VIN = 0V, Full Scale = 200mV -000.0 ±000.0 +000.0 Digital

Ratiometric Reading VlN = V

Rollover Error -VIN = +VlN≅ 200mV Difference in Reading for Equal

Positive and Negative Inputs Near Full Scale

Linearity Full Scale = 200mV or Full Scale = 2V Maximum

Deviation from Best Straight Line Fit (Note 5)
Common Mode Rejection Ratio VCM = ±1V, VIN = 0V, Full Scale = 200mV (Note 5) - 50 - µV/V
Noise VIN = 0V, Full Scale = 200mV (Peak-To-Peak Value Not

Exceeded 95% of Time) (Note 5)
Leakage Current Input VlN = 0V (Note 5) - 1 10 pA
Zero Reading Drift VlN = 0V, 0oC To 70oC (Note 5) - 0.2 1 µV/oC
Scale Factor Temperature Coefficient VIN = 199mV, 0oC To 70oC, (Ext. Ref. 0ppm/oC) (Note 5) - 1 5 ppm/oC
COMMON Pin Analog Common Voltage 25kΩ Between Common and Positive Supply (With

Respect to + Supply)
Temperature Coefficient of Analog

Common
SUPPLY CURRENT ICL7136
V+ Supply Current VIN = 0 (Does Not Include Common Current) 16kHz

SUPPLY CURRENT ICL7137
V+ Supply Current VIN = 0 (Does Not Include Common Current) 16kHz
V- Supply Current -40-µA
DISPLAY DRIVER ICL7136 ONLY
Peak-To-Peak Segment Drive Voltage

Peak-To-Peak Backplane Drive Voltage

25kΩ Between Common and Positive Supply (With

Respect to + Supply) (Note 5)

Oscillator (Note 6)

Oscillator (Note 6)

V+ = to V- = 9V (Note 4) 4 5.5 6 V

REF

, V

= 100mV 999 999/

REF

Thermal Resistance (Typical, Note 2) θJA (oC/W)

PDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

MQFP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . .150oC

Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . .300oC

(MQFP - Lead Tips Only)

Read-

ing

1000 Digital

1000

- ±0.2 ±1 Counts

- ±0.2 ±1 Counts

-15-µV

2.4 3.0 3.2 V

- 150 - ppm/oC

- 70 100 µA

- 70 200 µA

Read-

ing

2

ICL7136, ICL7137

Electrical Specifications (Note 3) (Continued)

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

DISPLAY DRIVER ICL7137 ONLY

Segment Sinking Current V+ = 5V, Segment Voltage = 3V

(Except Pins 19 and 20) 58-mA
Pin 19 Only 10 16 - mA
Pin 20 Only 47-mA

NOTES:

3. Unless otherwise noted, specifications apply to both the ICL7136 and ICL7137 at TA = 25oC, f
circuit of Figure 1. ICL7137 is tested in the circuit of Figure 2.

4. Back plane drive is in phase with segment drive for ‘off’ segment, 180 degrees out of phase for ‘on’ segment. Frequency is 20 times
conversion rate. Average DC component is less than 50mV.

5. Not tested, guaranteed by design.

6. 48kHz oscillator increases current by 20µA (Typ).

= 48kHz. ICL7136 is tested in the

CLOCK

Typical Applications and Test Circuits

IN

C

5

C

2

IN HI

IN LO

101112

9V

+

-

R

2

C

3

28

29

27262524232221

V-

INT

A-Z

BUFF

F2

E2

A2

D3

13

14151617181920

DISPLAY

G2

B3

C1= 0.1µF
C2= 0.47µF
C3= 0.047µF

C3

A3

G3

BP

C4= 50pF
C5= 0.01µF
R1= 240kΩ
R2= 180kΩ

F3

E3

AB4

POL

R3= 180kΩ
R4= 10kΩ
R5= 1MΩ

+ -

R

C

+

REF

C

5

1

-

REF

COM

C

R

1

R

C

4

OSC 3

TEST

4

REF HI

REF LO

R

3

4039383736353433323130

OSC 1

OSC 2

ICL7136

V+

D1C1B1

123456789

F1

G1

E1

D2C2B2

DISPLAY

A1

FIGURE 1. ICL7136 TEST CIRCUIT AND TYPICAL APPLICA TION WITH LCD DISPLAY COMPONENTS SELECTED FOR 200mV FULL SCALE

+5V -5V

R

1

R

R

3

4

C

4

+ -

IN

R

5

C

5

R

C

1

2

C

C

2

3

DISPLAY

C1= 0.1µF
C2= 0.47µF

IN LO

28

29

27262524232221

V-

INT

A-Z

BUFF

F2

E2

A2

D3

13

14151617181920

G2

B3

C3= 0.047µF

C3

A3

G3

GND

C4= 50pF
C5= 0.01µF
R1= 240kΩ
R2= 180kΩ

F3

E3

AB4

POL

R3= 180kΩ
R4= 10kΩ
R5= 1MΩ

4039383736353433323130

OSC 2

OSC 3

TEST

REF HI

OSC 1

+

REF

C

REF LO

-

REF

C

COM

IN HI

ICL7137

V+

D1C1B1

123456789

F1

G1

E1

D2C2B2

101112

DISPLAY

A1

FIGURE 2. ICL7137 TEST CIRCUIT AND TYPICAL APPLICA TION WITH LED DISPLAY COMPONENTS SELECTED FOR 200mV FULL SCALE

3

Design Information Summary Sheet

• OSCILLATOR FREQUENCY

= 0.45/RC

f

OSC

C

> 50pF; R

OSC

f

(Typ) = 48kHz

OSC

• OSCILLATOR PERIOD

= RC/0.45

t

OSC

• INTEGRATION CLOCK FREQUENCY

CLOCK

= f

OSC

f

• INTEGRATION PERIOD

= 1000 x (4/f

t

INT

• 60/50Hz REJECTION CRITERION

t

INT/t60Hz

or t

• OPTIMUM INTEGRATION CURRENT

= 1µA

I

INT

• FULL SCALE ANALOG INPUT VOLTAGE

(Typ) = 200mV or 2V

V

lNFS

• INTEGRATE RESISTOR

V

R

INT

---------------- -=

INFS

I

INT

• INTEGRATE CAPACITOR

t

()I

()

C

INT

INT

--------------------------------=

V

INT

• INTEGRATOR OUTPUT VOLTAGE SWING

t

()I

()

V

•V

INT

INT

INT

--------------------------------=

C

INT

MAXIMUM SWING:

(V- + 0.5V) < V

> 50kΩ

OSC

/4

)

OSC

lNT/t50Hz

INT

INT

INT

= Integer

< (V+ - 0.5V), V

(Typ) = 2V

INT

ICL7136, ICL7137

• DISPLAY COUNT

COUNT 1000

• CONVERSION CYCLE

= t

t

CYC

t

= t

CYC

when f

OSC

• COMMON MODE INPUT VOLTAGE

(V- + 1V) < V

• AUTO-ZERO CAPACITOR

0.01µF < C

• REFERENCE CAPACITOR

0.1µF < C

•V

COM

Biased between V+ and V-.

•V

• ICL7136 POWER SUPPLY: SINGLE 9V

• ICL7136 DISPLAY: LCD

• ICL7137 POWER SUPPLY: DUAL ±5.0V

• ICL7137 DISPLAY: LED

≅ V+ - 2.8V

COM

Regulation lost when V+ to V- < ≅6.8V.
If V

COM

the V

COM

V+ - V- = 9V
Digital supply is generated internally
V

TEST

Type: Direct drive with digital logic supply amplitude.

V+ = +5V to GND
V- = -5V to GND
Digital Logic and LED driver supply V+ to GND

Type: Non-Multiplexed Common Anode

V

IN

---------------

×=

V

REF

x 4000

CL0CK

x 16,000

OSC

= 48kHz; t

< (V+ - 0.5V)

lN

< 1µF

AZ

< 1µF

REF

CYC

= 333ms

is externally pulled down to (V + to V -)/2,

circuit will turn off.

≅ V+ - 4.5V

Typical Integrator Amplifier Output Waveform (INT Pin)

AUTO ZERO PHASE

(COUNTS)
2999 - 1000

SIGNAL INTEGRATE

PHASE FIXED
1000 COUNTS

TOTAL CONVERSION TIME = 4000 x t

4

DE-INTEGRATE PHASE

= 16,000 x t

CLOCK

0 - 1999 COUNTS

OSC

ICL7136, ICL7137

Pin Descriptions

PIN NUMBER

44 PIN

FLATPACK

1 8 V+ Supply Power Supply.
2 9 D1 Output Driver Pin for Segment “D” of the display units digit.
3 10 C1 Output Driver Pin for Segment “C” of the display units digit.
4 11 B1 Output Driver Pin for Segment “B” of the display units digit.
5 12 A1 Output Driver Pin for Segment “A” of the display units digit.
6 13 F1 Output Driver Pin for Segment “F” of the display units digit.
7 14 G1 Output Driver Pin for Segment “G” of the display units digit.
8 15 E1 Output Driver Pin for Segment “E” of the display units digit.

9 16 D2 Output Driver Pin for Segment “D” of the display tens digit.
10 17 C2 Output Driver Pin for Segment “C” of the display tens digit.
11 18 B2 Output Driver Pin for Segment “B” of the display tens digit.
12 19 A2 Output Driver Pin for Segment “A” of the display tens digit.
13 20 F2 Output Driver Pin for Segment “F” of the display tens digit.
14 21 E2 Output Driver Pin for Segment “E” of the display tens digit.
15 22 D3 Output Driver pin for segment “D” of the display hundreds digit.
16 23 B3 Output Driver pin for segment “B” of the display hundreds digit.
17 24 F3 Output Driver pin for segment “F” of the display hundreds digit.
18 25 E3 Output Driver pin for segment “E” of the display hundreds digit.
19 26 AB4 Output Driver pin for both “A” and “B” segments of the display thousands digit.
20 27 POL Output Driver pin for the negative sign of the display.
21 28 BP/GND Output Driver pin for the LCD backplane/Power Supply Ground.
22 29 G3 Output Driver pin for segment “G” of the display hundreds digit.
23 30 A3 Output Driver pin for segment “A” of the display hundreds digit.
24 31 C3 Output Driver pin for segment “C” of the display hundreds digit.
25 32 G2 Output Driver pin for segment “G” of the display tens digit.
26 34 V
27 35 INT Output Integrator amplifier output. To be connected to integrating capacitor.
28 36 BUFF Output Input buffer amplifier output. To be connected to integrating resistor.
29 37 A-Z Input Integrator amplifier input.To be connected to auto-zero capacitor.
30

31

32 40 COMMON Supply/

33
34

35
36

37 3 TEST Input Display test. Turns on all segments when tied to V+.
38

39
40

38
39

41
42

43
44

4
6
7

NAME FUNCTION DESCRIPTION40 PIN DIP

-

IN LO

IN HI

C

REF

C

REF

REF LO

REF HI

OSC3
OSC2
OSC1

Supply Negative power supply.

Input Differential inputs. To be connected to input voltage to be measured. LO and HI

designators are for reference and do not imply that LO should be connected to
lower potential, e.g., for negative inputs IN LO has a higher potential than IN HI.

Internal voltage reference output.

Output

-

+

Input Input pins for reference voltage to the device. REF HI should be positive

Output
Output

Input

Connection pins for reference capacitor.

reference to REF LO.

Device clock generator circuit connection pins.

5

ICL7136, ICL7137

Detailed Description

Analog Section

Figure 3 shows the Analog Section for the ICL7136 and
ICL7137. Each measurement cycle is divided into four
phases. They are (1) auto-zero (A-Z), (2) signal integrate
(INT) and (3) de-integrate (DE), (4) zero integrate (ZI).

Auto-Zero Phase

During auto-zero three things happen. First, input high and low
are disconnected from the pins and internally shorted to analog
COMMON. Second, the reference capacitor is charged to the
reference voltage. Third, a feedback loop is closed around the
system to charge the auto-zero capacitor C
for offset voltages in the buff er amplifier , integr ator , and compar­ator. Since the comparator is included in the loop , the A-Z accu­racy is limited only by the noise of the system. In any case, the
offset referred to the input is less than 10µV.

Signal Integrate Phase

During signal integrate, the auto-zero loop is opened, the
internal short is removed, and the internal input high and low
are connected to the external pins. The converter then
integrates the differential voltage between IN HI and IN LO
for a fixed time. This differential voltage can be within a wide
common mode range: up to 1V from either supply. If, on the
other hand, the input signal has no return with respect to the
converter power supply, IN LO can be tied to analog
COMMON to establish the correct common mode voltage. At
the end of this phase, the polarity of the integrated signal is
determined.

De-Integrate Phase

The final phase is de-integrate, or reference integrate. Input
low is internally connected to analog COMMON and input

to compensate

AZ

high is connected across the previously charged reference
capacitor. Circuitry within the chip ensures that the capacitor
will be connected with the correct polarity to cause the
integrator output to return to zero. The time required for the
output to return to zero is proportional to the input signal.
Specifically the digital reading displayed is:

V



IN

DISPLAY READING = 1000

---------------

V

.

REF




Zero Integrator Phase

The final phase is zero integrator. First, input low is shorted to
analog COMMON. Second, the reference capacitor is charged
to the reference voltage. Finally, a feedback loop is closed
around the system to IN HI to cause the integrator output to
return to zero. Under normal conditions, this phase lasts for
between 11 to 140 clock pulses, but after a “heavy” overrange
conversion, it is e xtended to 740 clock pulses .

Differential Input

The input can accept differential voltages anywhere within the
common mode range of the input amplifier, or specifically from

0.5V below the positive supply to 1V abov e thenegative supply.
In this range, the system has a CMRR of 86dB typical. How­ever, care must be exercised to assure the integrator output
does not saturate. A worst case condition would be a large pos­itive common mode voltage with a near full scale negative dif­ferential input voltage. The negative input signal drives the
integrator positive when most of its swing has been used up by
the positive common mode voltage. For these critical applica­tions the integrator output swing can be reduced to less than
the recommended 2V full scale swing with little loss of accu­racy. The integrator output can swing to within 0.3V of either
supply without loss of linearity .

IN HI

COMMON

IN LO

STRAY STRAY

+

REF

A-Z

REF HI

34

C

V+

10µA

31

INT

32

INT

30

C

REF

REF LO

36

A-Z, A-Z,
ZI ZI

DE- DE+

A-Z AND DE(±)
AND ZI

FIGURE 3. ANALOG SECTION OF ICL7136 AND ICL7137

35

DE-DE+

33

R

INT

-

C

REF

-

+

INPUT

HIGH

N

26

V-

BUFFER

28 29 27

-

+

V+

1

2.8V

C

AZ

A-Z INT

INTEGRATOR

6.2V

INPUT
LOW

A-Z

ZI

-

+

COMPARATOR

C

INT

-

+

TO
DIGITAL
SECTION

6

ICL7136, ICL7137

Differential Reference

The reference voltage can be generated an ywhere within the
power supply voltage of the conver ter. The main source of
common mode error is a roll-over voltage caused by the
reference capacitor losing or gaining charge to stray capacity
on its nodes. If there is a large common mode voltage, the
reference capacitor can gain charge (increase voltage) when
called up to de-integrate a positive signal but lose charge
(decrease voltage) when called up to de-integrate a negative
input signal. This difference in reference for positive or
negative input voltage will give a roll-over error. However, by
selecting the reference capacitor such that it is large enough
in comparison to the stray capacitance, this error can be
held to less than 0.5 count worst case. (See Component
Value Selection.)

Analog COMMON

This pin is included primarily to set the common mode
voltage for battery operation (ICL7136) or for any system
where the input signals are floating with respect to the power
supply. The COMMON pin sets a voltage that is approxi­mately 2.8V more negative than the positive supply. This is
selected to give a minimum end-of-life battery voltage of
about 6.8V. However, analog COMMON has some of the
attributes of a reference voltage. When the total supply
voltage is large enough to cause the zener to regulate (>7V),
the COMMON voltage will have a low voltage coefficient
(0.001%/V), low output impedance (≅15Ω), and a
temperature coefficient typically less than 150ppm/

o

C.

The limitations of the on chip reference should also be
recognized, however. With the ICL7137, the internal heating
which results from the LED drivers can cause some
degradation in performance. Due to their higher thermal resis­tance, plastic parts are poorer in this respect than ceramic.
The combination of reference Temperature Coefficient (TC),
internal chip dissipation, and package thermal resistance can
increase noise near full scale from 25µV to 80µV

. Also the

P-P

linearity in going from a high dissipation count such as 1000
(20 segments on) to a low dissipation count such as 1111 (8
segments on) can suffer by a count or more. Devices with a
positive TC reference ma y requiresev er al counts to pull out of
an over range condition. This is because over-range is a low
dissipation mode, with the three least significant digits
blanked. Similarly, units with a negative TC may cycle
between over range and a non-over range count as the die
alternately heats and cools. All these problems are of course
eliminated if an external reference is used.

reference can be conveniently tied to analog COMMON, it
should be since this removes the common mode voltage
from the reference system.

Within the lC, analog COMMON is tied to an N-Channel FET
that can sink approximately 3mA of current to hold the
voltage 2.8V below the positive supply (when a load is trying
to pull the common line positive). However, there is only
10µA of source current, so COMMON may easily be tied to a
more negative voltage thus overriding the internal reference.

V+

V
REF HI

REF LO

ICL7136
ICL7137

FIGURE 4A.

V

ICL7136
ICL7137

REF HI

REF LO

COMMON

FIGURE 4. USING AN EXTERNAL REFERENCE

20kΩ

FIGURE 4B.

6.8V
ZENER

I

V-

V+

6.8kΩ

ICL8069

1.2V
REFERENCE

Z

TEST

The TEST pin serves two functions. On the ICL7136 it is
coupled to the internally generated digital supply through a
500Ω resistor. Thus it can be used as the negativ e supply for
externally generated segment drivers such as decimal points
or any other presentation the user may want to include on
the LCD display. Figures 5 and 6 show such an application.
No more than a 1mA load should be applied.

The ICL7136, with its negligible dissipation, suffers from
none of these problems. In either case, an external
reference can easily be added, as shown in Figure 4.

Analog COMMON is also used as the input low return during
auto-zero and de-integrate. If IN LO is different from analog
COMMON, a common mode voltage exists in the system
and is taken care of by the excellent CMRR of the converter.
However, in some applications IN LO will be set at a fixed
known voltage (power supply common for instance). In this
application, analog COMMON should be tied to the same
point, thus removing the common mode voltage from the
converter. The same holds true for the reference voltage. If

V+

ICL7136

BP

21

TEST

37

FIGURE 5. SIMPLE INVERTER FOR FIXED DECIMAL POINT

1MΩ

TO LCD
DECIMAL
POINT

TO LCD
BACKPLANE

7

ICL7136, ICL7137

The second function is a “lamp test”. When TEST is pulled
high (to V+) all segments will be turned on and the display
should read “-1888”. The TEST pin will sink about 5mA
under these conditions.

CAUTION: On the ICL7136, in the lamp test mode, the segments have a

FIGURE 6. EXCLUSIVE ‘OR’ GATE FOR DECIMAL POINT DRIVE

constant DC voltage (no square-wave) and may burn the LCD
display if left in this mode for several minutes.

CD4030

GND

V+

TO LCD
DECIMAL
POINTS

V+

ICL7136

TEST

BP

DECIMAL

POINT

SELECT

Digital Section

Figures 7 and 8 show the digital section for the ICL7136 and
ICL7137, respectively. In the ICL7136, an internal digital
ground is generated from a 6V Zener diode and a large
P-Channel source follower. This supply is made stiff to
absorb the relative large capacitive currents when the back
plane (BP) voltage is switched. The BP frequency is the
clock frequency divided by 800. For three readings/second
this is a 60Hz square wave with a nominal amplitude of 5V.
The segments are driven at the same frequency and ampli­tude and are in phase with BP when OFF, but out of phase
when ON. In all cases negligible DC voltage exists across
the segments.

Figure 8 is the Digital Section of the ICL7137. It is identical
to the ICL7136 except that the regulated supply and back
plane drive have been eliminated and the segment drive has
been increased from 2mA to 8mA, typical for instrument size
common anode LED displays. Since the 1000 output (pin 19)
must sink current from two LED segments, it has twice the
drive capability or 16mA.

In both devices, the polarity indication is “on” for negative
analog inputs. If IN LO and IN HI are reversed, this indication
can be reversed also, if desired.

TYPICAL SEGMENT OUTPUT

INTERNAL DIGITAL GROUND

0.5mA

2mA

V+

SEGMENT

OUTPUT

† THREE INVERTERS

ONLY ONE INVERTER SHOWN
FOR CLARITY

a

b

1000’s 100’s 10’s 1’s

COUNTER COUNTER COUNTER COUNTER

FROM COMPARATOR OUTPUT

TO SWITCH DRIVERS

CLOCK

†

40 39 38

a

f

b

g

c

e

e

c

d

LCD PHASE DRIVER

7

SEGMENT

DECODE

LATCH

SEGMENT

DECODE

÷4

INTERNAL

DIGITAL

GROUND

a

f

b

g

c

d

7

LOGIC CONTROL

a

f

g

e

c

d

7

SEGMENT

DECODE

VTH = 1V

b

BACKPLANE

21

÷200

1

V+

6.2V

500Ω

TEST

37

26

V-

OSC 1

OSC 2

OSC 3

FIGURE 7. ICL7136 DIGITAL SECTION

8

ICL7136, ICL7137

TYPICAL SEGMENT OUTPUT

DIGITAL GROUND

0.5mA

8mA

V+

TO

SEGMENT

† THREE INVERTERS

ONLY ONE INVERTER SHOWN
FOR CLARITY

FROM COMPARATOR OUTPUT

TO SWITCH DRIVERS

V+

CLOCK

†

40 39 38

OSC 1

OSC 2

a

f

a

b

1000’s 100’s 10’s 1’s

COUNTER

OSC 3

b

g

e

c

c

d

7

SEGMENT

DECODE

LATCH

COUNTER COUNTER COUNTER

÷4

a

f

b

g

e

c

d

7

SEGMENT

DECODE

LOGIC CONTROL

e

SEGMENT

DECODE

a

f

b

g

c

d

7

1

V+
TEST

37

500Ω

27

DIGITAL
GROUND

FIGURE 8. ICL7137 DIGITAL SECTION

System Timing

Figure 9 shows the clocking arrangement used in the
ICL7136 and ICL7137. Two basic clocking arrangements
can be used:

1. Figure 9A, an external oscillator connected to pin 40.

2. Figure 9B, an R-C oscillator using all three pins.

The oscillator frequency is divided by four bef ore it cloc ks the
decade counters. It is then further divided to form the three
convert-cycle phases. These are signal integrate (1000
counts), reference de-integrate (0 to 2000 counts) and auto­zero (1000 to 3000 counts). For signals less than full scale,
auto-zero gets the unused portion of reference de-integrate.
This makes a complete measure cycle of 4,000 counts
(16,000 clock pulses) independent of input voltage. F or three
readings/second, an oscillator frequency of 48kHz would be
used.

To achieve maximum rejection of 60Hz pickup, the signal
integrate cycle should be a multiple of 60Hz. Oscillator
frequencies of 240kHz, 120kHz, 80kHz, 60kHz, 48kHz,
40kHz, 33
tion, Oscillator frequencies of 200kHz, 100kHz, 66

1

/3kHz, etc., should be selected. For 50Hz rejec-

2

/3kHz,
50kHz, 40kHz, etc. would be suitable. Note that 40kHz (2.5
readings/sec.) will reject both 50Hz and 60Hz (also 400Hz
and 440Hz).

INTERNAL TO PART

40 39

GND ICL7137
TEST ICL7136

FIGURE 9A. EXTERNAL OSCILLAT OR

INTERNAL TO PART

40 39

FIGURE 9B. RC OSCILLATOR

FIGURE 9. CLOCK CIRCUITS

÷4

38

÷4

38

R

C

CLOCK

CLOCK

9

ICL7136, ICL7137

Component Value Selection

Integrating Resistor

Both the buffer amplifier and the integrator have a class A
output stage with 100µA of quiescent current. They can
supply 1µA of drive current with negligible nonlinearity. The
integrating resistor should be large enough to remain in this
very linear region over the input voltage range, but small
enough that undue leakage requirements are not placed on
the PC board. For 2V full scale, 1.8MΩ is near optimum and
similarly a 180kΩ for a 200mV scale.

Integrating Capacitor

The integrating capacitor should be selected to give the
maximum voltage swing that ensures tolerance buildup will
not saturate the integrator swing (approximately 0.3V from
either supply). In the ICL7136 or the ICL7137, when the
analog COMMON is used as a reference, a nominal +2V full­scale integrator swing is fine. For the ICL7137 with +5V
supplies and analog COMMON tied to supply ground, a
±3.5V to +4V swing is nominal. For three readings/second
(48kHz clock) nominal values for C

0.5µF, respectively. Of course, if different oscillator frequen­cies are used, these values should be changed in inverse
proportion to maintain the same output swing.

An additional requirement of the integrating capacitor is that
it must have a low dielectric absorption to prevent roll-over
errors. While other types of capacitors are adequate for this
application, polypropylene capacitors give undetectable
errors at reasonable cost.

Auto-Zero Capacitor

The size of the auto-zero capacitor has some influence on
the noise of the system. For 200mV full scale where noise is
very important, a 0.47µF capacitor is recommended. On the
2V scale, a 0.047µF capacitor increases the speed of recov­ery from overload and is adequate for noise on this scale.

Reference Capacitor

are 0.047µF and

lNT

Reference Voltage

The analog input required to generate full scale output (2000
counts) is: V
V

should equal 100mV and 1V, respectively. However, in

REF

lN

= 2V

. Thus, for the 200mV and 2V scale,

REF

many applications where the A/D is connected to a
transducer, there will exist a scale factor other than unity
between the input voltage and the digital reading. For
instance, in a weighing system, the designer might like to
have a full scale reading when the voltage from the
transducer is 0.662V. Instead of dividing the input down to
200mV, the designer should use the input voltage directly
and select V

= 0.341V. Suitable values for integrating

REF

resistor and capacitor would be 330kΩ and 0.047µF. This
makes the system slightly quieter and also avoids a divider
network on the input. The ICL7137 with ±5V supplies can
accept input signals up to ±4V. Another advantage of this
system occurs when a digital reading of zero is desired for
V

≠ 0. Temperature and weighing systems with a variable

IN

fare are examples. This offset reading can be conveniently
generated by connecting the voltage transducer between IN
HI and COMMON and the variable (or fixed) offset voltage
between COMMON and IN LO.

ICL7137 Power Supplies

The ICL7137 is designed to work from ±5V supplies.
However, if a negative supply is not available, it can be
generated from the clock output with 2 diodes, 2 capacitors,
and an inexpensive lC . Figure 10 sho ws this application. See
ICL7660 data sheet for an alternative.

In fact, in selected applications no negative supply is
required. The conditions to use a single +5V supply are:

1. The input signal can be referenced to the center of the
common mode range of the converter.

2. The signal is less than ±1.5V.

3. An external reference is used.

V+

CD4009

A 0.1µF capacitor gives good results in most applications.
However, where a large common mode voltage exists (i.e.,
the REF LO pin is not at analog COMMON) and a 200mV
scale is used, a larger value is required to prevent roll-over
error. Generally 1µF will hold the roll-over error to 0.5 count
in this instance.

Oscillator Components

For all ranges of frequency a 180kΩ resistor is recom­mended and the capacitor is selected from the equation

0.45

------------ -

f

RC

For 48kHz Clock (3 Readings/sec.),=

C 50pF.=

V+

OSC 1

OSC 2
OSC 3

ICL7137

GND

V-

V- = 3.3V

FIGURE 10. GENERATING NEGATIVE SUPPLY FROM +5V

10

IN914

0.047
µF

IN914

+

10
µF

-

ICL7136, ICL7137

Typical Applications

The ICL7136 and ICL7137 may be used in a wide variety of
configurations. The circuits which follow show some of the
possibilities, and serve to illustrate the exceptional versatility
of these A/D converters.

The following application notes contain very useful
information on understanding and applying this part and are
available from Intersil semiconductor.

Typical Applications

OSC 1
OSC 2
OSC 3

TEST

REF HI

REF LO

C

REF

C

REF

COMMON

IN HI

IN LO

A-Z

BUFF

INT

V ­G2
C3
A3
G3
BP

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

TO DISPLAY

180kΩ

50pF

0.1µF

0.47µF
180kΩ

0.047µF

TO BACKPLANE

TO PIN 1

20kΩ 240kΩ

0.01µF

SET V

REF

= 100mV

1MΩ

+

IN

-

+

9V

-

Application Notes

AnswerFAX

NOTE # DESCRIPTION

AN016 “Selecting A/D Converters” 9016
AN017 “The Integrating A/D Converter” 9017
AN018 “Do’s and Don’ts of Applying A/D

Converters”
AN023 “Low Cost Digital Panel Meter Designs” 9023
AN032 “Understanding the Auto-Zero and

Common Mode Performance of the

ICL7136/7/9 Family”
AN046 “Building a Battery-Operated Auto

Ranging DVM with the ICL7106”
AN052 “Tips for Using Single Chip 31/2 Digit A/D

Converters”

OSC 1
OSC 2
OSC 3

TEST

REF HI

REF LO

C

REF

C

REF

COMMON

IN HI

IN LO

A-Z

BUFF

INT

V ­G2
C3
A3
G3

GND

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

TO DISPLAY

180kΩ

50pF

0.1µF

0.47µF
180kΩ

0.047µF

TO PIN 1

SET V
= 100mV

20kΩ 240kΩ

0.01µF

DOC. #

9018

9032

9046

9052

REF

1MΩ

+5V

+

IN

-

-5V

Values shown are for 200mV full scale, 3 readings/sec., floating
supply voltage (9V battery).

Values shown are for 200mV full scale, 3 readings/sec. IN LO may
be tied to either COMMON for inputs floating with respect to
supplies, or GND for single ended inputs. (See discussion under
Analog COMMON.)

FIGURE 11. ICL7136 USING THE INTERNAL REFERENCE FIGURE 12. ICL7137 USING THE INTERNAL REFERENCE

11

t

r

ICL7136, ICL7137

Typical Applications

OSC 1

40

OSC 2

39

OSC 3

38

TEST

37

REF HI

36

REF LO

COMMON

BP/GND

C

REF

C

REF

IN HI

IN LO

A-Z

BUFF

INT

V­G2
C3
A3
G3

35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

TO DISPLAY

100kΩ

50pF

0.1µF

0.47µF
180kΩ

0.047µF

(Continued)

TO PIN 1

SET V
= 100mV

20kΩ 200kΩ

0.01µF

REF

27kΩ

1.2V (ICL8069)

1MΩ

+

-

V+

IN

-

V

IN LO is tied to supply COMMON establishing the correct common mode
voltage. If COMMON is not shorted to GND, the input voltage may floa
with respect to the power supply and COMMON acts as a pre-regulato
for the reference. If COMMON is shorted to GND, the input is single
ended (referred to supply GND) and the pre-regulator is overridden.

FIGURE 13. ICL7137 WITH AN EXTERNAL BAND-GAP

REFERENCE (1.2V TYPE)

OSC 1
OSC 2
OSC 3

TEST

REF HI

REF LO

C

REF

C

REF

COMMON

IN HI

IN LO

A-Z

BUFF

INT

G2

G3

BP/GND

V -

C3
A3

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

TO DISPLAY

180kΩ

50pF

0.1µF

0.33µF
180kΩ

0.047µF

TO PIN 1

10kΩ 1M

SET V
= 100mV

1MΩ

0.01µF

REF

+5V

6.8V

+

IN

-

-5V

Since low TC zeners have breakdown voltages ~ 6.8V, diode must
be placed across the total supply (10V). As in the case of Figure 14,
IN LO may be tied to either COMMON or GND

FIGURE 14. ICL7137 WITH ZENER DIODE REFERENCE

OSC 1
OSC 2
OSC 3

TEST

REF HI

REF LO

C

REF

C

REF

COMMON

IN HI

IN LO

A-Z

BUFF

INT

V ­G2
C3
A3
G3

BP/GND

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

TO DISPLAY

180kΩ

50pF

0.1µF

0.01µF

1.8M

0.047µF

TO PIN 1

250kΩ 240kΩ

0.01µF

SET V
= 100mV

1MΩ

REF

FIGURE 15. ICL7136 AND ICL7137: RECOMMENDED

COMPONENT VALUES FOR 2V FULL SCALE

40

OSC 1

39

OSC 2

38

OSC 3

37

TEST

36

REF HI

C

REF

C

REF

IN HI

IN LO

A-Z

BUFF

INT

V -

G2

C3
A3

G3

35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

TO DISPLAY

V+

+

IN

REF LO

COMMON

-

V-

BP/GND

180kΩ

50pF

0.1µF

0.47µF
180kΩ

0.047µF

TO PIN 1

20kΩ 100kΩ

0.01µF

SET V

REF

= 100mV

27kΩ

1.2V (ICL8069)

1MΩ

+5V

+

IN

-

An external reference must be used in this application, since the
voltage between V+ and V- is insufficient for correct operation of the
internal reference.

FIGURE 16. ICL7137 OPERATED FROM SINGLE +5V

12

ICL7136, ICL7137

Typical Applications

40

OSC 1

39

OSC 2

38

OSC 3

37

TEST

36

REF HI

C

REF

C

REF

IN HI

IN LO

A-Z

BUFF

INT

V ­G2
C3
A3
G3

GND

35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

TO DISPLAY

REF LO

COMMON

TO PIN 1

180kΩ

50pF

0.1µF

0.47µF
180kΩ

0.047µF

(Continued)

V+

The resistor values within the bridge are determined by the desired
sensitivity.

FIGURE 17. ICL7137 MEASURING RATIOMETRIC VALUES OF

QUAD LOAD CELL

V+

OSC 1
OSC 2
OSC 3

TEST

REF HI

C

REF

C

REF

IN HI

IN LO

A-Z

BUFF

INT

G2
C3
A3
G3
BP

40
39
38
37
36
35

TO

LOGIC

34

GND

33
32
31
30
29
28
27
26

V-

V­25
24
23
22
21

O /RANGE

U /RANGE

CD4023 OR

74C10

TO LOGIC

V

CC

CD4077

1

V+
D1

2

C1

3

B1

4

A1

5

F1

6

G1

7

E1

8

D2

9

C2

10

B2

11

A2

12

F2

13

E2

14

D3

15

B3

16

F3

17

E3

18

AB4

19

POL

20

REF LO

COMMON

FIGURE 19. CIRCUIT FOR DEVELOPING UNDERRANGE AND

OVERRANGE SIGNAL FROM ICL7136 OUTPUTS

OSC 1
OSC 2
OSC 3

TEST

REF HI

REF LO

C

REF

C

REF

COMMON

IN HI

IN LO

A-Z

BUFF

INT

V ­G2
C3
A3
G3

BP

40
39
38
37
36
35
34

0.1µF

33
32
31
30
29
28
27
26
25
24
23
22
21

TO PIN 1

†

50pF

0.01µF

0.47µF
390kΩ

†

TO DISPLAY

SCALE
FACTOR
ADJUST

100kΩ 1MΩ
200kΩ 470kΩ

ZERO
ADJUST

TO BACKPLANE

22kΩ

SILICON NPN
MPS 3704 OR
SIMILAR

+

9V

-

A silicon diode-connected transistor has a temperature coefficient
of about -2mV/oC. Calibration is achieved by placing the sensing
transistor in ice water and adjusting the zeroing potentiometer for a

000.0 reading. The sensor should then be placed in boiling water
and the scale-factor potentiometer adjusted for a 100.0 reading.

† Value depends on clock frequency.

FIGURE 18. ICL7136 USED AS A DIGITAL CENTIGRADE

THERMOMETER

+5V

OSC 1
OSC 2
OSC 3

TEST

REF HI

C

REF

C

REF

IN HI

IN LO

A-Z

BUFF

INT

G2
C3
A3
G3
BP

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26

V-

V­25
24
23
22
21

1

V+
D1

2

C1

3

B1

4

A1

5

TO LOGIC

V

CC

12kΩ

The LM339 is required to
ensure logic compatibility
with heavy display loading.

O /RANGE

U /RANGE

CD4023 OR

74C10

F1

6

G1

7

E1

8

D2

9

C2

10

B2

11

A2

12

F2

13

E2

+

-

+

-

+

-

-

+

14
15
16
17
18
19
20

33kΩ

D3
B3
F3
E3
AB4
POL

REF LO

COMMON

FIGURE 20. CIRCUIT FOR DEVELOPING UNDERRANGE AND

OVERRANGE SIGNALS FROM ICL7137 OUTPUT

13

ICL7136, ICL7137

Typical Applications

OSC 1
OSC 2
OSC 3

TEST

REF HI

REF LO

C

REF

C

REF

COMMON

IN HI

IN LO

A-Z

BUFF

INT

V­G2
C3
A3
G3

BP

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

TO PIN 1

180kΩ

50pF

0.1µF

0.47µF

0.047µF

TO DISPLAY

Test is used as a common-mode reference level to ensure compatibility with most op amps.

(Continued)

20kΩ 220kΩ

180kΩ

TO BACKPLANE

10µF

10µF

SCALE FACTOR ADJUST
(V

= 100mV FOR AC TO RMS)

REF

470kΩ

1µF

4.3kΩ

+

9V

-

100pF

(FOR OPTIMUM

BANDWIDTH)

10kΩ

1µF

1N914

10kΩ

5µF

1µF

0.22µF

CA3140

2.2MΩ

+

-

100kΩ

AC IN

FIGURE 21. AC TO DC CONVERTER WITH ICL7136

14

Die Characteristics

ICL7136, ICL7137

DIE DIMENSIONS:

127 mils x 149 mils

METALLIZATION:

Type: Al
Thickness: 10k

Å ±1kÅ

Metallization Mask Layout

(14)

(15)

D

3

B

(16)

3

F3 (17)

(18)

E

3

(19)

AB

4

PASSIVATION:

Type: PSG Nitride
Thickness: 15k

Å ±3kÅ

WORST CASE CURRENT DENSITY:

4

2

9.1 x 10

ICL7136, ICL7137

E

2

(13)

2

2

(12)

A

F

B

(11)

C

2

2

(10)

D
(9)

E

2

(8)

A/cm

(5)

A

1

(4) B

1

(3) C

1

(2) D

1

(1) V+

F

G

1

1

1

(6)

(7)

POL (20)

BP/GND (21)

G

(22)

3

(23)

A

3

C

(24)

3

(25)

G

2

V- (26)

(27)
INT

(28)

BUFF

(29)
A/Z

(30)

IN LO

(31)

IN HI

(32)

COMM

C

(33)

REF-

C

(34)

REF+

(35)

LO HI

REF

(40) OSC 1

(39) OSC 2

(38) OSC 3

(37) TEST

(36)

REF

15

ICL7136, ICL7137

Dual-In-Line Plastic Packages (PDIP)

N

D1

-C-

E1

-B-

A1

A2

E

A

L

C

L

e

e

C

S

e

INDEX

AREA

BASE

PLANE

SEATING

PLANE

D1
B1

1 2 3 N/2

-A­D

e

B

0.010 (0.25) C AMB

NOTES:

1. Controlling Dimensions: INCH. In case of conflict between English
and Metric dimensions, the inch dimensions control.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Symbols are defined in the “MO Series Symbol List” in Section 2.2
of Publication No. 95.

4. Dimensions A, A1 and L are measured with the package seated in
JEDEC seating plane gauge GS-3.

5. D, D1, and E1 dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).

6. E and are measured with the leads constrained to be per-

e

pendicular to datum .

A

-C-

7. eB and eC are measured at the lead tips with the leads uncon­strained. eC must be zero or greater.

8. B1 maximum dimensions do not include dambar protrusions.
Dambar protrusions shall not exceed 0.010 inch (0.25mm).

9. N is the maximum number of terminal positions.

10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).

E40.6 (JEDEC MS-011-AC ISSUE B)

40 LEAD DUAL-IN-LINE PLASTIC PACKAGE

INCHES MILLIMETERS

SYMBOL

A - 0.250 - 6.35 4
A1 0.015 - 0.39 - 4
A2 0.125 0.195 3.18 4.95 -

B 0.014 0.022 0.356 0.558 ­B1 0.030 0.070 0.77 1.77 8

A

C

B

C 0.008 0.015 0.204 0.381 ­D 1.980 2.095 50.3 53.2 5

D1 0.005 - 0.13 - 5

E 0.600 0.625 15.24 15.87 6
E1 0.485 0.580 12.32 14.73 5

e 0.100 BSC 2.54 BSC ­e

A

e

B

0.600 BSC 15.24 BSC 6

- 0.700 - 17.78 7

L 0.115 0.200 2.93 5.08 4

N40 409

NOTESMIN MAX MIN MAX

Rev. 0 12/93

16

ICL7136, ICL7137

Metric Plastic Quad Flatpack Packages (MQFP/PQFP)

E

E1

0.40

0.016
0o MIN

0o-7

-H-

-A-

o

MIN

D

D1

-D-

Q44.10x10 (JEDEC MO-108AA-2 ISSUE A)

44 LEAD METRIC PLASTIC QUAD FLATPACK PACKAGE

SYM-

BOL

INCHES MILLIMETERS

NOTESMIN MAX MIN MAX

A - 0.093 - 2.35 ­A1 0.004 0.010 0.10 0.25 ­A2 0.077 0.083 1.95 2.10 -

-B-

B 0.012 0.018 0.30 0.45 6
B1 0.012 0.016 0.30 0.40 -

D 0.510 0.530 12.95 13.45 3

D1 0.390 0.398 9.90 10.10 4, 5

E 0.510 0.530 12.95 13.45 3

e

PIN 1

E1 0.390 0.398 9.90 10.10 4, 5

L 0.026 0.037 0.65 0.95 -

N44 447

e 0.032 BSC 0.80 BSC -

SEATING

PLANE

A

0.10

0.004

D

S

B

B1

0.13/0.23

0.005/0.009

-C-

S

o

5o-16

A2

o

L

5o-16

A1

0.20

M

0.008

0.13/0.17

0.005/0.007

BASE METAL

WITH PLATING

A-B

C

NOTES:

1. Controlling dimension: MILLIMETER. Converted inch
dimensions are not necessarily exact.

2. All dimensions and tolerances per ANSI Y14.5M-1982.

3. Dimensions D and E to be determined at seating plane .

4. Dimensions D1 and E1 to be determined at datum plane

-H-

.

5. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is 0.25mm (0.010 inch) per side.

6. Dimension B does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08mm (0.003 inch) total.

7. “N” is the number of terminal positions.

Rev. 1 1/94

-C-

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Intersil products are sold by description only. Intersil Corporation reser ves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
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