Datasheet ICE3BR0665JXKLA1 Specification

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CoolSET®-F3R

ICE3BR0665J

Off-Line SMPS Current Mode Controller with integrated 650V CoolMOS

and Startup cell

(frequency jitter Mode) in DIP-8

Version 2.3, 19 Nov 2012

Power Management & Supply

Never stop thinking.

CoolSET

ICE3BR0665J Revision History: 2012-11-19 Datasheet

-F3R

Previous Version: 2.2

Page Subjects (major changes since last revision)

For questions on technology, delivery and prices please contact the Infineon Technologies Offices in Germany or the Infineon Technologies Companies and Representatives worldwide: see our webpage at http:// www.infineon.com

CoolMOS

revised outline dimension for PG-DIP-8 package

, CoolSET® are trademarks of Infineon Technologies AG.

Edition 2012-11-19

Published by Infineon Technologies AG, 81726 Munich, Germany,

Legal disclaimer

The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party.

Information

For further information on technology, delivery terms and conditions and prices, please contact your nearest Infineon Technologies Office (www.infineon.com

Warnings

Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact your nearest Infineon Technologies Office.

Infineon Technologies Components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.

PG-DIP-8

VCC

Bulk

Converter

DC Output

Snubber

Power Management

PWM Controller

Current Mode

85 ... 270 VAC

Typical Application

Sense

GND

Active Burst Mode

Auto Restart Mode

Contr ol

Unit

VCC

Startup Cell

Precise Low Toler ance Peak

Current Limitation

Drai n

CoolS ET

™-F3R

(Jitter Mode)

CoolMOS

Off-Line SMPS Current Mode Controller with integrated 650V CoolMOS

and Startup cell

CoolSET®-F3R

(frequency jitter Mode) in DIP-8

Product Highlights

• Active Burst Mode to reach the lowest Standby Power Requirements < 50mW

• Auto Restart protection for overload, overtemperature, overvoltage

• External auto-restart enable function

• Built-in soft start and blanking window

• Extendable blanking Window for high load jumps

• Built-in frequency jitter and soft driving for low EMI

• Green Mould Compound

• Pb-free lead plating; RoHS compliant

Features

• 650V avalanche rugged CoolMOS® with built-in Startup Cell

• Active Burst Mode for lowest Standby Power

• Fast load jump response in Active Burst Mode

• 65kHz internally fixed switching frequency

• Auto Restart Protection Mode for Overload, Open Loop, VCC Undervoltage, Overtemperature & Overvoltage

• Built-in Soft Start

• Built-in blanking window with extendable blanking time for short duration high current

• External auto-restart enable pin

• Max Duty Cycle 75%

• Overall tolerance of Current Limiting < ±5%

• Internal PWM Leading Edge Blanking

• BiCMOS technology provide wide VCC range

• Built-in Frequency jitter and soft driving for low EMI

Description

The CoolSET®-F3R jitter series (ICE3BRxx65J) is the latest version of CoolSET battery adapters and low cost SMPS for lower power range such as application for DVD R/W, DVD Combi, Blue ray DVD player, set top box, etc. Besides inherited the outstanding performance of the CoolSET BiCMOS technology, active burst mode, auto-restart protection, propagation delay compensation, etc.,

CoolSET built-in soft start time, built-in blanking window, built-in frequency jitter, soft gate driving, etc. In case a longer blanking time is needed for high load application, a simple addition of capacitor to BA pin can serve the purpose. Furthermore, an external auto-restart enable feature can provide extra protection when there is a need of immediate stop of power switching.

-F3R series has some new features such as

ICE3BR0665J

-F3. It targets for the Off-Line

-F3 in the

Type Package Marking V

ICE3BR0665J PG-DIP-8 ICE3BR0665J 650V 65kHz 0.65 74W 49W

typ @ Tj=25°C

Calculated maximum input power rating at Ta=50°C, Ti=125°C and without copper area as heat sink. Refer to input power curve for other Ta.

Version 2.3 3 19 Nov 2012

OSC

DSon

230VAC ±15%

85-265 VAC

Table of Contents Page

1 Pin Configuration and Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

1.1 Pin Configuration with PG-DIP-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

1.2 Pin Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

2 Representative Blockdiagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

3.2 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

3.3 Improved Current Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

3.3.1 PWM-OP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

3.3.2 PWM-Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

3.4 Startup Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

3.5 PWM Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

3.5.1 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

3.5.2 PWM-Latch FF1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

3.5.3 Gate Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

3.6 Current Limiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

3.6.1 Leading Edge Blanking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

3.6.2 Propagation Delay Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

3.7 Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

3.7.1 Basic and Extendable Blanking Mode . . . . . . . . . . . . . . . . . . . . . . . . . . .15

3.7.2 Active Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

3.7.2.1 Entering Active Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

3.7.2.2 Working in Active Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

3.7.2.3 Leaving Active Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

3.7.3 Protection Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

3.7.3.1 Auto Restart mode with extended blanking time . . . . . . . . . . . . . . . . .17

3.7.3.2 Auto Restart without extended blanking time . . . . . . . . . . . . . . . . . . .18

4 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

4.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

4.2 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

4.3 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

4.3.1 Supply Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

4.3.2 Internal Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

4.3.3 PWM Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

4.3.4 Soft Start time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

4.3.5 Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

4.3.6 Current Limiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

4.3.7 CoolMOS® Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

5 Typical CoolMOS® Performance Characteristic . . . . . . . . . . . . . . . . . . .24

CoolSET®-F3R

ICE3BR0665J

Version 2.3 4 19 Nov 2012

6 Input Power Curve . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

7 Outline Dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

8 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

9 Schematic for recommended PCB layout . . . . . . . . . . . . . . . . . . . . . . . .29

CoolSET®-F3R

ICE3BR0665J

Version 2.3 5 19 Nov 2012

Package PG-DIP-8

GNDBA

VCC

n.c.

Drain

Drai n

Pin Configuration and Functionality

1 Pin Configuration and Functionality

1.1 Pin Configuration with PG-DIP-8

Pin Symbol Function

1 BA extended Blanking & Auto-restart

2 FB FeedBack

3 CS Current Sense/

4 Drain

5 Drain

6 n.c. Not connected

7 VCC Controller Supply Voltage

8 GND Controller GrouND

at Tj=110°C

650V

CoolMOS

CoolMOS® Drain

650V

CoolMOS® Drain

650V

Source

1.2 Pin Functionality

BA (extended Blanking & Auto-restart)

The BA pin combines the functions of extendable

nking time for over load protection and the external

bla auto-restart enable. The extendable blanking time function is to extend the built-in 20 ms blanking time by adding an external capacitor at BA pin to ground. The external auto-restart enable function is an external access to stop the gate switching and force the IC enter auto-restart mode. It is triggered by pulling down the BA pin to less than 0.33V.

FB (Feedback)

The information about the regulation is provided by the

o the internal Protection Unit and to the internal

FB Pin t PWM-Comparator to control the duty cycle. The FBSignal is the only control signal in case of light load at the Active Burst Mode.

CS (Current Sense)

The Current Sense pin senses the voltage developed

the series resistor inserted in the source of the

on integrated CoolMOS internal threshold of the Current Limit Comparator, the Driver output is immediately switched off. Furthermore the current information is provided for the PWMComparator to realize the Current Mode.

CoolSET®-F3R

ICE3BR0665J

If voltage in CS pin reaches the

Figure 1 Pin Configuration PG-DIP-8 (top view)

Note: Pin 4 and 5 are shorted

Version 2.3 6 19 Nov 2012

Drain (Drain of integrated CoolMOS

Drain pin is the connection to the Drain of the

egrated CoolMOS

int

VCC (Power Supply)

VCC pin is the positive supply of the IC. The operating ran

ge is between 10.5V and 25V.

GND (Ground)

GND pin is the ground of the controller.

)

Internal Bias

Voltage

Reference

Oscillator

Duty Cycle

max

x3.3

Current Limiting

PWM OP

Current Mode

Soft Start

20.5V

25.5V

Power Management

VCC

85 ... 270 VAC

Bulk

Converter

DC Output

OUT

PWM

Comparator

4.0V

Gate

Driver

0.72

Clock

Sense

10kΩ

C6a

3.05V

1.35V

C10

Auto

Restart

Mode

Thermal Shutdown

0.9V

Power-Down

Reset

GND

VCC

PWM

Section

Control Unit

FF1

C12

0.34V

Leading

Edge

Blanking

220ns

25kΩ

2pF

5.0V

G10

1pF

Propagation-Delay

Compensatio n

5.0V

Undervoltage Lockout

csth

ICE3BR0665J / CoolSET

™-F3R ( Jitter Mode )

Snubber

VCC Drain

CoolMOS

Startup Cel l

C6b

3.5V

G11

Active Burst

Mode

0.67V

10.5V

18V

# : optional external components;

#1 : C

is used to extend the Blanking Time

#2 : T

is used to enable the external Auto-restart feature

Freq. jitter

20ms

Blanking

Time

20ms Blanking

Time

120us Blanking Time

Soft

Start

Block

Soft-Start

Comparator

Spike

Blanking

30us

3.25kΩ

5.0V

T3 0.6V

VCC

Auto-restart

Enable

Signal

0.33V

1 ms

counter

>130°C

CoolSET®-F3R

ICE3BR0665J

Representative Blockdiagram

2 Representative Blockdiagram

Figure 2 Representative Blockdiagram

Version 2.3 7 19 Nov 2012

Internal Bias

Voltage

Reference

Power Management

5.0V

Undervoltage Lockout

18V

10.5V

Power-Down Reset

Active Burst

Mode

Auto Restart

Mode

Startup Cell

VCCDrain

Depl. CoolMOS™

Soft Start block

CoolSET®-F3R

ICE3BR0665J

Functional Description

3 Functional Description

All values which are used in the functional description are typical values. For calculating the worst cases the min/max values which can be found in section 4 Electrical Characteristics have to be considered.

3.1 Introduction

CoolSET®-F3R jitter series (ICE3BRxx65J) is the latest version of the CoolSET application. The particular enhanced features are the built-in features for soft start, blanking window and frequency jitter. It provides the flexibility to increase the blanking window by simply addition of a capacitor in BA pin. In order to further increase the flexibility of the protection feature, an external auto-restart enable features are added. Moreover, the proven outstanding features in CoolSET active burst mode, propagation delay compensation, modulated gate driving, auto-restart protection for Vcc overvoltage, over temperature, over load, open loop, etc.

The intelligent Active Burst Mode can effectively obtain

he lowest Standby Power at light load and no load

t conditions. After entering the burst mode, there is still a full control of the power conversion to the output through the optocoupler, that is used for the normal PWM control. The response on load jumps is optimized and the voltage ripple on V on well controlled in this mode.

The usually external connected RC-filter in the f

eedback line after the optocoupler is integrated in the

IC to reduce the external part count. Furthermore a high voltage Startup Cell is integrated

o the IC which is switched off once the Undervoltage

int Lockout on-threshold of 18V is exceeded. This Startup Cell is part of the integrated CoolMOS startup resistor is no longer necessary as this Startup Cell is connected to the Drain. Power losses are therefore reduced. This increases the efficiency under light load conditions drastically.

Adopting the BiCMOS technology, it can increase the

sign flexibility as the Vcc voltage range is increased

de to 25V.

The CoolSET function. It can further save external component counts.

There are 2 modes of blanking time for high load jump blanking time for the basic mode is set at 20ms while the extendable mode will increase the blanking time by adding an external capacitor at the BA pin in addition to the basic mode blanking time. During this blanking time window the overload detection is disabled. With this concept no further external components are necessary to adjust the blanking window.

Version 2.3 8 19 Nov 2012

-F3R has a built-in 20ms soft start

s; the basic mode and the extendable mode. The

-F3 for the lower power

-F3 are still remained such as the

is minimized. The V

out

. The external

In order to increase the robustness and safety of the

em, the IC provides Auto Restart protection. The

syst Auto Restart Mode reduces the average power conversion to a minimum level under unsafe operating conditions. This is necessary for a prolonged fault condition which could otherwise lead to a destruction of the SMPS over time. Once the malfunction is removed, normal operation is automatically retained after the next Start Up Phase. To make the protection more flexible, an external auto-restart enable pin is provided. When the pin is triggered, the switching pulse at gate will stop and the IC enters the auto-restart mode after the pre-defined spike blanking time.

The internal precise peak current control reduces the

s for the transformer and the secondary diode. The

cost influence of the change in the input voltage on the maximum power limitation can be avoided together with the integrated Propagation Delay Compensation. Therefore the maximum power is nearly independent on the input voltage, which is required for wide range SMPS. Thus there is no need for the over-sizing of the SMPS, e.g. the transformer and the output diode.

Furthermore, this F3R series implements the

requency jitter mode to the switching clock such that

f the EMI noise will be effectively reduced.

3.2 Power Management

out

Figure 3 Power Management

x3.3

PWM OP

Improved Current Mode

0.67V

PWM-Latch

RSQ

Driver

Soft-Start Comparator

Amplified Current Signal

0.67V

Driver

CoolSET®-F3R

ICE3BR0665J

Functional Description

The Undervoltage Lockout monitors the external supply voltage V main line the internal Startup Cell is biased and starts to charge the external capacitor C connected to the VCC pin. This VCC charge current is controlled to 0.9mA by the Startup Cell. When the V exceeds the on-threshold V are switched on. Then the Startup Cell is switched off by the Undervoltage Lockout and therefore no power losses present due to the connection of the Startup Cell to the Drain voltage. To avoid uncontrolled ringing at switch-on, a hysteresis start up voltage is implemented. The switch-off of the controller can only take place when V was entered. The maximum current consumption before the controller is activated is about 150μA.

When V the bias circuit is switched off and the soft start counter is reset. Thus it is ensured that at every startup cycle the soft start starts at zero.

The internal bias circuit is switched off if Auto Restart Mode reduced to 150μA.

Once the malfunction condition is removed, this block will then Mode does not require re-cycling the AC line.

When Active Burst Mode is entered, the internal Bias is switche is kept alive in order to reduce the current consumption below 450μA.

falls below 10.5V after normal operation

VCC

falls below the off-threshold V

VCC

is entered. The current consumption is then

turn back on. The recovery from Auto Restart

d off most of the time but the Voltage Reference

3.3 Improved Current Mode

Figure 4 Current Mode

. When the SMPS is plugged to the

VCC

which is

VCC

=18V the bias circuit

CCon

CCoff

VCC

=10.5V,

Current Mode means the duty cycle is controlled by the slo

pe of the primary current. This is done by comparing

the FB signal with the amplified current sense signal.

Figure 5 Pulse Width Modulation

In case the amplified current sense signal exceeds the FB

signal the on-time T

resetting the PWM-Latch (see Figure 5). The primary current is sensed by the external series

esistor R

r CoolMOS secondary output voltage is insensitive to the line variations. The current waveform slope will change with the line variation, which controls the duty cycle.

The external R the maximum source current of the integrated CoolMOS

To improve the Current Mode during light load con

ditions the amplified current ramp of the PWM-OP is superimposed on a voltage ramp, which is built by the switch T2, the voltage source V1 and a resistor R1 (see Figure 6). Every time the oscillator shuts down for maximum duty cycle limitation the switch T2 is closed by V

OSC

T2 is opened so that the voltage ramp can start. In case of light load the amplified current ramp is too

small Voltage Ramp is a well defined signal for the comparison with the FB-signal. The duty cycle is then controlled by the slope of the Voltage Ramp. By means of the time delay circuit the inverted V until it reaches approximately 156ns delay time (see Figure 7). It allows the duty cycle to be reduced continuously till 0% by decreasing V threshold.

inserted in the source of the integrated

Sense ®

. By means of Current Mode regulation, the

Sense

. When the oscillator triggers the Gate Driver,

to ensure a stable regulation. In that case the

OSC

of the driver is finished by

allows an individual adjustment of

signal, the Gate Driver is switched-off

which is triggered by

below that

Version 2.3 9 19 Nov 2012

PWM OP

0.67V

10kΩ

Oscillator

PWM-Latch

Gate Dri ver

Voltage Ramp

OSC

Soft-Start Comparator

time delay

circuit (156ns)

X3.3

PWM Comparator

OSC

0.67V

max.

Duty Cycle

Gate Driver

Voltage Ramp

156ns time delay

X3.3

PWM OP

Improved Current Mode

PWM Comparator

Soft-Start Comparator

0.67V

Optocoupler

PWM-Latch

Figure 6 Improved Current Mode

CoolSET®-F3R

ICE3BR0665J

Functional Description

3.3.1 PWM-OP

The input of the PWM-OP is applied over the internal leading edge blanking to the external sense resistor

connected to pin CS. R

Sense

current into a sense voltage. The sense voltage is amplified with a gain of 3.3 by PWM OP. The output of the PWM-OP is connected to the voltage source V The voltage ramp with the superimposed amplified current signal is fed into the positive inputs of the PWMComparator C8 and the Soft-Start-Comparator (see Figure 6).

3.3.2 PWM-Comparator

The PWM-Comparator compares the sensed current signal of the integrated CoolMOS

(see Figure 8). VFB is created by an external

signal V

optocoupler or external transistor in combination with the internal pull-up resistor R information of the feedback circuitry. When the amplified current signal of the integrated CoolMOS exceeds the signal VFB the PWM-Comparator switches off the Gate Driver.

converts the source

Sense

with the feedback

and provides the load

Figure 7 Light Load Conditions

Version 2.3 10 19 Nov 2012

Figure 8 PWM Controlling

So ft-S tart

Comparator

Soft Start

Ga te D river

0.67V

x3.3

PWM OP

Soft Start counter

So ft Sta rt

Soft Start finish

So ftS

SoftS

SoftS2

SoftS1

SoftS

Soft Start

Counter

SoftS

32I

SOFTS32

SoftS

Gate Driver

Soft-Star t

CoolSET®-F3R

ICE3BR0665J

Functional Description

3.4 Startup Phase

Figure 9 Soft Start

In the Startup Phase, the IC provides a Soft Start pe

riod to control the primary current by means of a duty cycle limitation. The Soft Start function is a built-in function and it is controlled by an internal counter.

When the V IC starts the Soft Start mode (see Figure 10).

exceeds the on-threshold voltage, the

VCC

The function is realized by an internal Soft Start r

esistor, an current sink and a counter. And the amplitude of the current sink is controlled by the counter (see Figure 11).

Figure 11 Soft Start Circuit

After the IC is switched on, the V controlled such that the voltage is increased stepwisely (32 steps) with the increase of the counts. The Soft Start counter would send a signal to the current sink control in every 600us such that the current sink decrease gradually and the duty ratio of the gate drive increases gradually. The Soft Start will be finished in 20ms (t the Soft Start period, the current sink is switched off.

) after the IC is switched on. At the end of

Soft-Start

SFOFTS

voltage is

Figure 10 Soft Start Phase

Version 2.3 11 19 Nov 2012

Figure 12 Gate drive signal under Soft-Start Phase

SoftS

SOFTS32

4.0V

Soft-Start

OUT

Start-Up

Oscill ator

Duty Cycle

max

Gate Driver

0.75

Clock

PWM Section

FF1

Soft Star t

Comparator

PWM

Comparator

Current Limiting

CoolMOS

Gate

Frequency

Jitter

Soft Start

Block

CoolSET®-F3R

ICE3BR0665J

Functional Description

Within the soft start period, the duty cycle is increasing from zero to maximum gradually (see Figure 12).

3.5 PWM Section

In addition to Start-Up, Soft-Start is also activated at each restart attempt during Auto Restart.

Figure 14 PWM Section Block

Figure 13 Start Up Phase

The Start-Up time t voltage V Start Phase t

By means of Soft-Start there is an effective mini integrated CoolMOS overshoot and it helps to prevent saturation of the transformer during Start-Up.

Version 2.3 12 19 Nov 2012

is settled, must be shorter than the Soft-

OUT

Soft-Start

mization of current and voltage stresses on the

before the converter output

Start-Up

(see Figure 13).

, the clamp circuit and the output

3.5.1 Oscillator

The oscillator generates a fixed frequency of 65KHz wit

h frequency jittering of ±4% (which is ±2.6KHz) at a

jittering period of 4ms. A capacitor, a current source and current sink which

etermine the frequency are integrated. In order to

d achieve a very accurate switching frequency, the charging and discharging current of the implemented oscillator capacitor are internally trimmed. The ratio of controlled charge to discharge current is adjusted to reach a maximum duty cycle limitation of D

Once the Soft Start period is over and when the IC goes i

nto normal operating mode, the switching frequency of the clock is varied by the control signal from the Soft Start block. Then the switching frequency is varied in range of 65KHz ± 2.6KHz at period of 4ms.

3.5.2 PWM-Latch FF1

The output of the oscillator block provides continuous

ulse to the PWM-Latch which turns on/off the

p integrated CoolMOS reset by the PWM comparator, the Soft Start comparator or the Current -Limit comparator. When it is in reset mode, the output of the driver is shut down

. After the PWM-Latch is set, it is

immediately.

max

=0.75.

VCC

PWM-Latch

CoolMOS

Gate Driver

Gate

(internal) V

Gate

ca. t = 130ns

Current Limiting

C10

C12

0.34V

Leading

Edge

Blanking

220ns

G10

Propagation -Delay

Compensation

csth

Active Burst

Mode

PWM Latch

FF1

10k

1pF

PWM-OP

CoolSET®-F3R

ICE3BR0665J

Functional Description

3.5.3 Gate Driver

3.6 Current Limiting

Figure 15 Gate Driver

The driver-stage is optimized to minimize EMI and to pr

ovide high circuit efficiency. The switch on speed is slowed down before it reaches the integrated CoolMOS the rising edge at the output of the driver (see Figure

16).

turn on threshold. That is a slope control of

Figure 17 Current Limiting Block

Figure 16 Gate Rising Slope

Thus the leading switch on spike is minimized. Furt

hermore the driver circuit is designed to eliminate

cross conduction of the output stage. During power up, when VCC is below the undervoltage

lockout is set to low in order to disable power transfer to the

threshold V

secondary side.

, the output of the Gate Driver

VCCoff

There is a cycle by cycle peak c realized by the Current-Limit comparator C10. The source current of the integrated CoolMOS via an external sense resistor R

the source current is transformed to a sense

Sense

voltage V V

Sense

comparator C10 immediately turns off the gate drive by resetting the PWM Latch FF1.

A Propagation Delay Compensation is added to

port the immediate shut down of the integrated

sup CoolMOS influence of the AC input voltage on the maximum output power can be reduced to minimal.

In order to prevent the current limit from distortions

sed by leading edge spikes, a Leading Edge

cau Blanking is integrated in the current sense path for the comparators C10, C12 and the PWM-OP.

The output of comparator C12 is activated by the Gate

10 if Active Burst Mode is entered. When it is

G activated, the current limiting is reduced to 0.34V. This voltage level determines the maximum power level in Active Burst Mode.

which is fed into the CS pin. If the voltage

Sense

exceeds the internal threshold voltage V

with very short propagation delay. Thus the

urrent limiting operation

is sensed

. By means of

Sense

Version 2.3 13 19 Nov 2012

csth,

the

Sense

csth

LEB

= 220ns

Sense

Limit

Propagation Delay

Overshoot1

peak1

Signal1Signal2

Overshoot2

peak2

0,9

0,95

1,05

1,1

1,15

1,2

1,25

1,3

0 0,2 0,4 0,6 0,8 1 1,2 1,4 1,6 1,8 2

with compensation without compensation

Sense

csth

OSC

Signal1 Signal2

Sense

Propagation Delay

max. Du ty Cycle

off time

CoolSET®-F3R

ICE3BR0665J

Functional Description

3.6.1 Leading Edge Blanking

Figure 18 Leading Edge Blanking

Whenever the integrated CoolMOS leading edge spike is generated due to the primaryside capacitances and reverse recovery time of the secondary-side rectifier. This spike can cause the gate drive to switch off unintentionally. In order to avoid a premature termination of the switching pulse, this spike is blanked out with a time constant of t

is switched on, a

= 220ns.

LEB

3.6.2 Propagation Delay Compensation

In case of over-current detection, there is always propagation delay to switch off the integrated CoolMOS induced to the delay, which depends on the ratio of dI/ dt of the peak current (see Figure 19).

. An overshoot of the peak current I

peak

For example, I sense threshold is set to a static voltage level V without Propagation Delay Compensation. A current ramp of dI/dt = 0.4A/µs, or dV propagation delay time of t to an I

peak

delay compensation, the overshoot is only around 2%

= 0.5A with R

peak

overshoot of 14.4%. With the propagation

= 2. The current

Sense

/dt = 0.8V/µs, and a

Sense

Propagation Delay

=1V

csth

=180ns leads

(see Figure 20).

Figure 20 Overcurrent Shutdown

The Propagation Delay Compensation is realized by me

ans of a dynamic threshold voltage V

21). In case of a steeper slope the switch off of the driver is earlier to compensate the delay.

(see Figure

csth

Figure 19 Current Limiting

The overshoot of Signal2 is larger than of Signal1 due

o the steeper rising waveform. This change in the

t slope depends on the AC input voltage. Propagation Delay Compensation is integrated to reduce the overshoot due to dI/dt of the rising primary current. Thus the propagation delay time between exceeding the current sense threshold V of the integrated CoolMOS temperature within a wide range. Current Limiting is then very accurate.

Version 2.3 14 19 Nov 2012

and the switching off

csth

is compensated over

Figure 21 Dynamic Voltage Threshold V

csth

4.0V

1.35V

0.9V

Control Unit

Active Burst Mode

Auto

Restart

Mode

5.0V

20ms

Blanking

Time

20ms

Blanking

Time

Spike

Blanking

30us

4.0V

C6a

3.5V

1.35V

Control Unit

Active

Burst

Mode

Internal Bias

G10

Current Limiting

& G6

C6b

3.05V

G11

20 ms Blanking

Time

CoolSET®-F3R

ICE3BR0665J

Functional Description

3.7 Control Unit

The Control Unit contains the functions for Active Burst Mode and Auto Restart Mode. The Active Burst Mode and the Auto Restart Mode both have 20ms internal Blanking Time. For the Auto Restart Mode, a further extendable Blanking Time is achieved by adding external capacitor at BA pin. By means of this Blanking Time, the IC avoids entering into these two modes accidentally. Furthermore those buffer time for the overload detection is very useful for the application that works in low current but requires a short duration of high current occasionally.

3.7.1 Basic and Extendable Blanking Mode

After the 30us spike blanking time, the Auto Restart Mode is activated.

For example, if C Blanking time = 20ms + C In order to make the startup properly, the maximum C

capacitor is restricted to less than 0.65uF. The Active Burst Mode has basic blanking mode only

ile the Auto Restart Mode has both the basic and the

wh extendable blanking mode.

= 0.22uF, IBK = 13uA

x (4.0 - 0.9) / IBK = 72ms

3.7.2 Active Burst Mode

The IC enters Active Burst Mode under low load

ditions. With the Active Burst Mode, the efficiency

con increases significantly at light load conditions while still maintaining a low ripple on V load jumps. During Active Burst Mode, the IC is controlled by the FB signal. Since the IC is always active, it can be a very fast response to the quick change at the FB signal. The Start up Cell is kept OFF in order to minimize the power loss.

and a fast response on

OUT

Figure 22 Basic and Extendable Blanking Mode

There are 2 kinds of Blanking mode; basic mode and t

he extendable mode. The basic mode is just an internal set 20ms blanking time while the extendable mode has an extra blanking time by connecting an external capacitor to the BA pin in addition to the preset 20ms blanking time. For the extendable mode, the gate G5 is blocked even though the 20ms blanking time is reached if an external capacitor C pin. While the 20ms blanking time is passed, the switch S1 is opened by G2. Then the 0.9V clamped voltage at BA pin is charged to 4.0V through the internal I constant current. G5 is enabled by comparator C3.

Version 2.3 15 19 Nov 2012

is added to BA

Figure 23 Active Burst Mode

The Active Burst Mode is located in the Control Unit. Fig

ure 23 shows the related components.

3.7.2.1 Entering Active Burst Mode

The FB signal is kept monitoring by the comparator C5.

ring normal operation, the internal blanking time

Du counter is reset to 0. Once the FB signal falls below

1.35V, it starts to count. When the counter reach 20ms

1.35V

3.5V

4.0V

0.34V

1.03V

10.5V

VCC

450uA

VCC

3.8mA

OUT

20ms Blanki ng Time

Current limit level during Active Burst Mode

3.05V

Enter ing Active Burst Mode

Leaving Active Burst Mode

Blanking Timer

and FB signal is still below 1.35V, the system enters the Active Burst Mode. This time window prevents a sudden entering into the Active Burst Mode due to large load jumps.

After entering Active Burst Mode, a burst flag is set and the internal bias is switched off in order to reduce the current consumption of the IC to approx. 450uA.

It needs the application to enforce the VCC voltage

ove the Undervoltage Lockout level of 10.5V such

ab that the Startup Cell will not be switched on accidentally. Or otherwise the power loss will increase drastically. The minimum VCC level during Active Burst Mode depends on the load condition and the application. The lowest VCC level is reached at no load condition.

3.7.2.2 Working in Active Burst Mode

After entering the Active Burst Mode, the FB voltage rises as V inactive PWM section. The comparator C6a monitors the FB signal. If the voltage level is larger than 3.5V, the internal circuit will be activated; the Internal Bias circuit resumes and starts to provide switching pulse. In Active Burst Mode the gate G10 is released and the current limit is reduced to 0.34V, which can reduce the conduction loss and the audible noise. If the load at

is still kept unchanged, the FB signal will drop to

OUT

3.05V. At this level the C6b deactivates the internal circuit again by switching off the internal Bias. The gate G11 is active again as the burst flag is set after entering Active Burst Mode. In Active Burst Mode, the FB voltage is changing like a saw tooth between 3.05V and

3.5V (see figure 24).

3.7.2.3 Leaving Active Burst Mode

The FB voltage will increase immediately if there is a

h load jump. This is observed by the comparator C4.

hig Since the current limit is app. 34% during Active Burst Mode, it needs a certain load jump to rise the FB signal to exceed 4.0V. At that time the comparator C4 resets the Active Burst Mode control which in turn blocks the comparator C12 by the gate G10. The maximum current can then be resumed to stabilize the V

starts to decrease, which is due to the

OUT

OUT.

CoolSET®-F3R

ICE3BR0665J

Functional Description

Figure 24 Signals in Active Burst Mode

Version 2.3 16 19 Nov 2012

4.0V

0.9V

Control Unit

Auto

Restart

Mode

5.0V

20ms

Blanking

Time

Spike

Blanking

30us

CoolSET®-F3R

ICE3BR0665J

Functional Description

3.7.3 Protection Modes

The IC provides Auto Restart Mode as the protection feature. Auto Restart mode can prevent the SMPS from destructive states. The following table shows the relationship between possible system failures and the corresponding protection modes.

3.7.3.1 Auto Restart mode with extended anking time

VCC Overvoltage Auto Restart Mode

Overtemperature Auto Restart Mode

Overload Auto Restart Mode

Open Loop Auto Restart Mode

VCC Undervoltage Auto Restart Mode

Short Optocoupler Auto Restart Mode

Auto restart enable Auto Restart Mode

Before entering the Auto Restart protection mode,

of the protections can have extended blanking

some time to delay the protection and some needs to fast react and will go straight to the protection. Overload and open loop protection are the one can have extended blanking time while Vcc Overvoltage, Over temperature, Vcc Undervoltage, short opto-coupler and external auto restart enable will go to protection right away.

After the system enters the Auto-restart mode, the IC

off. Since there is no more switching, the Vcc

will be voltage will drop. When it hits the Vcc turn off threshold, the start up cell will turn on and the Vcc is charged by the startup cell current to Vcc turn on threshold. The IC is on and the startup cell will turn off. At this stage, it will enter the startup phase (soft start) with switching cycles. After the Start Up Phase, the fault condition is checked. If the fault condition persists, the IC will go to auto restart mode again. If, otherwise, the fault is removed, normal operation is resumed.

Figure 25 Auto Restart Mode

In case of Overload or Open Loop, the FB exceeds 4

.0V which will be observed by comparator C4. Then the internal blanking counter starts to count. When it reaches 20ms, the switch S1 is released. Then the clamped voltage 0.9V at V is no external capacitor C reach 4.0V immediately. When both the input signals at AND gate G5 is positive, the Auto Restart Mode will be activated after the extra spike blanking time of 30us is elapsed. However, when an extra blanking time is needed, it can be achieved by adding an external capacitor, C to charge the capacitor C switch S1 is released. The charging time from 0.9V to

4.0V are the extendable blanking time. If C and I 52ms and the total blanking time is 72ms. In combining the FB and blanking time, there is a blanking window generated which prevents the system to enter Auto Restart Mode due to large load jumps.

. A constant current source of IBK will start

is 13uA, the extendable blanking time is around

can increase. When there

connected, the VBA will

from 0.9V to 4.0V after the

is 0.22uF

Version 2.3 17 19 Nov 2012

20.5V

Spik e

Blanking

30us

Thermal Shutdown

>140°C

Auto Restart

mode

VCC

4.0V

Voltage

Refer ence

Contr ol Uni t

Auto Restart Mode Reset

VCC

< 10.5V

120us

Blanking

Time

VCC

25.5V

softs_period

Auto-restart

Enable

Signal

8us

Blanki ng

Time

0.3V

Stop gate driv e

1ms

counter

UVLO

CoolSET®-F3R

ICE3BR0665J

Functional Description

3.7.3.2 Auto Restart without extended blanking time

a trigger signal to the base of the externally added transistor, T enabled, the gate drive switching will be stopped and then the IC will enter auto-restart mode if the signal persists. To ensure this auto-restart function will not be mis-triggered during start up, a 1ms delay time is implemented to blank the unstable signal.

VCC undervoltage is the Vcc voltage drop below Vcc

off threshold. Then the IC will turn off and the start

turn up cell will turn on automatically. And this leads to Auto Restart Mode.

Short Optocoupler also leads to VCC undervoltage as

here is no self supply after activating the internal

t reference and bias.

at the BA pin. When the function is

Figure 26 Auto Restart mode

There are 2 modes of V is during soft start and the other is at all conditions.

The first one is V and during soft_start period and the IC enters Auto Restart Mode. The VCC voltage is observed by comparator C1 and C4. The fault conditions are to detect the abnormal operating during start up such as open loop during light load start up, etc. The logic can eliminate the possible of entering Auto Restart mode if there is a small voltage overshoots of V normal operating.

The 2nd one is V IC enters Auto Restart Mode. This 25.5V Vcc OVP

VCC

overvoltage protection; one

VCC

during

voltage is > 20.5V and FB is > 4.0V

>25.5V and last for 120us and the

protection is inactivated during burst mode. The Thermal Shutdown block monitors the junction

emperature of the IC. After detecting a junction

t temperature higher than 130°C, the Auto Restart Mode is entered.

In case the pre-defined auto-restart features are not

ficient, there is a customer defined external Auto-

suf restart Enable feature. This function can be triggered by pulling down the BA pin to < 0.33V. It can simply add

Version 2.3 18 19 Nov 2012

CoolSET®-F3R

ICE3BR0665J

Electrical Characteristics

4 Electrical Characteristics

Note: All voltages are measured with respect to ground (Pin 5). The voltage levels are valid if other ratings are

not violated.

4.1 Absolute Maximum Ratings

Note: Absolute maximum ratings are defined as ratings, which when being exceeded may lead to destruction

of the integrated circuit. For the same reason make sure, that any capacitor that will be connected to pin 4

discharged before assembling the application circuit.T

(VCC) is

Parameter Symbol Limit Values Unit Remarks

min. max.

limited

limited by

D_Puls

VCC

thJA

sold

ESD

Switching drain current, pulse width t limited by T

Pulse drain current, pulse width t by T

Avalanche energy, repetitive t max. T

Avalanche current, repetitive t max. T

=150°C

VCC Supply Voltage V

FB Voltage V

BA Voltage V

CS Voltage V

Junction Temperature T

Storage Temperature T

Thermal Resistance Junction -Ambient

Soldering temperature, wavesoldering on

ly allowed at leads

ESD Capability (incl. Drain Pin) V

Repetitive avalanche causes additional power losses that can be calculated as PAV=EAR*f

According to EIA/JESD22-A114-B (discharging a 100pF capacitor through a 1.5kΩ series resistor)

- 9.95 A

- 15.75 A

- 0.47 mJ

- 2.5 A

-0.3 27 V

-0.3 5.5 V

-40 150 °C Controller & CoolMOS

-55 150 °C

- 90 K/W

- 260 °C 1.6mm (0.063in.) from

- 2 kV Human body model

=25°C unless otherwise specified.

case for 10s

Version 2.3 19 19 Nov 2012

CoolSET®-F3R

ICE3BR0665J

Electrical Characteristics

4.2 Operating Range

Note: Within the operating range the IC operates as described in the functional description.

Parameter Symbol Limit Values Unit Remarks

min. max.

VCC Supply Voltage V

Junction Temperature of

roller

Cont

Junction Temperature of Cool

MOS

VCC

jCon

jCoolMOS

-25 130 °C Max value limited due to thermal

25 V Max value limited due to Vcc OVP

VCCoff

shut down of controller

-25 150 °C

4.3 Characteristics

4.3.1 Supply Section

Note: The electrical characteristics involve the spread of

temperature range T related to 25°C. If not otherwise stated, a supply voltage of V

from – 25 °C to 125 °C. Typical values represent the median values, which are

Parameter Symbol Limit Values Unit Test Condition

Start Up Current I

VCCstart

values within the specified supply voltage and junction

= 18 V is assumed.

min. typ. max.

- 150 250 μA V

VCC

=17V

VCC Charge Current I

Leakage Current of Start Up Cell and CoolMOS

Supply Current with Inactive Gate

Supply Current with Active Gate I

Supply Current in Auto Restart Mode with Inactive Ga

Supply Current in Active Burst

with Inactive Gate

Mode

VCC Turn-On Threshold VCC Turn-Off Threshold VCC Turn-On/Off Hysteresis

VCCcharge1

VCCcharge2

VCCcharge3

StartLeak

VCCsup1

VCCsup2

VCCrestart

VCCburst1

VCCburst2

VCCon

VCCoff

VCChys

- - 5.0 mA V

0.55 0.9 1.60 mA V

- 0.7 - mA V

- 0.2 50 μA V

- 1.5 2.5 mA

- 3.8 4.2 mA IFB = 0A

- 250 - μA IFB = 0A

- 450 950 μA VFB = 2.5V

- 450 950 μA V

17.0

9.8

18.0

10.5

7.5

19.0

11.2

V V V

= 0V

VCC

= 1V

VCC

=17V

VCC

= 450V

Drain

=100°C

at T

= 11.5V,VFB = 2.5V

VCC

Version 2.3 20 19 Nov 2012

CoolSET®-F3R

ICE3BR0665J

4.3.2 Internal Voltage Reference

Parameter Symbol Limit Values Unit Test Condition

min. typ. max.

Trimmed Reference Voltage V

REF

4.3.3 PWM Section

Parameter Symbol Limit Values Unit Test Condition

Fixed Oscillator Frequency f

Frequency Jittering Range f

Frequency Jittering period T

Max. Duty Cycle D

OSC1

OSC2

jitter

max

4.90 5.00 5.10 V measured at pin FB

min. typ. max.

56.5 65.0 73.5 kHz

59.8 65.0 70.2 kHz Tj = 25°C

- ±2.6 - kHz Tj = 25°C

- 4.0 - ms Tj = 25°C

0.70 0.75 0.80

Electrical Characteristics

= 0

Min. Duty Cycle D

PWM-OP Gain A

Voltage Ramp Offset V

Operating Range Min Level V

Operating Range Max level V

FB Pull-Up Resistor R

The parameter is not subjected to production test - verified by design/characterization

min

Offset-Ramp

FBmin

FBmax

0 - - VFB < 0.3V

3.1 3.3 3.5

- 0.67 - V

- 0.5 - V

- - 4.3 V CS=1V, limited by Comparator C4

9 15.4 22 kΩ

4.3.4 Soft Start time

Parameter Symbol Limit Values Unit Test Condition

min. typ. max.

Soft Start time t

- 20.0 - ms

Version 2.3 21 19 Nov 2012

CoolSET®-F3R

ICE3BR0665J

Electrical Characteristics

4.3.5 Control Unit

Parameter Symbol Limit Values Unit Test Condition

min. typ. max.

Clamped V Normal Operating Mode

Blanking time voltage limit for Compa

Over Load & Open Loop Detection Limi

Active Burst Mode Level for Compa

Overvoltage Detection Limit for Compa

voltage during

rator C3

t for Comparator C4

rator C5

rator C6a

rator C6b

rator C1

BAclmp

BKC3

FBC4

FBC5

FBC6a

FBC6b

VCCOVP1

0.85 0.9 0.95 V VFB = 4V

3.85 4.00 4.15 V

1.25 1.35 1.45 V

3.35 3.50 3.65 V After Active Burst

2.93 3.05 3.16 V After Active Burst

Mode is entered

19.5 20.5 21.5 V VFB = 5V

Overvoltage Detection Limit for

rator C2

Compa

Auto-restart Enable level at BA pin V

Charging current at BA pin I

Thermal Shutdown

Built-in Blanking Time for Over

load Protection or enter

VCCOVP2

jSD

25.0 25.5 26.5 V

0.25 0.33 0.4 V >30μs

10 13.0 16.9 μA Charge starts after the

built-in 20ms blanking time elapsed

130 140 150 °C Controller

- 20 - ms without external

capacitor at BA pin

Active Burst Mode

Inhibit Time for Auto-Restart

able function during start up

Spike Blanking Time before AutoRest

art Protection

The parameter is not subjected to production test - verified by design/characterization. The thermal shutdown

IHAE

Spike

- 1.0 - ms Count when VCC>18V

- 30 - μs

temperature refers to the junction temperature of the controller.

Note: The trend of all the voltage levels in the Control Unit is the same regarding the deviation except V

VCCOVP

Version 2.3 22 19 Nov 2012

CoolSET®-F3R

ICE3BR0665J

Electrical Characteristics

4.3.6 Current Limiting

Parameter Symbol Limit Values Unit Test Condition

min. typ. max.

Peak Current Limitation (incl. Propagation Delay)

Peak Current Limitation during

tive Burst Mode

Leading Edge Blanking t

CS Input Bias Current I

4.3.7

CoolMOS® Section

LEB

CSbias

csth

CS2

0.96 1.03 1.10 V dV

0.29 0.34 0.38 V

- 220 - ns

-1.5 -0.2 - μA V

/ dt = 0.6V/μs

sense

(see Figure 20)

=0V

Parameter Symbol Limit Values Unit Test Condition

min. typ. max.

Drain Source Breakdown Voltage V

Drain Source On-Resistance R

Effective output capacitance, energy re

lated

Rise Time t

Fall Time t

The parameter is not subjected to production test - verified by design/characterization

Measured in a Typical Flyback Converter Application

rise

fall

650 - - V Tj = 110°C

(BR)DSS

DSon

o(er)

0.65

1.37

- 26 - pF VDS = 0V to 480V

- 30

0.75

1.58ΩΩ

- ns

Refer to Figure 30 for

her V

(BR)DSS

different T

Tj = 25°C T

at I

=125°C

= 2.5A

Version 2.3 23 19 Nov 2012

Safe Operating Area for ICE3A(B)R0665J

= f ( VDS )

parameter : D = 0, T

= 25deg.C

0.0001

0.001

0.01

0.1

100

1 10 100 1000

VDS [V]

[A]

tp = 1000ms

tp = 1ms tp = 10ms tp = 100ms

tp = 0.1ms

tp = 0.01m s

SOA temperature derating coefficient curve ( package dissipation ) for F3 & F2 CoolSET

100

120

0 20 40 60 80 100 120 140

Ambient/Case temperature Ta/Tc [deg.C]

Ta : DIP, Tc : TO220

SOA temperature derating coefficient [%]

CoolSET®-F3R

ICE3BR0665J

Typical CoolMOS® Performance Characteristic

5 Typical CoolMOS® Performance Characteristic

Figure 27 Safe Operating area (SOA) curve for ICE3BR0665J

Figure 28 SOA temperature derating coefficient curve

Version 2.3 24 19 Nov 2012

Allowable Power Dissipation for F3 CoolSET in DIP-8 package

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

0 20 40 60 80 100 120 140

Ambient temperature, T

[deg.C]

Allowable Power Dissipation, P

tot

[W]

540

580

620

660

700

-60 -20 20 60 100 140 180

[°C]

BR(DSS)

[V]

CoolSET®-F3R

ICE3BR0665J

Figure 29 Power dissipation; P

tot

Typical CoolMOS® Performance Characteristic

=f(Ta)

Figure 30 Drain-source breakdown voltage; V

Version 2.3 25 19 Nov 2012

BR(DSS)

=f(Tj)

Ambient Temperature [°C]

Input power (85~265Vac) [W]

PI-001-ICE3BR0665J_85Vac

0 10 20 30 40 50 60 70 80 90 100 110 120 130

Ambient Temperature [°C]

Input power (230Vac) [W]

PI-002-ICE3BR0665J_230Vac

100

0 102030405060708090100110120130

CoolSET®-F3R

ICE3BR0665J

Input Power Curve

6 Input Power Curve

Two input power curves giving the typical input power versus ambient temperature are showed below; Vin=85Vac~265Vac (Figure 31) and Vin=230Vac+/-15% (Figure 32). The curves are derived based on a typical discontinuous mode flyback model which considers either 50% maximum duty ratio or 100V maximum secondary to primary reflected voltage (higher priority). The calculation is based on no copper area as heatsink for the device. The input power already includes the power loss at input common mode choke, bridge rectifier and the CoolMOS.The device saturation current (I

To estimate the output power of the device, it is simply mult temperature with the estimated efficiency for the application. For example, a wide range input voltage (Figure 31), operating temperature is 50°C, estimated efficiency is 85%, then the estimated output power is 42W (49W * 85%).

@ Tj=125°C) is also considered.

D_Puls

iplying the input power at a particular operating ambient

Figure 31 Input power curve Vin=85~265Vac; Pin=f(Ta)

Figure 32 Input power curve Vin=230Vac+/-15%; Pin=f(Ta)

Version 2.3 26 19 Nov 2012

PG-DIP-8 (Plastic Dual In-Line Outline)

CoolSET®-F3R

ICE3BR0665J

7 Outline Dimension

Outline Dimension

Figure 33 PG-DIP-8 (Pb-free lead plating Plastic Dual-in-Line Outline)

Version 2.3 27 19 Nov 2012

Marking

8 Marking

Figure 34 Marking for ICE3BR0665J

CoolSET®-F3R

ICE3BR0665J

Marking

Version 2.3 28 19 Nov 2012

C11

bulk cap

R11

D11

C12

IC12

R12

C13

C16

C15

C14

D13

R14

R23

R22

IC21

C23

R24

C22

R21

R25

GND

D21

C21

F3 CoolSET schematic for recommended PCB layout

R13

Z11

TR1

BR1

Y-CAP

X-CAP

FUSE1

Y-CAP

GND

Spark Gap 3

Spark Gap 4

D11

Spark Gap 1

Spark Gap 2

GND NC

VCC

DRAIN

CoolSET

IC11

CoolSET®-F3R

ICE3BR0665J

Schematic for recommended PCB layout

9 Schematic for recommended PCB layout

Figure 35 Schematic for recommended PCB layout

General guideline for PCB layout design using F3/F3R CoolSET

1. “Star Ground “at bulk capacitor ground, C11: “Star Ground “means all primary DC grounds should be connected to the ground of bulk capacitor C11

tely in one point. It can reduce the switching noise going into the sensitive pins of the CoolSET

separa

effectively. The primary DC grounds include the followings. a. DC ground of the primary auxiliary winding in power transformer, TR1, and ground of C16 and Z11. b. DC ground of the current sense resistor, R12 c. DC ground of the CoolSET

device, GND pin of IC11; the signal grounds from C13, C14, C15 and collector

of IC12 should be connected to the GND pin of IC11 and then “star “connect to the bulk capacitor ground. d. DC ground from bridge rectifier, BR1 e. DC ground from the bridging Y-capacitor, C4

2. High voltage traces clearance: High voltage traces should keep enough spacing to the n

a. 400V traces (positive rail of bulk capacit b. 600V traces (drain voltage of CoolSET

3. Filter capacitor close to the controller ground: Filter capacitors, C13, C14 and C15 should be placed as

as possible so as to reduce the switching noise coupled into the controller.

Guideline for PCB layout design when >3KV lightning surge test applied (refer to Figure 35):

1. Add spark gap Spark gap is a pair of saw-tooth like copper plate f

charge during surge test through the sharp point of the saw-tooth plate.

a. Spark Gap 3 and Spark Gap 4, input common mode choke, L1:

Gap separation is around 1.5mm (no safety concern)

or C11) to nearby trace: > 2.0mm

IC11) to nearby trace: > 2.5mm

(refer to Figure 35):

earby traces. Otherwise, arcing would incur.

close to the controller ground and the controller pin

acing each other which can discharge the accumulated

device

Version 2.3 29 19 Nov 2012

CoolSET®-F3R

ICE3BR0665J

Schematic for recommended PCB layout

b. Spark Gap 1 and Spark Gap 2, Live / Neutral to GROUND:

These 2 Spark Gaps can be used when the lightning surge requirement is >6KV. 230Vac input voltage application, the gap separation is around 5.5mm 115Vac input voltage application, the gap separation is around 3mm

2. Add Y-capacitor (C2 and C3) in the Live and Neutral to ground even though it is a 2-pin input

3. Add negative pulse clamping diode, D11 to the Current sense resistor, R12:

The negative pulse clamping diode can reduce the negative pulse going into the CS pin of the CoolSET® and reduce the abnormal behavior of the CoolSET

The principle behind is to drain the high surge voltage from Live/Neutral to Ground without passing through the sensitive components such as the primary controller, IC11.

. The diode can be a fast speed diode such as IN4148.

Version 2.3 30 19 Nov 2012

Total Quality Management

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Dazu gehört eine bestimmte Geisteshaltung unserer Mitarbeiter. Total Quality im Denken und Handeln gegenüber Kollegen, Lieferanten und Ihnen, unserem Kunden. Unsere Leitlinie ist jede Aufgabe mit „Null Fehlern“ zu lösen – in offener Sichtweise auch über den eigenen Arbeitsplatz hinaus – und uns ständig zu verbessern.

Unternehmensweit orientieren wir uns dabei auch an „top“ (Time Optimized Processes), um Ihnen durch größere Schnelligkeit den entscheidenden Wettbewerbsvorsprung zu verschaffen.

Geben Sie uns die Chance, hohe Leistung durch umfassende Qualität zu beweisen.

Wir werden Sie überzeugen.

Quality takes on an allencompassing significance at Semiconductor Group. For us it means living up to each and every one of your demands in the best possible way. So we are not only concerned with product quality. We direct our efforts equally at quality of supply and logistics, service and support, as well as all the other ways in which we advise and attend to you.

Part of this is the very special attitude of our staff. Total Quality in thought and deed, towards co-workers, suppliers and you, our customer. Our guideline is “do everything with zero defects”, in an open manner that is demonstrated beyond your immediate workplace, and to constantly improve.

Throughout the corporation we also think in terms of Time Optimized Processes (top), greater speed on our part to give you that decisive competitive edge.

Give us the chance to prove the best of performance through the best of quality – you will be convinced.

http://www.infineon.com

Published by Infineon Technologies AG

Datasheet ICE3BR0665JXKLA1 Specification

Specifications and Main Features

Frequently Asked Questions

User Manual

1 Pin Configuration and Functionality

1.1 Pin Configuration with PG-DIP-8

1.2 Pin Functionality

2 Representative Blockdiagram

3 Functional Description

3.1 Introduction

3.2 Power Management

3.3 Improved Current Mode

3.3.1 PWM-OP

3.3.2 PWM-Comparator

3.4 Startup Phase

3.5 PWM Section

3.5.1 Oscillator

3.5.2 PWM-Latch FF1

3.5.3 Gate Driver

3.6 Current Limiting

3.6.1 Leading Edge Blanking

3.6.2 Propagation Delay Compensation

3.7 Control Unit

3.7.1 Basic and Extendable Blanking Mode

3.7.2 Active Burst Mode

3.7.2.1 Entering Active Burst Mode

3.7.2.2 Working in Active Burst Mode

3.7.2.3 Leaving Active Burst Mode

3.7.3 Protection Modes

3.7.3.2 Auto Restart without extended blanking time

4 Electrical Characteristics

4.1 Absolute Maximum Ratings

4.2 Operating Range

4.3 Characteristics

4.3.1 Supply Section

4.3.2 Internal Voltage Reference

4.3.3 PWM Section

4.3.4 Soft Start time

4.3.5 Control Unit

4.3.6 Current Limiting

CoolMOS® Section

5 Typical CoolMOS® Performance Characteristic

6 Input Power Curve

7 Outline Dimension

8 Marking

9 Schematic for recommended PCB layout