Datasheet IC-Delta 1A Specification

November 1990
Edition 5.0

DATA SHEET

MB1502

SERIAL INPUT PLL FREQUENCY SYNTHESIZER

LOW POWER SERIAL INPUT PLL SYNTHESIZER

WITH 1.1 GHz PRESCALER

The Fujitsu MB1502, utilizing BI-CMOS technology , is a single chip serial input PLL
synthesizer with pulse-swallow function. The MB1502 contains a 1.1GHz two
modulus prescaler that can select of either 64/65 or 128/129 divide ratio, control
signal generator, 16-bit shift register, 15-bit latch, programmable reference divider
(binary 14-bit programmable reference counter), 1-bit switch counter, phase
comparator with phase conversion function, charge pump, crystal oscillator, 19-bit
shift register, 18-bit latch, programmable divider (binary 7-bit swallow counter and
binary 1 1-bit programmable counter) and analog switch to speed up lock up time.

It operates supply voltage of 5V typ. and achieves very low supply current of 8mA typ.
realized through the use of Fujitsu Advanced Process Technology.

Plastic Package

DIP-16P-M04

FEATURES

• High operating frequency: f

• Pulse swallow function: 64/65 or 128/129

• Low supply current: I

=8mA typ.

CC

• Serial input 18-bit programmable divider consisting of:
— Binary 7-bit swallow counter: 0 to 127
— Binary 11-bit programmable counter: 16 to 2047

• Serial input 15-bit programmable reference divider consisting of:
— Binary 14-bit programmable reference counter: 8 to 16383
— 1-bit switch counter (SW) sets divide ratio of prescaler

• On-chip analog switch achieves fast lock up time

• 2 types of phase detector output

— On-chip charge pump (Bipolar type)
— Output for external charge pump

• Wide operating temperature: –40C to +85C

• 16-pin Plastic DIP Package (Suffix: —P)

16-pin Plastic Flat Package (Suffix: —PF)

ABSOLUTE MAXIMUM RATINGS (See NOTE)

RatIng Symbol Value Unit

Power Supply Voltage

Output Voltage V
Open-drain Voltage V
Output Current I
Storage Temperature T

NOTE: Permanent device damage may occur if the above Absolute Maximum RatIngs are exceed-

ed.Functional operation should be restricted to the condItions as detailed in the operational
sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.

IN MAX

=1.1GHz (V

V

CC

V

P

OUT

OOP

OUT

STG

=10dBm)

IN MIN

–0.5 to +7.0 V
VCC to 10.0 V

–0.5 to VCC +0.5 V

–0.5 to 0.8 V

± 10 mA

–55 to +125 C

Plastic Package

FPT-16P–M06

Pin Assignment

OUT

V

V

CC

D

LD

f

1

IN

2
3

P

4
5

O

6
7
8

IN

OSC

OSC

GND

This device contains circuitry to protect the inputs against
damage due to high static voltages or electric fields. However,
it is advised that normal precautions be taken to avoid
application of any voltage higher than maximum rated voltages
to this high impedance circuit.

(TOP VIEW)

16
15
14
13
12
11
10

∅R
∅P

f

OUT

BiSW
FC
LE
Data

9

Clock

     

MB1502

MB1502 Block Diagram

OSC

OSC

V

CC

GND

LE

OUT

f

4

16-Bit Shift Register

16-Bit Shift Register

6

BiSW

13

12

7

FC

LD

11

15-Bit Latch

15-Bit Latch

Programmable

Reference Divider

1

IN

Oscillator

Crystal

Binary 14-Bit
Reference Counter

1-bit
SW

Phase
Comparator

Circuit

16

15

∅R

∅P

2

19-Bit Shift Register

3

V

19-Bit Shift Register

Charge

P

Pump

5

D

O

8

in

Prescaler
Circuit

7-Bit Latch

18-Bit Latch

1 1-Bit Latch

14

f

OUT

Programmable Divider

Data

Clock

10

9

Control
1-Bit Latch

Binary 7-Bit
Swallow Counter

Binary 11-Bit
Programmable Counter

Control Circuit

2

PIN DESCRIPTION

MB1502

Pin
No.

1
2

3 V
4 V

5 D

Pin

Name

OSC

OSC

CC

OUT

P

O

I/O Description

I

IN

O

— Power supply input for charge pump and analog switch.
— Power supply voltage input.

O

Oscillator input.
Oscillator output.
A crystal is placed between OSC

Charge pump output.
The characteristics of charge pump is reversed depending upon FC input.

6 GND — Ground

Phase comparator output.

7 LD O

Normally this pin outputs high level. While the phase difference of f
pin outputs low level.

8 f

IN

9 Clock I

Prescaler input.

l

The connection with an external VCO should be AC connection.
Clock input for 19-bit shift register and 16-bit shift register.

On rising edge of the clock shifts one bit of data into the shift registers.
Binary serial data input.

10 Data l

The last bit of the data is a control bit which specified destination of shift registers.
When this bit is high level and LE is high level, the data stored in shift register is transferred to 15-bit latch.
When this bit is low level and LE is high level, the data is transferred to 18-bit latch.

Load enable input (with internal pull up resistor).

11 LE I

When LE is high or open, the data stored in shift register is transferred into latch depending upon the control
bit. At the time, internal charge pump output to be connected to BISW pin because internal analog switch
becomes ON state.

Phase select input of phase comparator (with internal pull up resistor).

12 FC l

When FC is low level, the characteristics of charge pump, phase comparator is reversed.
FC input signal is also used to control f

Analog switch output.

13 BISW O

Usually BISW pin is set high-impedance state. When internal analog switch is ON (LE pin is high level), this
pin outputs internal charge pump state.

Monitor pin of phase comparator input.

14 f

15
16

OUT

∅P
∅R

O

O
O

f

OUT

depending upon FC pin input level.
Outputs for external charge pump.

The characteristics are reversed according to FC input.
∅P pin is N-channel open drain output.

and OSC

IN

OUT pin (test pin) output level for fr or f

OUT

.

, and fp exists, this

r

.

p

pin outputs either programmable reference divider output (fr) or programmable divider output (fp)

3

MB1502

FUNCTIONAL DESCRIPTIONS

SERIAL DATA INPUT

Serial data input is achieved by three inputs, such as Data pin, Clock pin and LE pin. Serial data input controls 15-bit programmable
reference divider and 18-bit programmable divider, respectively.

Binary serial data is input to Data pin.
On rising edge of clock shifts one bit of serial data into the internal shift registers and when load enable pin is high level or open, stored

data is transferred into latch depending upon the control bit.
Control data “H” data is transferred into 15-bit latch.
Control data “L” data is transferred into 18-bit latch.

PROGRAMMABLE REFERENCE DIVIDER

Programmable reference divider consists of 16-bit shift register, 15-bit latch and 14-bit reference counter. Serial 16-bit data format is
shown below.

Control bit Divide ratio of prescaler setting bit
LSB MSB

C S1S2S3S4S5S6S7S8S9S10S11S12S13S14S

Divide ratio of programmable reference counter setting bit

14-BIT PROGRAMMABLE REFERENCE COUNTER DIVIDE RATIO

Divide

Ratio

R

8 0 0 0 0 0 0 0 0 0 0 1 0 0 0
9 0 0 0 0 0 0 0 0 0 0 1 0 0 1

• • • • • • • • • • • • • • •

16383 1 1 1 1 1 1 1 1 1 1 1 1 1 1

NOTES: Divide ratio less than 8 is prohibited.

S14S13S12S11S10S9S8S7S6S5S4S3S2S

Divide ratio: 8 to 16383
SW: This bit selects divide ratio of prescaler.
SW=H : 64
SW=L :128
S1 to S14: These bits select divide ratio of programmable reference divider.
C: Control bit (sets as high level).
Data is input from MSB side.

W

1

PROGRAMMABLE DIVIDER

Programmable divider consists of 19-bit shift register, 18-bit latch, 7-bit swallow counter and 11-bit programmable counter.
Serial 19-bit data format is shown on following page.

4

Control bit
LSB MSB

C

S1S2S3S4S5S6S7S8S

MB1502

S

S

S

S

S

S

S

S

S

1

1

1

1

1

1

1

1

9

0

1

2

3

4

5

6

1

7

8

Divide ratio of swallow

Divide ratio of programmable

counter setting bit

7-BIT SWALLOW COUNTER DIVIDE RATIO

Divide

Ratio

A
0 0 0 0 0 0 0 0
1 0 0 0 0 0 0 1

• • • • • • • •

127 1 1 1 1 1 1 1

NOTE: Divide ratio: 0 to 127

S7S6S5S4S3S2S

1

11-BIT PROGRAMMABLE COUNTER DIVIDE RATIO

S

S

S

S

S

S

S

S

Divide

Ratio

N

16 0 0 0 0 0 0 1 0 0 0 1
17 0 0 0 0 0 0 1 0 0 0 1

• • • • • • • • • • • •

2047 1 1 1 1 1 1 1 1 1 1 1

1

1

1

1

1

1

8

7

6

5

4

1

3

2

S

1

1

1

0

counter setting bit

S9S

8

NOTES: Divide ratio less than 16 is prohibited.

Divide ratio: 16 to 2047
S1 to S7: Swallow counter divide ratio setting bit. (0 to 127)
S8 to S18: Programmable counter divide ratio setting bit. (16 to 2047)
C: Control bit (sets as low level).
Data is input from MSB side.

PULSE SWALLOW FUNCTION

f

= [(PxN)+A] x f

vco

f

: Output frequency of external voltage controlled oscillator (VCO)

VCO

N: Preset divide ratio of binary 11-bit programmable counter (16 to 2047)
A: Preset divide ratio of binary 7-bit swallow counter (0≤A≤127, A<N)

: Output frequency of the external reference frequency oscillator

f

OSC

R: Preset divide ratio of binary 14-bit programmable reference counter (8 to 16383)
P: Preset modulus of external dual modulus prescaler (64 or 128)

osc

÷ R

5

MB1502

Data

Clock

LE

Serial Data Input Timing

S18=MSB

*(SW) (S14) (S8) (S7) (S1) (C: Control bit)

(C: Control bit)S17 S10 S9 S1=LSB

t

1

– t5 ≥ 1µs

t

1

NOTES: Parenthesis data is used for setting divide ratio of programmable reference divider.

On rising edge of clock shifts one bit of data in the shift register.

t

2

t

3

t

5

t

4

PHASE CHARACTERISTICS

FC pin is provided to change phase characteristics of phase comparator. Characteristics of internal charge pump output level (Do),
phase comparator output level (
comparator is controlled by FC pin input level. The relation between outputs (D

FC=H or open FC=L

D

∅R ∅P

O

fr > f
fr < f
fr = f

Note: Z = (High impedance)

H L L (fr) L H Z (fp)

p
p
p

L H Z (fr) H L L (fp)

Z L Z (fr) Z L Z (fp)

∅R, ∅P) are reversed depending upon FC pin input level. Also, monitor pin (f

f

OU

T

D

O

∅R ∅P

f

OU

T

, ∅R, ∅P) and FC input level are shown below.

O

) output level of phase

OUT

1

VCO CHARACTERISTICS
Depending upon VCO characteristics,
FC pin should be set accordingly:

— When VCO characteristics are like

1,

FC should be set High or open circuit;
— When VCO characteristics are like

2,

FC should be set Low.

VCO OUTPUT FREQUENCY

VCO INPUT VOLTAGE

6

2

fr

fp

LD

Do

MB1502

H

Z

L

NOTES: Phase difference detection range: –2π to +2π

Spike appearance depends on charge pump characteristics. Also, the spike is output in order to diminish dead band.

> fp or fr < fp, spike might not appear depending upon charge pump characteristics.

When f

r

ANALOG SWITCH

ON/OFF of analog switch is controlled by LE input signal. When the analog switch is ON, internal charge pump output (DO) to be
connected to BlSW pin. When the analog switch is OFF, BlSW pin is set to high-impedance state.

LE=H (Changing the divide ratio of internal prescaler) : Analog switch=ON
LE=L (Normal operating mode): Analog switch=OFF

LPF time constant is decreased in order to insert a analog switch between LPF1 and LPF2 when channel of PLL is changing.
Thus, lock up time is decreased, that is, fast lock up time is achieved.

Do

CHARGE PUMP LPF-1

ANALOG SW

(CONTROL SIGNAL)

LPF-2

BISW

VCO

RECOMMENDED OPERATING CONDITIONS

Parameter Symbol

V

Power Supply Voltage

Input Voltage V
Operating Temperature T

Min Typ Max

CC

V

P
I

A

4.5 5.0 5.5 V

V

CC

GND V

–40 85 C

Value

V

P

Unit

8.0 V

CC

V

7

MB1502

Except f

i

Data

ELECTRICAL CHARACTERISTICS

(Vcc=4.5 to 5.5V, TA=–40 to +85oC, unless otherwise noted.)

Parameter Symbol Condition

Power Supply Current I

f

Operating Frequency

Input Sensitivity

High-level Input Voltage
Low-level Input Voltage
High-level Input Current
Low-level Input Current

Input Current

High-level Output Current
Low-level Output Current
N-channel Open Drain Cutoff

Current

Output Current

Analog Switch On Resistor R

in

OSC

IN

f

in

OSC

IN

Except f

in

and OSC

n
IN

Data

Clock

OSC

IN

LE, FC I

Except D

and

OSC

O

OUT

DO, ∅P I

Except D

and

OSC

O

OUT

f

V

I

V
V

CC

f

in

OSC

V

fin

OSC

V

IH

V

IL

I

IH

I

IL

OSC

LE

OH

OL

OFF

I

OH

I

OL

ON

Value

Min Typ Max

Note 1 8.0 12.0 mA
Note2 10 1100 MHz

12 20 MHz

–10 6 dBm

0.5 V

VCCx0.7 V

VCCx0.3 V

1.0 A

–1.0 A

±50 A
–60 A

VCC = 5 V 4.4 V

0.4 V

VP = VCC to 8V

= GND to 8V

V

OOP

–1.0 mA

1.0 mA
25 

1.1 µA

Unit

PP

NOTE: 1: f in = 1.1GHz, OSClN=12MHz, Vcc=5V. Inputs are grounded and outputs are open.

2: AC coupling. Minimum operating frequency is measured when a capacitor 1000pF is connected.

8

TYPICAL CHARACTERISTICS CURVES

INPUT SENSITIVITY CHARACTERISTICS

MB1502

9

MB1502

INPUT IMPEDANCE CHARACTERISTICS

10

TYPICAL APPLICATION EXAMPLE

V

(6V)

PX

10kΩ

MB1502

OUTPUT

LPF VCO

12kΩ

Charge Pump Selection
(Internal or external)

12kΩ

∅R ∅PFCf

10kΩ

p

f

r

LE Data Clock

16 15 14 13 12 11 10 9

MB1502

12345678

OSC

IN

OSC

OUTVP

V

CC

D

O

FROM
CONTROLLER

47kΩ 47kΩ

f

LDGND

in

X’tal

6V 5V

C

1

C

2

0.1µF

, Vpx: 8V max

p

V

, C2: Depends on crystal oscillator

C

1

LE, FC : With internal pull up resistor
∅P : Open drain output

1000pF

33kΩ

0.01µF

V

100kΩ

CC

(5V)

10kΩ

LOCK DET

11

MB1502

PACKAGE DIMENSIONS

16–Lead Plastic Dual In–Line Package

(Case No.: DIP–16P–M04)

.770

INDEX-1

INDEX-2

+.012

.039

–0
+0.30

(0.99 )

–0

.050(1.27)

MAX

1991 FUJITSU LIMITED D16033S-2C

+.008

(19.55 )

–.012

.100(2.54)

TYP

+0.20
–0.30

.060

(1.52 )

+.012
–0

+0.30
–0

.018

(0.46

±.003

±0.08)

±.010

.244

(6.20

±0.25)

.172(4.36)MAX

.118(3.00)MIN

.020(0.51)MIN

.300(7.62)

TYP

.010

±.002

(0.25±0.05)

Dimensions in
inches (millimeters)

15

°MAX

12

.050(1.27)

TYP

.400

INDEX

+.010
–.008

+0.25

(10.15 )

–0.20

.018

±.004

(0.45

±0.10)

16–Lead Plastic Flat Package

(Case No.: FPT–16P–M06)

±.016

.307

(7.80

±0.40)

.209

±.012

(5.30

“B”

∅.005(0.13)

±0.30)

M

.089(2.25)MAX

(MOUNTING HEIGHT)

.002(0.05)MIN

(STAND OFF HEIGHT)

.268

+.016
–.008

.006

+0.40

(6.80 )

–0.20

.020

±.008

(0.50

±0.20)

+.002

(0.15 )

–.001

MB1502

+0.05
–0.02

.004(0.10)

.350(8.89) REF

1991 FUJITSU LIMITED F16015S-2C

“A”

Details of “A” part

.016(0.40)

.008(0.20)

.007(0.18)

MAX

.027(0.68)

MAX

Details of “B” part

.006(0.15)

.008(0.20)

.007(0.18)

MAX

.027(0.68)

MAX

Dimensions in
inches (millimeters)

13

MB1502

All Rights Reserved.
Circuit diagrams utilizing Fujitsu products are included as a means of illustrating

typical semiconductor applications. Complete Information sufficient for construction
purposes is not necessarily given.

The information contained in this document has been carefully checked and is
believed to be reliable. However, Fujitsu assumes no responsibility for inaccuracies.

The information contained in this document does not convey any license under the
copyrights, patent rights or trademarks claimed and owned by Fujitsu.

Fujitsu reserves the right to change products or specifications without notice.
No part of this publication may be copied or reproduced in any form or by any means,

or transferred to any third party without prior written consent of Fujitsu.

14

FUJITSU LIMITED

For further information, please contact:

Japan

FUJITSU LIMITED

Semiconductor Marketing
Furukawa Sogo Bldg.
6-1,Marunouchi 2-chome
Chiyoda-ku, Tokyo 100
Japan
Tel: [phone]
Telex: 781-2224361
FAX: [phone]

North and South America

FUJITSU MICROELECTRONICS, INC.

Semiconductor Division
3545 North First Street
San Jose, CA 95134-1804 USA
Tel: [phone]
FAX: [phone]

MB1502

Europe

FUJITSU MIKROELEKTRONIK GmbH

Arabella Centre 9.OG
Lyoner Strasse 44-48
D-6000 Frankfurt 71
F.R. Germany
Tel: [phone]
Telex: 41 1963
FAX: [phone]

Asia

FUJITSU MICROELECTRONICS ASIA PTE LIMITED
51 Bras Basah Road
Plaza by the Park
#06-04/07
Singapore 0718
Tel: [phone]
Telex: 55373
FAX: [phone]

 1990 FUJITSU LIMITED JV0123-90Y A3

Printed in Japan

15