Datasheet IC62LV256-100JI, IC62LV256-100N, IC62LV256-100T, IC62LV256-100TI, IC62LV256-100U Datasheet (ICSI)

IC62LV256

Document Title

32K x 8 Low Power SRAM with 3.3V

Revision History

Revision No History Draft Date Remark

0A Initial Draft October 5,2001

The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and
products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices.

Integrated Circuit Solution Inc. 1

ALSR007-0A 10/5/2001

IC62LV256

32K x 8 LOW VOLTAGE STATIC RAM

FEATURES

• Access time: 45, 70, 100 ns

• Low active power: 70 mW

• Low standby power
— 60 µW CMOS standby

• Fully static operation: no clock or refresh
required

• TTL compatible inputs and outputs

• Single 3.3V power supply

FUNCTIONAL BLOCK DIAGRAM

DESCRIPTION

The ICSI IC62LV256 is a low power, 32, 768-word by 8-bit
static RAM. It is fabricated using ICSI's high-performance
CMOS double-metal technology.

When CE is HIGH (deselected), the device assumes a standby
mode at which the power dissipation is reduced to
20 µW (typical) with CMOS input levels.

Easy memory expansion is provided by using an active LOW
Chip Enable (CE) input and an active LOW Output Enable (OE)
input. The active LOW Write Enable (WE) controls both writing
and reading of the memory.

The IC62LV256 is pin compatible with other 32K x 8 SRAMs
in 300mil DIP and SOJ, 330mil SOP, and 8*13.4mm TSOP-1
packages.

A0-A14

VCC
GND

I/O0-I/O7

CE
OE

WE

ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.

DECODER

I/O

DATA

CIRCUIT

CONTROL

CIRCUIT

256 X 1024

MEMORY ARRAY

COLUMN I/O

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IC62LV256

PIN CONFIGURATION

28-Pin DIP, SOJ and SOP

A14
A12

A7
A6
A5
A4
A3
A2
A1

A0
I/O0
I/O1
I/O2

GND

1
2
3
4
5
6
7
8
9
10
11
12
13
14

28
27
26
25
24
23
22
21
20
19
18
17
16
15

PIN DESCRIPTIONS

VCC
WE
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3

PIN CONFIGURATION

8x13.4mm TSOP-1

OE

A11

A9
A8

A13

WE

VCC

A14
A12

A7
A6
A5
A4
A3

22
23
24
25
26
27
28
1
2
3
4
5
6
7

TRUTH TABLE

21
20
19
18
17
16
15
14
13
12
11
10

A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0

9

A1

8

A2

A0-A14 Address Inputs

CE Chip Enable Input
OE Output Enable Input
WE Write Enable Input

I/O0-I/O7 Input/Output

Mode

WEWE

WE

WEWE

Not Selected X H X High-Z ISB1, ISB2
(Power-down)

Output Disabled H L H High-Z ICC1, ICC2
Read H L L DOUT ICC1, ICC2
Write L L X DIN ICC1, ICC2

CECE

OEOE

CE

OE I/O Operation Vcc Current

CECE

OEOE

Vcc Power
GND Ground

ABSOLUTE MAXIMUM RATINGS

(1)

Symbol Parameter Value Unit

VTERM Terminal Voltage with Respect to GND –0.5 to +4.6 V
TBIAS Temperature Under Bias –55 to +125 °C
TSTG Storage Temperature –65 to +150 °C
PT Power Dissipation 0.5 W
IOUT DC Output Current (LOW) 20 mA

Notes:

1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.

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IC62LV256

OPERATING RANGE

Range Ambient Temperature VCC

Commercial 0°C to +70°C 3.3V ± 5%
Industrial –40°C to +85°C 3.3V ± 5%

DC ELECTRICAL CHARACTERISTICS (Over Operating Range)

Symbol Parameter Test Conditions Min. Max. Unit

VOH Output HIGH Voltage VCC = Min., IOH = –1.0 mA 2.4 — V
VOL Output LOW Voltage VCC = Min., IOL = 2.1 mA — 0.4 V
VIH Input HIGH Voltage 2.2 VCC + 0.3 V
VIL Input LOW Voltage
I

LI Input Leakage GND ≤ VIN ≤ VCC Com. –2 2 µA

ILO Output Leakage GND ≤ VOUT ≤ VCC, Outputs Disabled Com. –2 2 µA

Notes:

1. VIL = –3.0V for pulse width less than 10 ns.

2. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.

(1)

–0.3 0.8 V

Ind. –5 5

Ind. –5 5

POWER SUPPLY CHARACTERISTICS

(1)

(Over Operating Range)

-45 ns -70 ns -100 ns

Symbol Parameter Test Conditions Min. Max. Min. Max. Min. Max. Unit

ICC1 Vcc Operating VCC = Max., CE = VIL Com. — 20 — 20 — 20 mA

Supply Current IOUT = 0 mA, f = 0 Ind. — 30 — 30 — 30

ICC2 Vcc Dynamic Operating VCC = Max., CE = VIL Com. — 35 — 30 — 30 mA

Supply Current IOUT = 0 mA, f = fMAX Ind. — 45 — 40 — 40

ISB1 TTL Standby Current VCC = Max., Com. — 2 — 2 — 2 mA

(TTL Inputs) VIN = VIH or VIL Ind. — 5 — 5 — 5

CE ≥ VIH, f = 0

ISB2 CMOS Standby VCC = Max., Com. — 90 — 90 — 90 µA

Current (CMOS Inputs) CE ≥ VCC – 0.2V, Ind. — 200 — 200 — 200

VIN ≥ VCC – 0.2V, or
VIN ≤ 0.2V, f = 0

Notes:

1. At f = f

CAPACITANCE

MAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.

(1,2)

Symbol Parameter Conditions Max. Unit

CIN Input Capacitance VIN = 0V 6 pF
COUT Output Capacitance VOUT = 0V 5 pF

Notes:

1. Tested initially and after any design or process changes that may affect these parameters.

2. Test conditions: T

A = 25°C, f = 1 MHz, Vcc =3.3V.

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IC62LV256

READ CYCLE SWITCHING CHARACTERISTICS

(1)

(Over Operating Range)

-45 ns -70 ns -100 ns

Symbol Parameter Min. Max. Min. Max. Min. Max. Unit

tRC Read Cycle Time 45 — 70 — 100 — ns
tAA Address Access Time — 45 — 70 — 100 ns
tOHA Output Hold Time 2 — 2 — 2 — ns
tACE CE Access Time — 45 — 70 — 100 ns
tDOE OE Access Time — 25 — 35 — 50 ns

(2)

tLZOE

(2)

tHZOE

(2)

tLZCE

(2)

tHZCE

(3)

tPU

(3)

tPD

Notes:

1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V
and output loading specified in Figure 1a.

2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.

3. Not 100% tested.

OE to Low-Z Output 0 — 0 — 0 — ns
OE to High-Z Output 0 20 0 25 0 25 ns
CE to Low-Z Output 3 — 3 — 3 — ns
CE to High-Z Output 0 20 0 25 0 25 ns
CE to Power-Up 0 — 0 — 0 — ns
CE to Power-Down — 30 — 50 — 50 ns

AC TEST CONDITIONS

Parameter Unit

Input Pulse Level 0V to 3.0V
Input Rise and Fall Times 5 ns
Input and Output Timing 1.5V

and Reference Levels
Output Load See Figures 1a and 1b

AC TEST LOADS

1213 Ω

3.3V

OUTPUT

100 pF

Including

jig and

scope

Figure 1a. Figure 1b.

1378 Ω

3.3V

OUTPUT

5 pF

Including

jig and

scope

1213 Ω

1378 Ω

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IC62LV256

AC WAVEFORMS

READ CYCLE NO. 1

ADDRESS

D

OUT

READ CYCLE NO. 2

ADDRESS

OE

(1,2)

(1,3)

t

RC

t

AA

t

OHA

DATA VALID

t

RC

t

AA

t

OHA

t

OHA

t

DOE

t

LZOE

D

CE

OUT

HIGH-Z

t

PU

t

LZCE

t

ACE

SUPPLY

CURRENT

Notes:

1. WE is HIGH for a Read Cycle.

2. The device is continuously selected. OE, CE = V

3. Address is valid prior to or coincident with CE LOW transitions.

IL.

t

HZCE

DATA VALID

t

HZOE

t

PD

HIGH-Z

ICC

50%50%

ISB

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IC62LV256

WRITE CYCLE SWITCHING CHARACTERISTICS

(1,2,3)

(Over Operating Range)

-45 ns -70 ns -100 ns

Symbol Parameter Min. Max. Min. Max. Min. Max. Unit

tWC Write Cycle Time 45 — 70 — 100 — ns
tSCE CE to Write End 35 — 60 — 80 — ns
tAW Address Setup Time to Write End 25 — 60 — 80 — ns
tHA Address Hold from Write End 0 — 0 — 0 — ns
tSA Address Setup Time 0 — 0 — 0 — ns

(4)

tPWE

WE Pulse Width 25 — 55 — 60 — n s

tSD Data Setup to Write End 20 — 30 — 35 — ns
tHD Data Hold from Write End 0 — 0 — 0 — ns

Notes:

1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V
and output loading specified in Figure 1a.

2. Tested with the load in Figure 1b. Transition is measured

3. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the Write.

4. Tested with OE HIGH.

±500 mV from steady-state voltage. Not 100% tested.

AC WAVEFORMS

WRITE CYCLE NO. 1 (

ADDRESS

CE

WE

D

OUT

D

IN

WEWE

WE Controlled)

WEWE

t

SA

DATA UNDEFINED

(1,2)

t

AW

t

HZWE

t

SCE

t

WC

t

PWE

HIGH-Z

t

SD

DATA-IN VALID

t

HA

t

LZWE

t

HD

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IC62LV256

WRITE CYCLE NO. 2 (

CECE

CE Controlled)

CECE

(1,2)

tWC

ADDRESS

tSA tHA

tSCE

CE

tAW

tPWE

WE

tHZWE

DOUT

D

IN

Notes:

1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the Write.

2. I/O will assume the High-Z state if OE

DATA UNDEFINED

≥ VIH.

HIGH-Z

tSD

DATA-IN VALID

tLZWE

tHD

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IC62LV256

ORDERING INFORMATION
Commercial Range: 0°C to +70°C

Speed (ns) Order Part No. Package

45 IC62LV256-45N 300mil DIP
45 IC62LV256-45J 300mil SOJ
45 IC62LV256-45T 8*13.4mm TSOP-1
45 IC62LV256-45U 330mil SOP

70 IC62LV256-70N 300mil DIP
70 IC62LV256-70J 300mil SOJ
70 IC62LV256-70T 8*13.4mm TSOP-1
70 IC62LV256-70U 330mil SOP

100 IC62LV256-100N 300mil DIP
100 IC62LV256-100J 300mil SOJ
100 IC62LV256-100T 8*13.4mm TSOP-1
100 IC62LV256-100U 330mil SOP

ORDERING INFORMATION
Industrial Range: –40°C to +85°C

Speed (ns) Order Part No. Package

45 IC62LV256-45JI 300mil SOJ
45 IC62LV256-45TI 8*13.4mm TSOP-1
45 IC62LV256-45UI 330mil SOP

70 IC62LV256-70JI 300mil SOJ
70 IC62LV256-70TI 8*13.4mm TSOP-1
70 IC62LV256-70UI 330mil SOP

100 IC62LV256-100JI 300mil SOJ
100 IC62LV256-100TI 8*13.4mm TSOP-1
100 IC62LV256-100UI 330mil SOP

Integrated Circuit Solution Inc.

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Integrated Circuit Solution Inc. 9

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