Datasheet IC62LV12816DLL-55TI, IC62LV12816DLL-70B, IC62LV12816DLL-70BI, IC62LV12816DLL-70T, IC62LV12816DLL-70TI Datasheet (ICSI)

Integrated Circuit Solution Inc. 1

LPSR025-0A 6/7/2002

IC62LV12816DL
IC62LV12816DLL

Document Title

128 K x 16 bit Low Voltage and Ultra Low Power CMOS Static RAM

Revision History

Revision No History Draft Date Remark

0A Initial Draft June 7,2002 Preliminary

The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and
products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices.

2 Integrated Circuit Solution Inc.

LPSR025-0A 6/7/2002

IC62LV12816DL
IC62LV12816DLL

ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.

DESCRIPTION

The ICSI IC62LV12816DL and IC62LV12816DLL are low­power,2,097,152 bit static RAMs organized as 131,072 words
by 16 bits. They are fabricated using ICSI's high-performance
CMOS technology. This highly reliable process coupled with
innovative circuit design techniques, yields high-performance
and low power consumption devices.

When CE1 is HIGH or when CE2 is low (deselected) or both LB
and UB are HIGH, the device assumes a standby mode at
which the power dissipation can be reduced by using CMOS
input levels.

Easy memory expansion is provided by using Chip Enable
Output and Enable inputs, CE1, CE2 and OE. The active LOW
Write Enable (WE) controls both writing and reading of the
memory. A data byte allows Upper Byte (UB) and Lower Byte
(LB) access.

The IC62LV12816DL and IC62LV12816DLL are packaged in
the JEDEC standare 44-pin TSOP-2 and 48-pin 6*8mm TF­BGA.

FUNCTIONAL BLOCK DIAGRAM

128K x 16 LOW VOLTAGE, ULTRA
LOW POWER CMOS STATIC RAM

FEATURES

• High-speed access times: 55, 70, 100 ns

• CMOS low power operation

--60mW (typical)* operating

--3

µW (typical)* CMOS standby

• TTL compatible interface levels

• Single 2.7V-3.6V Vcc power supply

• Fully static operation: no clock or refresh re­quired

• Three state outputs

• Data control for upper and lower bytes

• Industrial temperature available

• Available in the 44-pin TSOP-2 and 48-pin
6x8mm TF-BGA

• CE2 pin only for 48-pin TF-BGA.

* Typical values are measured at VCC=3.0V, TA=25°C

A0-A16

CE1, CE2

OE
WE

128K x 16

MEMORY ARRAY

DECODER

COLUMN I/O

CONTROL

CIRCUIT

GND

VCC

I/O

DATA

CIRCUIT

I/O0-I/O7

Lower Byte

I/O8-I/O15

Upper Byte

UB

LB

Preliminary

Integrated Circuit Solution Inc. 3

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IC62LV12816DL
IC62LV12816DLL

TRUTH TABLE

I/O PIN

Mode

WEWE

WEWE

WE

CE1CE1

CE1CE1

CE1

CE2CE2

CE2CE2

CE2

OEOE

OEOE

OE

LBLB

LBLB

LB

UBUB

UBUB

UB I/O0/-I/O7 I/O8-I/O15 Vcc Current

Not Selected X H X X X X High-Z High-Z Standby

X X L X X X High-Z High-Z Standby
X L H X H H High-Z High-Z Standby

Output Disabled H L H H L X High-Z High-Z Active

H L H H X L High-Z High-Z Active

Read H L H L L H DOUT High-Z Active

H L H L H L High-Z DOUT Active
HLHLL L DOUT DOUT Active

Write L L H X L H DIN High-Z Active

L L H X H L High-Z DIN Active
LLHXL L DIN DIN Active

PIN DESCRIPTIONS

A0-A16 Address Inputs
I/O0-I/O15 Data Input/Output
CE1 Chip Enable1 Input
CE2 Chip Enable2 Input, BGA only

OE Output Enable Input
WE Write Enable Input

LB Lower-byte Control (l/O0-I/O7)
UB Upper-byte Control (l/O8-I/O15)

NC No Connection
Vcc Power
GND Ground

48-Pin TF-BGA (TOP View)

PIN CONFIGURATIONS

44-Pin TSOP-2

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23

A4
A3
A2
A1

A0
CE1
I/O0
I/O1
I/O2
I/O3

Vcc

GND

I/O4
I/O5
I/O6
I/O7

WE
A16
A15
A14
A13
A12

A5
A6
A7
OE
UB
LB
I/O15
I/O14
I/O13
I/O12
GND
Vcc
I/O11
I/O10
I/O9
I/O8
NC
A8
A9
A10
A11
NC

1 2 3 4 5 6

A
B
C
D
E
F
G
H

LB

OE

A0

A1

A2

CE2

I/O

8

UB A3

A4

CE1 I/O

0

I/O

9

I/O10A5

A6

I/O1I/O

2

GND

I/O

11

NC

A7

I/O

3

Vcc

Vcc

I/O12NC

A16

I/O

4

GND

I/O

14

I/O

13

A14

A15

I/O

5

I/O

6

I/O

15

NC

A12

A13

WE

I/O

7

NC

A8

A9

A10

A11 NC

4 Integrated Circuit Solution Inc.

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IC62LV12816DLL

ABSOLUTE MAXIMUM RATINGS

(1)

Symbol Parameter Value Unit

VTERM Terminal Voltage with Respect to GND –0.5 to Vcc + 0.5 V
TBIAS Temperature Under Bias –40 to +85 °C
VCC Vcc related to GND –0.3 to +4.0 V
TSTG Storage Temperature –65 to +150 °C
PT Power Dissipation 1.0 W

Notes:

1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.

CAPACITANCE

(1)

Symbol Parameter Conditions Max. Unit

CIN Input Capacitance VIN = 0V 6 pF
COUT Output Capacitance VOUT = 0V 8 pF

Notes:

1. Tested initially and after any design or process changes that may affect these parameters.

DC ELECTRICAL CHARACTERISTICS (Over Operating Range)

Symbol Parameter Test Conditions Min. Max. Unit

VOH Output HIGH Voltage IOH = –1 mA 2.0 — V

VOL Output LOW Voltage IOL = 2.1 mA — 0.4 V

VIH

(1)

Input HIGH Voltage 2.2 VCC + 0.2 V

VIL

(2)

Input LOW Voltage

(1)

–0.2 0.4 V
ILI Input Leakage GND ≤ VIN ≤ VCC –1 1 µA
ILO Output Leakage GND ≤ VOUT ≤ VCC, OUTPUTS DISABLED –1 1 µA

Notes:

1. VIH(max.) = Vcc + 0.2V for pulse width less than 10ns.

2. V

IL(min.) = –2.0V for pulse width less than 10 ns.

OPERATING RANGE

Range Ambient Temperature VCC

Commercial 0°C to +70°C 2.7V- 3.6V
Industrial –40°C to +85°C 2.7V - 3.6V

Integrated Circuit Solution Inc. 5

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IC62LV12816DLL

IC62LV12816DL POWER SUPPLY CHARACTERISTICS

(1)

(Over Operating Range)

-55 -70 -100

Symbol Parameter Test Conditions Min. Max. Min. Max. Min. Max. Unit

ICC Vcc Dynamic Operating VCC = 3.0V., Com. — 40 — 30 — 20 mA

Supply Current I OUT = 0 mA, f = fMAX Ind. — 45 — 35 — 25

ISB1 TTL Standby Current VCC = Max., Com. — 0.5 — 0.5 — 0.5 mA

(TTL Inputs) VIN = VIH or VIL, f = 0 Ind. — 1.0 — 1.0 — 1.0

CE1 = VIH, CE2 = VIL

ISB2 CMOS Standby VCC = Max., Com. — 35 — 35 — 35 µA

Current (CMOS Inputs) CE1 ≥ VCC – 0.2V, Ind. — 50 — 50 — 50

or CE2 ≤ 0.2V
other input = 0-VCC, f = 0

OR
ULB Control VCC = Max., CE1 = VIL, CE2 = VIH

VIN ≤ 0.2V, f = 0, UB / LB = VCC – 0.2V

Note:

1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.

AC TEST CONDITIONS

Parameter Unit

Input Pulse Level 0.4V to 2.2V
Input Rise and Fall Times 5 ns
Input and Output Timing 1.3V

and Reference Level
Output Load See Figures 1 and 2

AC TEST LOADS

Figure 1 Figure 2

5 pF

Including

jig and

scope

OUTPUT

1 TTL

100 pF

Including

jig and

scope

OUTPUT

1 TTL

6 Integrated Circuit Solution Inc.

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IC62LV12816DL
IC62LV12816DLL

READ CYCLE SWITCHING CHARACTERISTICS

(1)

(Over Operating Range)

-55 -70 -100

Symbol Parameter Min. Max. Min. Max. Min. Max. Unit

tRC Read Cycle Time 55 — 70 — 100 — ns
tAA Address Access Time — 55 — 70 — 100 ns
tOHA Output Hold Time 10 — 10 — 15 — ns
tACE CE Access Time — 55 — 70 — 100 ns
tDOE OE Access Time — 30 — 35 — 50 ns
tHZOE

(2)

OE to High-Z Output — 20 — 25 — 30 ns

tLZOE

(2)

OE to Low-Z Output 5 — 5 — 5 — ns

tHZCE

(2)

CE to High-Z Output 0 20 0 25 0 30 ns

tLZCE

(2)

CE to Low-Z Output 10 — 10 — 10 — ns

tBA LB, UB Access Time — 55 — 70 — 100 ns
tHZB LB, UB o High-Z Output 0 25 0 25 0 35 ns
tLZB LB. UB to Low-Z Output 0 — 0 — 0 — ns

Notes:

1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels
of 0.4V to 2.2V and output loading specified in Figure 1.

2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.

IC62LV12816DLL POWER SUPPLY CHARACTERISTICS

(1)

(Over Operating Range)

-55 -70 -100

Symbol Parameter Test Conditions Min. Max. Min. Max. Min. Max. Unit

ICC Vcc Dynamic Operating VCC = Max Com. — 40 — 30 — 20 mA

Supply Current I OUT = 0 mA, f = fMAX Ind. — 45 — 35 — 25

ISB1 TTL Standby Current VCC = Max., Com. — 0.5 — 0.5 — 0.5 mA

(TTL Inputs) VIN = VIH or VIL, Ind. — 1.0 — 1.0 — 1.0

CE1 = VIH, CE2 = VIL

ISB2 CMOS Standby VCC = Max., f = 0 Com . — 10 — 10 — 10 µA

Current (CMOS Inputs) CE1 ≥ VCC – 0.2V, Ind. — 15 — 15 — 15

or CE2 ≤ 0.2V
other input = 0-VCC, f = 0

OR

ULB Control VCC = Max., CE1 = VIL, CE2 = VIH

VIN ≤ 0.2V, f = 0, UB / LB = VCC – 0.2V

Note:

1. At f = f

MAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.

Integrated Circuit Solution Inc. 7

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IC62LV12816DL
IC62LV12816DLL

t

RC

t

OHA

t

AA

t

DOE

t

LZOE

t

ACE

t

LZCE

t

HZOE

HIGH-Z

DATA VALID

t

HZB

ADDRESS

OE

CE1

LB, UB

D

OUT

CE2

t

HZCE

t

BA

t

LZB

Notes:

1. WE is HIGH for a Read Cycle.

2. The device is continuously selected. OE, CE1, UB, or LB = V

IL, CE2 = VIH

3. Address is valid prior to or coincident with CE1 LOW and CE2 HIGH transitions.

AC WAVEFORMS
READ CYCLE NO. 2

(1,3)

(OE, Controlled)

AC TEST LOADS

READ CYCLE NO.1

(1,2)

(Address Controlled) (CE1 = OE = VIL, CE2 = VIH, UB or LB = VIL)

DATA VALID

PREVIOUS DATA VALID

t

AA

t

OHA

t

OHA

t

RC

D

OUT

ADDRESS

8 Integrated Circuit Solution Inc.

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IC62LV12816DL
IC62LV12816DLL

WRITE CYCLE SWITCHING CHARACTERISTICS

(1,2)

(Over Operating Range)

-55 -70 -100

Symbol Parameter Min. Max. Min. Max. Min. Max Unit

tWC Write Cycle Time 55 — 70 — 100 — ns
tSCE CE1 Low and CE2 HIGH to Write End 50 — 65 — 80 — ns
tAW Address Setup Time to Write End 50 — 65 — 80 — ns
tHA Address Hold from Write End 0 — 0 — 0 — ns
tSA Address Setup Time 0 — 0 — 0 — ns
tPWB LB, UB Valid to End of Write 45 — 60 — 80 — ns
tPWE WE Pulse Width 45 — 40 — 80 — ns
tSD Data Setup to Write End 25 — 30 — 40 — ns
tHD Data Hold from Write End 0 — 0 — 0 — ns
tHZWE

(3)

WE LOW to High-Z Output — 30 — 30 — 40 n s

tLZWE

(3)

WE HIGH to Low-Z Output 5 — 5 — 5 — ns

Notes:

1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.3V, input pulse levels of 0.4V to 2.2V
and output loading specified in Figure 1.

2. The internal write time is defined by the overlap of CE1 LOW, and UB or LB, WE LOW, and CE2 HIGH. All signals must be in
valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are
referenced to the rising or falling edge of the signal that terminates the Write.

3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.

DATA UNDEFINED

t

WC

VALID ADDRESS

t

SCE

t

PWE

t

AW

t

HA

HIGH-Z

t

PBW

t

HD

t

SA

t

HZWE

ADDRESS

CE1

UB, LB

WE

D

OUT

D

IN

CE2

DATAIN VALID

t

LZWE

t

SD

AC WAVEFORMS
WRITE CYCLE NO. 1

(1,2)

(CE1 or CE2, Controlled, OE = HIGH or LOW)

Notes:

1. WRITE is an internally generated signal asserted during an overlap of the WE, CE1 = VIL, CE2 = VIH and at least one of the LB
and UB inputs being in the LOW state.

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IC62LV12816DL
IC62LV12816DLL

WRITE CYCLE NO. 2 (WE Controlled; OE is HIGH During Write Cycle)

DATA UNDEFINED

t WC

VALID ADDRESS

t PWE

t AW

t SCE

t HA

HIGH-Z

t PBW

t HD

t SA

t HZWE

ADDRESS

CE1

UB, LB

WE

D

OUT

DIN

CE2

OE

DATAIN VALID

t LZWE

t SD

WRITE CYCLE NO. 3 (WE Controlled; OE is LOW During Write Cycle)

DATA UNDEFINED

t

SCE

VALID ADDRESS

LOW

t

PWE

t

AW

t

HA

HIGH-Z

t

PBW

t

HD

t

SA

t

HZWE

ADDRESS

CE1

UB, LB

WE

D

OUT

DIN

CE2

OE

DATAIN VALID

t

LZWE

t

SD

t

WC

10 Integrated Circuit Solution Inc.

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IC62LV12816DL
IC62LV12816DLL

DATA RETENTION SWITCHING CHARACTERISTICS

Symbol Parameter Test Condition Min. Max. Unit

VDR Vcc for Data Retention See Data Retention Waveform 1.5 3.6 V

IDR Data Retention Current VCC = 1.5V, CE1 ≥ VCC – 0.2V

(1)

Com. (-L) — 20 µA

Com. (-LL) — 5

Ind. (-L) — 25

Ind. (-LL) — 8

tSDR Data Retention Setup Time See Data Retention Waveform 0 — ns
tRDR Recovery Time See Data Retention Waveform t

RC

—ns

WRITE CYCLE NO. 4 (UB / LB Controlled)

DATA UNDEFINED

t

WC

ADDRESS 1 ADDRESS 2

t

WC

HIGH-Z

t

PBW

WORD 1

WORD 2

t

HD

t

SA

t

HZWE

ADDRESS

CE1

UB, LB

WE

D

OUT

D

IN

CE2

OE

DATA

IN

VALID

t

LZWE

t

SD

t

PBW

DATA

IN

VALID

t

SD

t

HD

t

SA

t

HA

t

HA

Notes:

1.1)CE1

≥ VCC -0.2V, CE2 ≥ VCC -0.2V, (CE1 controlled) or

2) 0V

≤ CE2 ≤ 0.2V (CE2 controlled) or

3)LB = UB

≥ VCC -0.2V, CE2 ≥ VCC -0.2V (LB/UB controlled)

Integrated Circuit Solution Inc. 11

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IC62LV12816DL
IC62LV12816DLL

DATA RETENTION WAVEFORM (CE1 Controlled)

V

CC

CE1 ≥ V

CC

- 0.2V

t

SDR

t

RDR

V

DR

CE1

GND

2.7V

2.2V

Data Retention Mode

12 Integrated Circuit Solution Inc.

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IC62LV12816DL
IC62LV12816DLL

ORDERING INFORMATION
Commercial Range: 0°C to +70°C

Speed (ns) Order Part No. Package

55 IC62LV12816DL-55T TSOP-2

IC62LV12816DL-55B 6*8mm TF-BGA

70 IC62LV12816DL-70T TSOP-2

IC62LV12816DL-70B 6*8mm TF-BGA

100 IC62LV12816DL-100T TSOP-2

IC62LV12816DL-100B 6*8mm TF-BGA

Industrial Range: -40°C to +85°C

Speed (ns) Order Part No. Package

55 IC62LV12816DL-55TI TSOP-2

IC62LV12816DL-55BI 6*8mm TF-BGA

70 IC62LV12816DL-70TI TSOP-2

IC62LV12816DL-70BI 6*8mm TF-BGA

100 IC62LV12816DL-100TI TSOP-2

IC62LV12816DL-100BI 6*8mm TF-BGA

ORDERING INFORMATION
Commercial Range: 0°C to +70°C

Speed (ns) Order Part No. Package

55 IC62LV12816DLL-55T TSOP-2

IC62LV12816DLL-55B 6*8mm TF-BGA

70 IC62LV12816DLL-70T TSOP-2

IC62LV12816DLL-70B 6*8mm TF-BGA

100 IC62LV12816DLL-100T TSOP-2

IC62LV12816DLL-100B 6*8mm TF-BGA

Industrial Range: -40°C to +85°C

Speed (ns) Order Part No. Package

55 IC62LV12816DLL-55TI TSOP-2

IC62LV12816DLL-55BI 6*8mm TF-BGA

70 IC62LV12816DLL-70TI TSOP-2

IC62LV12816DLL-70BI 6*8mm TF-BGA

100 IC62LV12816DLL-100TI TSOP-2

IC62LV12816DLL-100BI 6*8mm TF-BGA

Integrated Circuit Solution Inc.

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