Datasheet IC62LV1008L-100B, IC62LV1008L-100BI, IC62LV1008L-55B, IC62LV1008L-55BI, IC62LV1008L-70B Datasheet (ICSI)

IC62LV1008L
IC62LV1008LL

Document Title

1 M x 8 bit Low Voltage and Ultra Low Power CMOS Static RAM

Revision History

Revision No History Draft Date Remark

0A Initial Draft January 3,2002 Preliminary

The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and
products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices.

Integrated Circuit Solution Inc. 1

LPSR015-0A 1/3/2002

IC62LV1008L
IC62LV1008LL

1M x 8 LOW POWER and LOW VCC
CMOS STATIC RAM

FEATURES

• Access times of 55, 70, 100 ns

• CMOS Low power operation:
I

CC=15mA (typical)* operation

ISB2=2µA (typical)* standby

• Low data retention voltage: 1.5V (min.)

• Output Enable (OE) and Two Chip Enables
(CE1, CE2) inputs for ease in applications

• TTL compatible inputs and outputs

• Fully static operation:

— No clock or refresh reguired

• Single 2.7V-3.6V power supply

• Wafer level burn in test mode

• Available in the know good die form and
48-pin 8*10mm TF-BGA

* Typical values are measured at VCC=3.0V, TA=25°C

DESCRIPTION

The ICSI IC62LV1008L and IC62LV1008LL is a low voltage,
1,048,576 words by 8 bits, CMOS SRAM. It is fabricated using

ICSI's low voltage, six transistor (6T), CMOS technology. The

device is targeted to satisfy the demands of the state-of-the-art
technologies such as cell phones and pagers.

When

CE1 is HIGH or CE2 is LOW (deselected), the device

assumes a standby mode at which the power dissipation can
be reduced down with CMOS input levels. Additionally, easy
memory expansion is provided by using two Chip Enable
inputs, CE1 and CE2. The active LOW Write Enable ( WE)
controls both writing and reading of the memory.

The IC62LV1008L and IC62LV1008LL are available in know
good die form and 48-pin 8*10mm TF-BGA.

Preliminary

FUNCTIONAL BLOCK DIAGRAM

A0-A19

VCC

GND

I/O0-I/O7

CE1
CE2

OE
WE

ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.

DECODER

I/O

DATA

CIRCUIT

CONTROL

CIRCUIT

1024K x 8

MEMORY ARRAY

COLUMN I/O

2 Integrated Circuit Solution Inc.

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IC62LV1008L
IC62LV1008LL

PIN CONFIGURATIONS

48-Pin 8*10mm TF-BGA (TOP View)

1 2 3 4 5 6

A1

OE

A0

A

NC

A2

CE2

A5

A17

Vcc

A14

A12

A9

A4

A6

A7

A16

A15

A13

A10

CE1 NC

NC

I/O

I/O

NC

WE

A11 A19

NC A3

B
C
D
E
F
G
H

NC

I/O

GND

Vcc

I/O

NC

A18

NC

0

I/O

1

I/O

2

NC

3

NC

A8

PIN DESCRIPTIONS

A0-A19 Address Inputs
CE1 Chip Enable 1 Input
CE2 Chip Enable 2 Input

OE Output Enable Input
WE Write Enable Input

I/O0-I/O7 Data Input/Output
NC No Connection

I/O

4

Vcc

5

GND

6

I/O

7

NC

Vcc Power
GND Ground

TRUTH TABLE

Mode

WEWE

WE

WEWE

Not Selected X H X X High-Z ISB1, ISB2
(POWER-DOWN) X X L X High-Z ISB1, ISB2

Output Disabled H L H H High-Z ICC
Read H L H L DOUT ICC
Write L L H X DIN ICC

CE1CE1

CE1 CE2

CE1CE1

OEOE

OE I/O Operation Vcc Current

OEOE

OPERATING RANGE

Range Ambient Temperature VCC

Commercial 0°C to +70°C 2.7V - 3.6V
Industrial –40°C to +85°C 2.7V - 3.6V

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IC62LV1008L
IC62LV1008LL

ABSOLUTE MAXIMUM RATINGS

(1)

Symbol Parameter Value Unit

VTERM Terminal Voltage with Respect to GND –0.5 to Vcc + 0.5 V
VCC Vcc related to GND –0.3 to +4.0 V
TBIAS Temperature Under Bias –40 to +85 °C
TSTG Storage Temperature –65 to +150 °C
PT Power Dissipation 1 W

Notes:

1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.

CAPACITANCE

(1)(2)

Symbol Parameter Conditions Max. Unit

CIN Input Capacitance VIN = 0V 6 pF
COUT Output Capacitance VOUT = 0V 8 pF

Notes:

1. Tested initially and after any design or process changes that may affect these parameters.

2. Test conditions: T

o

A = 25

C, f = 1 MHz, VCC = 3.0 V

DC ELECTRICAL CHARACTERISTICS (Over Operating Range)

Symbol Parameter Test Conditions Min. Max. Unit

VOH Output HIGH Voltage VCC = Min., IOH = –1.0 mA 2.0 — V
VOL Output LOW Voltage VCC = Min., IOL = 2.1 mA — 0.4 V
VIH Input HIGH Voltage
VIL Input LOW Voltage
ILI Input Leakage GND ≤ VIN ≤ VCC –1 1 µA
ILO Output Leakage GND ≤ VOUT ≤ VCC –1 1 µA

Notes:

IH(max.) = VCC +2.0V for pulse width less than 10 ns.

1. V

1. VIL(min.) = –2.0V for pulse width less than 10 ns.

(1)

(2)

2.2 VCC + 0.3 V

–0.2 0.4 V

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IC62LV1008LL

IC62LV1008L POWER SUPPLY CHARACTERISTICS

(1)

(Over Operating Range)

-55 -70 -100

Symbol Parameter Test Conditions Min. Max. Min. Max. Min. Max. Unit

CC Vcc Dynamic Operating VCC = 3.0V, CE1 = VIL,CE2=VIH Com. — 30 — 25 — 20 mA

I

Supply Current IOUT = 0 mA, f = fMAX Ind. — 35 — 30 — 25

I

SB1 TTL Standby Current VCC = Max., f = 0 Com. — 0.2 — 0.2 — 0.2 mA

(TTL Inputs) CE1 ≥ VIH or CE2 ≤ VIL, Ind. — 0.3 — 0.3 — 0.3

VIN = VIH or VIL,

ISB2 CMOS Standby VCC = Max., f = 0 Com. — 35 — 35 — 35 µA

Current (CMOS Inputs) CE1 ≥ VCC – 0.2V Ind. — 50 — 50 — 50

or CE2 ≤ 0.2V,
VIN ≥ VCC – 0.2V, VIN ≤ 0.2V

Note:

1. At f = f

IC62LV1008LL POWER SUPPLY CHARACTERISTICS

MAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.

(1)

(Over Operating Range)

-55 -70 -100

Symbol Parameter Test Conditions Min. Max. Min. Max. Min. Max. Unit

ICC Vcc Dynamic Operating VCC = 3.0V, CE1 = VIL,CE2=VIH Com. — 30 — 25 — 20 mA

Supply Current IOUT = 0 mA, f = fMAX Ind. — 35 — 30 — 25

ISB1 TTL Standby Current VCC = Max., f = 0 Com. — 0.2 — 0.2 — 0.2 mA

(TTL Inputs) CE1 ≥ VIH or CE2 ≤ VIL, Ind. — 0.3 — 0.3 — 0.3

VIN = VIH or VIL,

ISB2 CMOS Standby VCC = Max., f = 0 Com. — 20 — 20 — 20 µA

Current (CMOS Inputs) CE1 ≥ VCC – 0.2V Ind. — 25 — 25 — 25

or CE2 ≤ 0.2V,
VIN ≥ VCC – 0.2V, VIN ≤ 0.2V

Note:

1. At f = f

MAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.

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IC62LV1008LL

READ CYCLE SWITCHING CHARACTERISTICS

(1)

(Over Operating Range)

-55 -70 -100

Symbol Parameter Min. Max. Min. Max. Min. Max. Unit

tRC Read Cycle Time 55 — 70 — 100 — ns
tAA Address Access Time — 55 — 70 — 100 ns
tOHA Output Hold Time 10 — 10 — 15 — n s
tACE1 CE1 Access Time — 55 — 70 — 100 ns
tACE2 CE2 Access Time — 55 — 70 — 100 ns
tDOE OE Access Time — 30 — 35 — 50 ns

(2)

tLZOE
tHZOE
tLZCE1
tLZCE2
tHZCE

Notes:

1. Test conditions assume signal transition times of 5 ns or less, input pulse levels of 0.4V to 2.2V and output
loading specified in Figure 1.

2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.

OE to Low-Z Output 5 — 5 — 5 — ns

(2)

OE to High-Z Output — 20 0 25 0 30 ns

(2)

CE1 to Low-Z Output 10 — 10 — 10 — ns

(2)

CE2 to Low-Z Output 10 — 10 — 10 — ns

(2)

CE1 or CE2 to Low-Z Output 0 20 0 25 0 30 ns

AC TEST CONDITIONS

Parameter Unit

Input Pulse Level 0.4V to 2.2V
Input Rise and Fall Times 5 ns
Input Reference Level 1.3V

Output Reference Level 1.5V
Output Load See Figures 1 and 2

AC TEST LOADS

1 TTL

OUTPUT

100 pF

Including

jig and

scope

1 TTL

OUTPUT

5 pF

Including

jig and

scope

Figure 1 Figure 2

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IC62LV1008L
IC62LV1008LL

AC TEST LOADS
READ CYCLE NO.1

ADDRESS

(1,2)

(Address controlled, CE1 =

t

OHA

OE OE

OE = VIL , CE2 = VIH)

OE OE

t

RC

t

AA

t

OHA

D

OUT

AC WAVEFORMS
READ CYCLE NO. 2

ADDRESS

OE

CE1

CE2

DOUT

PREVIOUS DATA VALID

(1,3)

(CE1,

OEOE

OE, CE2 controlled)

OEOE

t

ACE1/tACE2

t

LZCE1/

t

LZCE2

HIGH-Z

DATA VALID

t

RC

t

AA

t

LZOE

t

DOE

t

DATA VALID

t

HZOE

HZCE

t

OHA

Notes:

1. WE is HIGH for a Read Cycle.

2. The device is continuously selected. OE, CE1 = V

IL, CE2 = VIH.

3. Address is valid prior to or coincident with CE1 LOW and CE2 HIGH transitions.

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IC62LV1008L
IC62LV1008LL

WRITE CYCLE SWITCHING CHARACTERISTICS

(1,2)

(Over Operating Range, Standard and Low Power)

-55 -70 -100

Symbol Parameter Min. Max. Min. Max. Min. Max Unit

tWC Write Cycle Time 55 — 70 — 100 — ns
tSCE1 CE1 to Write End 50 — 65 — 80 — ns
tSCE2 CE2 to Write End 50 — 65 — 80 — ns
tAW Address Setup Time to Write End 50 — 65 — 80 — ns
tHA Address Hold from Write End 0 — 0 — 0 — ns
tSA Address Setup Time 0 — 0 — 0 — ns

(4)

tPWE

WE Pulse Width 45 — 55 — 80 — ns

tSD Data Setup to Write End 25 — 30 — 40 — ns
tHD Data Hold from Write End 0 — 0 — 0 — ns

(3)

tHZWE
tLZWE

Notes:

1. Test conditions assume signal transition times of 5 ns or less, input pulse levels of 0.4V to 2.2V and output loading specified in
Figure 1.

2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.

3. The internal write time is defined by the overlap of CE1 LOW , CE2 HIGH and WE LOW. All signals must be in valid states to
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the Write.

4. Tested with OE HIGH.

WE LOW to High-Z Output — 30 — 30 — 40 ns

(3)

WE HIGH to Low-Z Output 5 — 5 — 5 — ns

AC WAVEFORMS
WRITE CYCLE NO. 1

ADDRESS

CE1

CE2

WE

DOUT

DIN

(WE Controlled)

t

SA

DATA UNDEFINED

(1,2)

t

AW

t

HZWE

t

SCE1

t

SCE2

t

WC

t

PWE

HIGH-Z

t

SD

DATA-IN VALID

t

HA

t

LZWE

t

HD

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IC62LV1008L
IC62LV1008LL

WRITE CYCLE NO. 2 (CE1, CE2 Controlled)

ADDRESS

t

SA

CE1

CE2

WE

t

HZWE

DOUT

DIN

DATA UNDEFINED

t

AW

(1,2)

t

t

SCE1

t

SCE2

PWE

t

WC

HIGH-Z

t

SD

DATA-IN VALID

t

HA

t

LZWE

t

HD

Notes:

1. The internal write time is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states to
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the Write.

2. I/O will assume the HIGH-z state if OE =V

IH.

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IC62LV1008LL

DATA RETENTION SWITCHING CHARACTERISTICS

Symbol Parameter Test Condition Min. Max. Unit

VDR Vcc for Data Retention See Data Retention Waveform 1.5 3.6 V

I

DR Data Retention Current Vcc = 1.5V, CE1

tSDR Data Retention Setup Time See Data Retention Waveform 0 — ns
tRDR Recovery Time See Data Retention Waveform 10 —ns

DATA RETENTION WAVEFORM (CE1 Controlled)

≥

Vcc – 0.2V Com. (-L) — 15 µA

Com. (-LL) — 6 µA
Ind. (-L) — 20 µA
Ind. (-LL) — 9 µA

3.0V

2.2V

GND

V

CC

V

DR

CE1

SDR

t

Data Retention Mode

CE1 ≥ V

CC

- 0.2V

t

RDR

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IC62LV1008L
IC62LV1008LL

ORDERING INFORMATION
Commercial Range: 0°C to +70°C

Industrial Range: -40°C to +85°C

Speed (ns) Order Part No. Package

55 IC62LV1008L-55B 8*10mm TF-BGA
70 IC62LV1008L-70B 8*10mm TF-BGA

100 IC62LV1008L-100B 8*10mm TF-BGA

ORDERING INFORMATION
Commercial Range: 0°C to +70°C

Speed (ns) Order Part No. Package

55 IC62LV1008LL-55B 8*10mm TF-BGA

IC62LV1008LL-55D know good die

70 IC62LV1008LL-70B 8*10mm TF-BGA

IC62LV1008LL-70D know good die

100 IC62LV1008LL-100B 8*10mm TF-BGA

IC62LV1008LL-100D know good die

Speed (ns) Order Part No. Package

55 IC62LV1008L-55BI 8*10mm TF-BGA
70 IC62LV1008L-70BI 8*10mm TF-BGA

100 IC62LV1008L-100BI 8*10mm TF-BGA

Industrial Range: -40°C to +85°C

Speed (ns) Order Part No. Package

55 IC62LV1008LL-55BI 8*10mm TF-BGA

IC62LV1008LL-55DI know good die

70 IC62LV1008LL-70BI 8*10mm TF-BGA

IC62LV1008LL-70DI know good die

100 IC62LV1008LL-100BI 8*10mm TF-BGA

IC62LV1008LL-100DI know good die

Integrated Circuit Solution Inc.

HEADQUARTER:

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HSIN-CHU, TAIWAN, R.O.C.

TEL: [phone]

Fax: [phone]

BRANCH OFFICE:

7F, NO. 106, SEC. 1, HSIN-TAI 5TH ROAD,

HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C.

TEL: [phone]

FAX: [phone]

http://www.icsi.com.tw

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