Datasheet IC61LV6416-10B, IC61LV6416-10BI, IC61LV6416-8T, IC61LV6416-8TI, IC61LV6416-10K Datasheet (ICSI)

IC61LV6416

Document Title

64K x 16 Hight Speed SRAM with 3.3V

Revision History

Revision No History Draft Date Remark

0A Initial Draft September 12,2001

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The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and
products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices.

Integrated Circuit Solution Inc. 1

AHSR026-0A 09/12/2001

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IC61LV6416

64K x 16 HIGH-SPEED CMOS STATIC RAM
WITH 3.3V SUPPLY

FEATURES

• High-speed access time: 8, 10, 12, and 15 ns

• CMOS low power operation
— 250 mW (typical) operating
— 250 µW (typical) standby

• TTL compatible interface levels

• Single 3.3V power supply

• Fully static operation: no clock or refresh
required

• Three state outputs

• Data control for upper and lower bytes

• Industrial temperature available

FUNCTIONAL BLOCK DIAGRAM

DESCRIPTION

The ICSI IC61LV6416 is a high-speed, 1,048,576-bit static
RAM organized as 65,536 words by 16 bits. It is fabricated
using ICSI's high-performance CMOS technology. This highly
reliable process coupled with innovative circuit design
techniques, yields access times as fast as 8 ns with low power
consumption.

When CE is HIGH (deselected), the device assumes a standby
mode at which the power dissipation can be reduced down with
CMOS input levels.

Easy memory expansion is provided by using Chip Enable and
Output Enable inputs, CE and OE. The active LOW Write
Enable (WE) controls both writing and reading of the memory.
A data byte allows Upper Byte (UB) and Lower Byte (LB)
access.

The IC61LV6416 is packaged in the JEDEC standard 44-pin
400mil SOJ, 44-pin 400mil TSOP-2, and 48-pin 6*8mm TF­BGA.

A0-A15

VCC
GND

I/O0-I/O7

Lower Byte

I/O8-I/O15

Upper Byte

CE
OE

WE

UB

LB

ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.

DECODER

I/O

DATA

CIRCUIT

CONTROL

CIRCUIT

64K x 16

MEMORY ARRAY

COLUMN I/O

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AHSR026-0A 09/12/2001

IC61LV6416

PIN CONFIGURATIONS

44-Pin SOJ

A15
A14
A13
A12
A11

CE
I/O0
I/O1
I/O2
I/O3

Vcc

GND

I/O4
I/O5
I/O6
I/O7

WE

A10

NC

A9
A8
A7

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2
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16
17
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19
20
21
22

44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23

A0
A1
A2
OE
UB
LB
I/O15
I/O14
I/O13
I/O12
GND
Vcc
I/O11
I/O10
I/O9
I/O8
NC
A3
A4
A5
A6
NC

44-Pin TSOP-2

CE

A9
A8
A7

NC

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13
14
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19
20
21
22

A15
A14
A13
A12
A11

I/O0
I/O1
I/O2
I/O3

Vcc

GND

I/O4
I/O5
I/O6
I/O7

WE

A10

44
43
42
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40
39
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34
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31
30
29
28
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25
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A0
A1
A2
OE
UB
LB
I/O15
I/O14
I/O13
I/O12
GND
Vcc
I/O11
I/O10
I/O9
I/O8
NC
A3
A4
A5
A6
NC

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2

3

4

5

48-Pin 6x8mm TF-BGA

1 2 3 4 5 6

A7

OE

UB A2

I/O2A0

I/O

3

I/O

4

I/O

6

NC

A12

A3

NC

NC

A9

A11

A13

A1

A4

A5

NC

A8

A10

A14

A
B
C
D
E
F
G
H

LB

I/O

I/O

GND

Vcc

I/O

I/O

NC

0

1

5

7

A6

CE I/O

I/O13I/O

I/O

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I/O

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I/O

10

WE

A15 NC

N/C

Vcc

GND

I/O

I/O

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PIN DESCRIPTIONS

A0-A15 Address Inputs
I/O0-I/O15 Data Inputs/Outputs

CE Chip Enable Input
OE Output Enable Input
WE Write Enable Input
LB Lower-byte Control (I/O0-I/O7)
UB Upper-byte Control (I/O8-I/O15)

NC No Connection
Vcc Power
GND Ground

TRUTH TABLE

I/O PIN

Mode

WEWE

WE

WEWE

Not Selected X H X X X High-Z High-Z ISB1, ISB2
Output Disabled H L H X X High-Z High-Z ICC

X L X H H High-Z High-Z

Read H L L L H DOUT High-Z ICC

H L L H L High-Z DOUT
HLLLL DOUT DOUT

Write L L X L H DIN High-Z ICC

L L X H L High-Z DIN
LLXLL DIN DIN

CECE

CE

CECE

OEOE

OE

OEOE

LBLB

LB

LBLB

UBUB

UB I/O0-I/O7 I/O8-I/O15 Vcc Current

UBUB

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Integrated Circuit Solution Inc. 3

AHSR026-0A 09/12/2001

IC61LV6416

ABSOLUTE MAXIMUM RATINGS

(1)

Symbol Parameter Value Unit

VTERM Terminal Voltage with Respect to GND –0.5 to Vcc+0.5 V
TSTG Storage Temperature –65 to +150 °C
PT Power Dissipation 1.5 W
IOUT DC Output Current (LOW) 20 mA

Note:

1. Stress greater than those listed under
ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the
device. This is a stress rating only and
functional operation of the device at
these or any other conditions above
those indicated in the operational sec­tions of this specification is not implied.
Exposure to absolute maximum rating
conditions for extended periods may
affect reliability.

OPERATING RANGE

Range Ambient Temperature Vcc

Commercial 0°C to +70°C 3.3V ± 10%
Industrial –40°C to +85°C 3.3V ± 10%

DC ELECTRICAL CHARACTERISTICS (Over Operating Range)

Symbol Parameter Test Conditions Min. Max. Unit

VOH Output HIGH Voltage VCC = Min., IOH = –4.0 mA 2.4 — V
VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA — 0.4 V
VIH Input HIGH Voltage 2 VCC + 0.3 V
VIL Input LOW Voltage
ILI Input Leakage GND ≤ VIN ≤ VCC Com. –2 2 µA

(1)

–0.3 0.8 V

Ind. -5 5

ILO Output Leakage GND ≤ VOUT ≤ VCC, Outputs Disabled Com. –2 2 µA

Ind. -5 5

Notes:

IL (min.) = –2.0V for pulse width less than 10 ns.

1. V

2. The Vcc operating range for 8 ns is 3.3V +10%, -5%.

POWER SUPPLY CHARACTERISTICS

(1)

(Over Operating Range)

-8 ns -10 ns -12 ns -15 ns

Symbol Parameter Test Conditions Min. Max. Min. Max. Min. Max. Min. Max. Unit

ICC Vcc Dynamic Operating VCC = Max., Com. — 220 — 200 — 180 — 180 mA

Supply Current IOUT = 0 mA, f = fMAX Ind. — 230 — 210 — 190 — 190

ISB1 TTL Standby Current VCC = Max., Com. — 30 — 30 — 30 — 30 mA

(TTL Inputs) VIN = VIH or VIL Ind. — 40 — 40 — 40 — 40

CE ≥ VIH , f = 0

ISB2 CMOS Standby VCC = Max., Com. — 10 — 10 — 10 — 10 mA

Current (CMOS Inputs) CE ≥ VCC – 0.2V, Ind. — 15 — 15 — 15 — 15

VIN ≥ VCC – 0.2V, or
VIN ≤ 0.2V, f = 0

Note:

1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.

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AHSR026-0A 09/12/2001

IC61LV6416

319 Ω

5 pF

Including

jig and

scope

353 Ω

OUTPUT

3.3V

CAPACITANCE

Symbol Parameter Conditions Max. Unit

CIN Input Capacitance VIN = 0V 6 pF
COUT Input/Output Capacitance VOUT = 0V 8 pF

Note:

1. Tested initially and after any design or process changes that may affect these parameters.

READ CYCLE SWITCHING CHARACTERISTICS

Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Unit

tRC Read Cycle Time 8 — 10 — 12 — 15 — ns
tAA Address Access Time — 8 — 10 — 12 — 15 ns
tOHA Output Hold Time 3 — 3 — 3 — 3 — ns
tACE CE Access Time — 8 — 10 — 12 — 15 ns
tDOE OE Access Time — 4 — 5 — 6 — 7 ns

(2)

tHZOE
tLZOE
tHZCE
tLZCE
tBA LB, UB Access Time — 4 — 5 — 6 — 7 ns
tHZB LB, UB to High-Z Output 0 4 0 5 0 6 0 6 ns

OE to High-Z Output 0 4 — 5 — 6 0 6 ns

(2)

OE to Low-Z Output 0 — 0 — 0 — 0 — ns

(2

CE to High-Z Output 0 4 0 5 0 6 0 6 ns

(2)

CE to Low-Z Output 3 — 3 — 3 — 3 — ns

(1)

(1)

(Over Operating Range)

-8 -10 -12 -15

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tLZB LB, UB to Low-Z Output 0 — 0 — 0 — 0 — ns

Notes:

1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of
0 to 3.0V and output loading specified in Figure 1a.

2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.

3. Not 100% tested.

AC TEST CONDITIONS

Parameter Unit

Input Pulse Level 0V to 3.0V
Input Rise and Fall Times 3 ns
Input and Output Timing 1.5V

and Reference Level
Output Load See Figures 1a and 1b

Notes:

1. The Vcc operating range for 8 ns is 3.3V +10%, -5%.

AC TEST LOADS

3.3V

OUTPUT

Integrated Circuit Solution Inc. 5

AHSR026-0A 09/12/2001

319 Ω

30 pF

Including

jig and

scope

Figure 1a. Figure 1b.

353 Ω

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IC61LV6416

AC WAVEFORMS

READ CYCLE NO. 1

ADDRESS

D

OUT

READ CYCLE NO. 2

ADDRESS

OE

(1,2)

(Address Controlled) (CS = OE = VIL, UB or LB = VIL)

t

RC

t

AA

t

OHA

PREVIOUS DATA VALID

(1,3)

t

RC

t

AA

DATA VALID

t

OHA

t

OHA

t

DOE

t

CE

t

LZCE

LZOE

t

ACE

LB, UB

t

BA

t

OUT

D

Notes:

1. WE is HIGH for a Read Cycle.

2. The device is continuously selected. OE, CE, UB, or LB = V

3. Address is valid prior to or coincident with CE LOW transition.

HIGH-Z

LZB

t

HZOE

t

HZCE

t

HZB

DATA VALID

IL.

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IC61LV6416

WRITE CYCLE SWITCHING CHARACTERISTICS

-8 -10 -12 -15

Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Unit

tWC Write Cycle Time 8 — 10 — 12 — 15 — ns
tSCE CE to Write End 7 — 8 — 9 — 10 — ns
tAW Address Setup Time 7 — 8 — 9 — 10 — ns

to Write End

tHA Address Hold from Write End 0 — 0 — 0 — 0 — ns
tSA Address Setup Time 0 — 0 — 0 — 0 — ns
tPWB LB, UB Valid to End of Write 7 — 8 — 9 — 10 — ns
tPWE WE Pulse Width 7 — 8 — 9 — 10 — ns
tSD Data Setup to Write End 4.5 — 5 — 6 — 7 — ns
tHD Data Hold from Write End 0 — 0 — 0 — 0 — ns

(2)

tHZWE
tLZWE

Notes:

1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V
and output loading specified in Figure 1a.

2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.

3. The internal write time is defined by the overlap of CE LOW and UB or LB, and WE LOW. All signals must be in valid states to
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the write.

WE LOW to High-Z Output — 4 — 5 — 6 — 7 ns

(2)

WE HIGH to Low-Z Output 3 — 3 — 3 — 3 — ns

(1,3)

(Over Operating Range)

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IC61LV6416

AC WAVEFORMS

WRITE CYCLE NO. 1 (

ADDRESS

CE

LB, UB

WE

WRITE

(1)

WEWE

WE Controlled)

WEWE

t

SA

(1,2)

t

AW

t

SCE

t

PWB

t

PWE

t

WC

t

HA

t

t

SD

D

IN

t

HZWE

D

OUT

Notes:

1. WRITE is an internally generated signal asserted during an overlap of the LOW states on the CE and WE inputs and at least
one of the LB and UB inputs being in the LOW state.

2. WRITE = (CE)

[ (LB) = (UB) ] (WE).

UNDEFINED UNDEFINED

HD

t

LZWE

HIGH-ZHIGH-Z

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IC61LV6416

ORDERING INFORMATION
Commercial Range: 0°C to +70°C

Speed (ns) Order Part No. Package

8 IC61LV6416-8B 6*8mm TF-BGA
8 IC61LV6416-8T 400mil TSOP-2
8 IC61LV6416-8K 400mil SOJ

10 IC61LV6416-10B 6*8mm TF-BGA
10 IC61LV6416-10T 400mil TSOP-2
10 IC61LV6416-10K 400mil SOJ

12 IC61LV6416-12B 6*8mm TF-BGA
12 IC61LV6416-12T 400mil TSOP-2
12 IC61LV6416-12K 400mil SOJ

15 IC61LV6416-15B 6*8mm TF-BGA
15 IC61LV6416-15T 400mil TSOP-2
15 IC61LV6416-15K 400mil SOJ

ORDERING INFORMATION
Industrial Range: –40°C to +85°C

Speed (ns) Order Part No. Package

8 IC61LV6416-8BI 6*8mm TF-BGA
8 IC61LV6416-8TI 400mil TSOP-2
8 IC61LV6416-8KI 400mil SOJ

10 IC61LV6416-10BI 6*8mm TF-BGA
10 IC61LV6416-10TI 400mil TSOP-2
10 IC61LV6416-10KI 400mil SOJ

12 IC61LV6416-12BI 6*8mm TF-BGA
12 IC61LV6416-12TI 400mil TSOP-2
12 IC61LV6416-12KI 400mil SOJ

15 IC61LV6416-15BI 6*8mm TF-BGA
15 IC61LV6416-15TI 400mil TSOP-2
15 IC61LV6416-15KI 400mil SOJ

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Integrated Circuit Solution Inc.

HEADQUARTER:

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TEL: [phone]

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TEL: [phone]

FAX: [phone]

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Integrated Circuit Solution Inc. 9

AHSR026-0A 09/12/2001