Datasheet IC61LV5128-10K, IC61LV5128-10KI, IC61LV5128-10T, IC61LV5128-10TI, IC61LV5128-12K Datasheet (ICSI)
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IC61LV5128
Document Title
512K x 8 Hight Speed SRAM with 3.3V
Revision History
Revision No History Draft Date Remark
0A Initial Draft September 11,2001
The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and
products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices.
Integrated Circuit Solution, Inc. 1
AHSR021-0A 09/11/2001
IC61LV5128
512K x 8 HIGH-SPEED CMOS STATIC RAM
FEATURES
• High-speed access times:
— 8, 10, 12 and 15 ns
• High-preformance, lower-power CMOS process
• Multiple center power and ground pins for
greater noise immunity
• Easy memory expansion with CE and OE
options
• CE power-down
• Fully static operation: no clock or refresh
reguired
• TTL compatible inputs and outputs
• Single 3.3V ± 10% power supply
• Packages available:
— 36-pin 400mil SOJ
— 44-pin TSOP-2
FUNCTIONAL BLOCK DIAGRAM
DESCRIPTION
The ICSI IC61LV5128 is a very high-speed, low power,
524,288-word by 8-bit COMS static RAM. The IC61LV5128 is
fabricated using ICSI's high-performance CMOS technology.
This highly reliable process coupled with innovative circuit
design techniques, yields higher preformance and low power
consumotion devices.
When CE is HIGH (deselected), the device assumes a standby
mode at which the power dissipation can be reduced down to
250 µW (typical) with CMOS input levels.
The IC61LV5128 operates from a single 3.3V power supply and
all inputs are TTL-compatible.
The IC61LV5128 is available in 36-pin, 400mil SOJ and 44-pin
TSOP-2 package.
A0-A18
VCC
GND
I/O0-I/O7
CE
OE
WE
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution, Inc.
DECODER
I/O
DATA
CIRCUIT
CONTROL
CIRCUIT
512K X 8
MEMORY ARRAY
COLUMN I/O
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IC61LV5128
PIN CONFIGURATION
36-Pin SOJ
A0
A1
A2
A3
A4
CE
I/O0
I/O1
Vcc
GND
I/O2
I/O3
WE
A5
A6
A7
A8
A9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
PIN DESCRIPTIONS
NC
A18
A17
A16
A15
OE
I/O7
I/O6
GND
Vcc
I/O5
I/O4
A14
A13
A12
A11
A10
NC
PIN CONFIGURATION
44-Pin TSOP-2
TRUTH TABLE
NC
NC
CE
I/O0
I/O1
Vcc
GND
I/O2
I/O3
WE
NC
NC
44
1
2
3
A0
4
A1
5
A2
6
A3
7
A4
8
9
10
11
12
13
14
15
16
A5
17
A6
18
A7
19
A8
20
A9
21
22
NC
43
NC
42
NC
41
A18
40
A17
39
A16
38
A15
37
OE
36
I/O7
35
I/O6
34
GND
33
Vcc
32
I/O5
31
I/O4
30
A14
29
A13
28
A12
27
A11
26
A10
25
NC
24
NC
23
NC
A0-A18 Address Inputs
CE Chip Enable Input
OE Output Enable Input
WE Write Enable Input
I/O0-I/O7 Input/Output
Mode
WEWE
WE
WEWE
Not Selected X H X High-Z ISB1, ISB2
(Power-down)
Output Disabled H L H High-Z ICC
Read H L L DOUT ICC
Write L L X DIN ICC
CECE
OEOE
CE
OE I/O Operation Vcc Current
CECE
OEOE
Vcc Power
GND Ground
NC No Connection
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol Parameter Value Unit
VTERM Terminal Voltage with Respect to GND –0.5 to Vcc + 0.5 V
TBIAS Temperature Under Bias –55 to +125 °C
TSTG Storage Temperature –65 to +150 °C
PD Power Dissipation 1.0 W
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or any
other conditions above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Integrated Circuit Solution, Inc. 3
AHSR021-0A 09/11/2001
IC61LV5128
OPERATING RANGE
Range Ambient Temperature VCC
Commercial 0°C to +70°C 3.3V ± 10%
Industrial –40°C to +85°C 3.3V ± 10%
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol Parameter Test Conditions Min. Max. Unit
VOH Output HIGH Voltage VCC = Min., IOH = –4.0 mA 2.4 — V
VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA — 0.4 V
VIH Input HIGH Voltage 2.0 VCC + 0.3 V
VIL Input LOW Voltage
ILI Input Leakage GND ≤ VIN ≤ VCC Com. –1 1 µA
ILO Output Leakage GND ≤ VOUT ≤ VCC, Outputs Disabled Com. –1 1 µA
(1)
–0.3 0.8 V
Ind. –5 5
Ind. –5 5
Notes:
IL = –3.0V for pulse width less than 10 ns.
1. V
2. The Vcc operating range for 8 ns is 3.3V +10%, -5%.
POWER SUPPLY CHARACTERISTICS
(1)
(Over Operating Range)
-8 ns -10 ns -12 ns -15 ns
Symbol Parameter Test Conditions Min. Max. Min. Max. Min. Max. Min. Max. Unit
ICC Vcc Dynamic Operating VCC = Max., Com. — 300 — 280 — 260 — 240 mA
Supply Current IOUT = 0 mA, f = fMAX Ind. — 310 — 290 — 270 — 250
ISB1 TTL Standby Current VCC = Max., Com. — 55 — 55 — 55 — 55 mA
(TTL Inputs) VIN = VIH or VIL Ind. — 65 — 65 — 65 — 65
CE ≥ VIH , f = 0
ISB2 CMOS Standby VCC = Max., Com. — 10 — 10 — 10 — 10 mA
Current (CMOS Inputs) CE ≥ VCC – 0.2V, Ind. — 15 — 15 — 15 — 15
VIN ≥ VCC – 0.2V, or
VIN ≤ 0.2V, f = 0
Note:
1. At f = f
CAPACITANCE
MAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
(1,2)
Symbol Parameter Conditions Max. Unit
CIN Input Capacitance VIN = 0V 6 pF
COUT Output Capacitance VOUT = 0V 8 pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: T
A = 25°C, f = 1 MHz, Vcc = 3.3V.
4 Integrated Circuit Solution, Inc.
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IC61LV5128
READ CYCLE SWITCHING CHARACTERISTICS
(1)
(Over Operating Range)
-8 -10 -12 -15
Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Unit
tRC Read Cycle Time 8 — 10 — 12 — 15 — ns
tAA Address Access Time — 8 — 10 — 12 — 15 ns
tOHA Output Hold Time 3 — 3 — 3 — 3 — ns
tACE CE Access Time — 8 — 10 — 12 — 15 ns
tDOE OE Access Time — 4 — 5 — 6 — 7 ns
(2)
tHZOE
tLZOE
tHZCE
tLZCE
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of
0 to 3.0V and output loading specified in Figure 1a.
2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. Not 100% tested.
OE to High-Z Output 0 4 — 5 — 6 0 6 ns
(2)
OE to Low-Z Output 0 — 0 — 0 — 0 — ns
(2
CE to High-Z Output 0 4 0 5 0 6 0 6 ns
(2)
CE to Low-Z Output 3 — 3 — 3 — 3 — ns
AC TEST CONDITIONS
Parameter Unit
Input Pulse Level 0V to 3.0V
Input Rise and Fall Times 3 ns
Input and Output Timing 1.5V
and Reference Levels
Output Load See Figures 1 and 2
Notes:
1. The Vcc operating range for 8 ns is 3.3V +10%, -5%.
AC TEST LOADS
319 Ω
3.3V
OUTPUT
30 pF
Including
jig and
scope
353 Ω
OUTPUT
3.3V
5 pF
Including
jig and
scope
319 Ω
353 Ω
Figure 1. Figure 2.
Integrated Circuit Solution, Inc. 5
AHSR021-0A 09/11/2001
IC61LV5128
AC WAVEFORMS
READ CYCLE NO. 1
ADDRESS
D
OUT
READ CYCLE NO. 2
ADDRESS
OE
(1,2)
PREVIOUS DATA VALID
(1,3)
t
RC
t
AA
t
OHA
DATA VALID
t
RC
t
AA
t
OHA
t
OHA
t
DOE
t
CE
t
LZCE
OUT
D
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE = V
3. Address is valid prior to or coincident with CE LOW transitions.
HIGH-Z
LZOE
t
ACE
IL.
DATA VALID
t
HZCE
t
HZOE
6 Integrated Circuit Solution, Inc.
AHSR021-0A 09/11/2001
IC61LV5128
WRITE CYCLE SWITCHING CHARACTERISTICS
(1,3)
(Over Operating Range)
-8 -10 -12 -15
Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Unit
tWC Write Cycle Time 8 — 10 — 12 — 15 — ns
tSCE CE to Write End 7 — 8 — 9 — 10 — ns
tAW Address Setup Time 7 — 8 — 9 — 10 — ns
to Write End
tHA Address Hold from Write End 0 — 0 — 0 — 0 — ns
tSA Address Setup Time 0 — 0 — 0 — 0 — ns
tPWE WE Pulse Width 7 — 8 — 9 — 10 — ns
tSD Data Setup to Write End 4.5 — 5 — 6 — 7 — ns
tHD Data Hold from Write End 0 — 0 — 0 — 0 — ns
(2)
tHZWE
tLZWE
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1a.
2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the write.
WE LOW to High-Z Output — 4 — 5 — 6 — 7 ns
(2)
WE HIGH to Low-Z Output 3 — 3 — 3 — 3 — ns
AC WAVEFORMS
WRITE CYCLE NO. 1
ADDRESS
CE
WE
OUT
D
D
IN
(1,2 )
(CE Controlled, OE is HIGH or LOW)
VALID ADDRESS
t
SA
t
AW
t
PWE1
t
PWE2
t
HZWE
DATA UNDEFINED
t
t
WC
SCE
HIGH-Z
t
SD
DATAIN VALID
t
HA
t
LZWE
t
HD
Integrated Circuit Solution, Inc. 7
AHSR021-0A 09/11/2001
IC61LV5128
WRITE CYCLE NO. 2
(1,2)
(WE Controlled, OE is HIGH During Write Cycle)
t
WC
ADDRESS
OE
CE
LOW
WE
OUT
D
DIN
WRITE CYCLE NO. 3
VALID ADDRESS
t
AW
t
PWE1
t
SA
DATA UNDEFINED
t
HZWE
HIGH-Z
t
(WE Controlled, OE is LOW During Write Cycle)
SD
DATAIN VALID
t
HA
t
LZWE
t
HD
t
WC
ADDRESS
OE
CE
LOW
LOW
VALID ADDRESS
t
AW
t
PWE2
t
HA
WE
t
SA
D
OUT
DATA UNDEFINED
DIN
Notes:
1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the Write.
2. I/O will assume the High-Z state if OE
> VIH.
t
HZWE
HIGH-Z
t
SD
DATAIN VALID
t
LZWE
t
HD
8 Integrated Circuit Solution, Inc.
AHSR021-0A 09/11/2001
IC61LV5128
ORDERING INFORMATION
Commercial Range: 0°C to +70°C
Speed (ns) Order Part No. Package
8 IC61LV5128-8T 400mil T SOP-2
IC61LV5128-8K 400mil SOJ
10 IC61LV5128-10T 400mil T SOP-2
IC61LV5128-10K 400mil SOJ
12 IC61LV5128-12T 400mil T SOP-2
IC61LV5128-12K 400mil SOJ
15 IC61LV5128-15T 400mil T SOP-2
IC61LV5128-15K 400mil SOJ
ORDERING INFORMATION
Industrial Range: –40°C to +85°C
Speed (ns) Order Part No. Package
8 IC61LV5128-8TI 400mil T SOP-2
IC61LV5128-8KI 400mil SOJ
10 IC61LV5128-10TI 400mil T SOP-2
IC61LV5128-10KI 400mil SOJ
12 IC61LV5128-12TI 400mil T SOP-2
IC61LV5128-12KI 400mil SOJ
15 IC61LV5128-15TI 400mil T SOP-2
IC61LV5128-15KI 400mil SOJ
Integrated Circuit Solution, Inc.
HEADQUARTER:
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HSIN-CHU, TAIWAN, R.O.C.
TEL: 886-3-5780333
Fax: 886-3-5783000
BRANCH OFFICE:
7F, NO. 106, SEC. 1, HSIN-TAI 5TH ROAD,
HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C.
TEL: 886-2-26962140
FAX: 886-2-26962252
http://www.icsi.com.tw
Integrated Circuit Solution, Inc. 9
AHSR021-0A 09/11/2001
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