Datasheet IC61LV12816-10T, IC61LV12816-10TI, IC61LV12816-12B, IC61LV12816-12BI, IC61LV12816-12K Datasheet (ICSI)

IC61LV12816

Document Title

128K x 16 Hight Speed SRAM with 3.3V

Revision History

Revision No History Draft Date Remark

0A Initial Draft September 12,2001

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The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and
products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices.

Integrated Circuit Solution, Inc. 1

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IC61LV12816

128K x 16 HIGH-SPEED CMOS STATIC RAM
WITH 3.3V SUPPLY

FEATURES

• High-speed access time: 8, 10, 12, and 15 ns

• CMOS low power operation

• TTL and CMOS compatible interface levels

• Single 3.3V ± 10%power supply

• Fully static operation: no clock or refresh
required

• Three state outputs

• Data control for upper and lower bytes

• Industrial temperature available

FUNCTIONAL BLOCK DIAGRAM

DESCRIPTION

The ICSI IC61LV12816 is a high-speed, 2,097,152-bit static
RAM organized as 131,072 words by 16 bits. It is fabricated
using ICSI's high-performance CMOS technology. This highly
reliable process coupled with innovative circuit design
techniques, yields access times as fast as 8 ns with low power
consumption.

When CE is HIGH (deselected), the device assumes a standby
mode at which the power dissipation can be reduced down with
CMOS input levels.

Easy memory expansion is provided by using Chip Enable and
Output Enable inputs, CE and OE. The active LOW Write
Enable (WE) controls both writing and reading of the memory.
A data byte allows Upper Byte (UB) and Lower Byte (LB)
access.

The IC61LV12816 is packaged in the JEDEC standard 44-pin
400mil SOJ, 44-pin 400mil TSOP-2, and 48-pin 6*8mm TF­BGA.

A0-A16

VCC
GND

I/O0-I/O7

Lower Byte

I/O8-I/O15

Upper Byte

CE
OE

WE

UB

LB

ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution, Inc.

DECODER

I/O

DATA

CIRCUIT

CONTROL

CIRCUIT

128K x 16

MEMORY ARRAY

COLUMN I/O

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IC61LV12816

PIN CONFIGURATIONS

44-Pin SOJ

A4
A3
A2
A1
A0

CE
I/O0
I/O1
I/O2
I/O3

Vcc

GND

I/O4
I/O5
I/O6
I/O7

WE
A16
A15
A14
A13
A12

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2
3
4
5
6
7
8
9
10
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12
13
14
15
16
17
18
19
20
21
22

44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23

A5
A6
A7
OE
UB
LB
I/O15
I/O14
I/O13
I/O12
GND
Vcc
I/O11
I/O10
I/O9
I/O8
NC
A8
A9
A10
A11
NC

44-Pin TSOP-2

A4
A3
A2
A1
A0

CE
I/O0
I/O1
I/O2
I/O3

Vcc

GND

I/O4
I/O5
I/O6
I/O7

WE
A16
A15
A14
A13
A12

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2
3
4
5
6
7
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15
16
17
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21
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43
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40
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35
34
33
32
31
30
29
28
27
26
25
24
23

A5
A6
A7
OE
UB
LB
I/O15
I/O14
I/O13
I/O12
GND
Vcc
I/O11
I/O10
I/O9
I/O8
NC
A8
A9
A10
A11
NC

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2

3

4

5

6

48-Pin TF-BGA

1 2 3 4 5 6

A
B
C
D

E
F

G
H

LB

I/O

I/O

GND

Vcc

I/O

I/O

NC

0

1

6

7

OE

UB A3

I/O2A5

I/O

3

I/O

4

I/O

5

NC

A8

A0

NC

NC

A14

A12

A9

A1

A4

A6

A7

A16

A15

A13

A10

A2

N/C

CE I/O

I/O10I/O

I/O11Vcc

I/O

GND

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I/O

I/O

13

WE

I/O

A11 NC

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IC61LV12816

PIN DESCRIPTIONS

A0-A16 Address Inputs
I/O0-I/O15 Data Inputs/Outputs
CE Chip Enable Input

OPERATING RANGE

Range Ambient Temperature Vcc

Commercial 0°C to +70°C 3.3V ± 10%
Industrial –40°C to +85°C 3.3V ± 10%

OE Output Enable Input
WE Write Enable Input
LB Lower-byte Control (I/O0-I/O7)
UB Upper-byte Control (I/O8-I/O15)

NC No Connection
Vcc Power
GND Ground

ABSOLUTE MAXIMUM RATINGS

(1)

Symbol Parameter Value Unit

VCC Power Supply Voltage Relative to GND –0.5 to 4.0 V
VTERM Terminal Voltage with Respect to GND –0.5 to Vcc+0.5 V
TSTG Storage Temperature –65 to +150 °C
TBIAS Temperature Under Bias: Com. –65 to +85 °C

Ind. –45 to +90 °C
PT Power Dissipation 2.0 W
IOUT DC Output Current (LOW) +20 mA

Note:

1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.

DC ELECTRICAL CHARACTERISTICS (Over Operating Range)

Symbol Parameter Test Conditions Min. Max. Unit

VOH Output HIGH Voltage VCC = Min., IOH = –4.0 mA 2.4 — V
VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA — 0.4 V
VIH Input HIGH Voltage 2 VCC + 0.3 V
VIL Input LOW Voltage
ILI Input Leakage GND ≤ VIN ≤ VCC Com. –1 1 µA

ILO Output Leakage GND ≤ VOUT ≤ VCC, Com. –1 1 µA

Notes:

1. VIL (min.) = –2.0V for pulse width less than 10 ns.

2. The Vcc operating range for 8 ns is 3.3V +10%, -5%.

(1)

–0.3 0.8 V

Ind. –5 5 µA

Outputs Disabled Ind. –5 5 µA

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IC61LV12816

TRUTH TABLE

I/O PIN

Mode

Not Selected X H X X X High-Z High-Z ISB1, ISB2
Output Disabled H L H X X High-Z High-Z ICC

Read H L L L H DOUT High-Z ICC

Write L L X L H DIN High-Z ICC

WEWE

WE

WEWE

X L X H H High-Z High-Z

H L L H L High-Z DOUT
HLLLL DOUT DOUT

L L X H L High-Z DIN
LLXLL DIN DIN

CECE

CE

CECE

OEOE

OE

OEOE

LBLB

LB

LBLB

UBUB

UB I/O0-I/O7 I/O8-I/O15 Vcc Current

UBUB

1

2

3

4

POWER SUPPLY CHARACTERISTICS

Symbol Parameter Test Conditions Min. Max. Min. Max. Min. Max. Min. Max. Unit

ICC Vcc Dynamic Operating VCC = Max., CE = VIL Com. — 220 — 200 — 180 — 165 mA

Supply Current IOUT = 0 mA, f = fMAX Ind. — 230 — 210 — 190 — 175

ISB 1 TTL Standby Current VCC = Max., Com. — 30 — 30 — 30 — 30 mA

(TTL Inputs) VIN = VIH or VIL Ind. — 40 — 40 — 40 — 40

CE ≥ VIH , f = 0

ISB 2 CMOS Standby V CC = Max., Com. — 10 — 10 — 10 — 10 mA

Current (CMOS Inputs) CE ≥ VCC – 0.2V, Ind. — 15 — 15 — 15 — 15

VIN ≥ VCC – 0.2V, or
VIN ≤ 0.2V, f = 0

Note:

1. At f = f

MAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.

(1)

(Over Operating Range)

-8 ns -10 ns -12 ns -15 ns

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IC61LV12816

CAPACITANCE

(1)

Symbol Parameter Conditions Max. Unit

CIN Input Capacitance VIN = 0V 6 pF
COUT Input/Output Capacitance VOUT = 0V 8 pF

Note:

1. Tested initially and after any design or process changes that may affect these parameters.

READ CYCLE SWITCHING CHARACTERISTICS

(1)

(Over Operating Range)

-8 -10 -12 -15

Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Unit

tRC Read Cycle Time 8 — 10 — 12 — 15 — ns
tAA Address Access Time — 8 — 10 — 12 — 15 ns
tOHA Output Hold Time 3 — 3 — 3 — 3 — ns
tACE CE Access Time 8 — — 10 — 12 — 15 ns
tDOE OE Access Time — 3 — 4 — 5 — 6 ns

(2)

tHZOE
tLZOE
tHZCE
tLZCE

OE to High-Z Output — 3 — 4 — 5 0 6 ns

(2)

OE to Low-Z Output 0 — 0 — 0 — 0 — ns

(2)

CE to High-Z Output 0 3 0 4 0 5 0 8 ns

(2)

CE to Low-Z Output 3 — 3 — 3 — 3 — ns

tBA LB, UB Access Time — 3 — 4 — 5 — 6 ns

(2)

tHZB
tLZB

LB, UB to High-Z Output 0 3 0 4 0 5 0 6 ns

(2)

LB, UB to Low-Z Output 0 — 0 — 0 — 0 — ns

Notes:

1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of
0 to 3.0V and output loading specified in Figure 1.

2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.

AC TEST CONDITIONS

Parameter Unit

Input Pulse Level 0V to 3.0V
Input Rise and Fall Times 3 ns
Input and Output Timing 1.5V

and Reference Level
Output Load See Figures 1 and 2

Notes:

1. The Vcc operating range for 8 ns is 3.3V +10%, -5%.

AC TEST LOADS

5 pF

Including

jig and

scope

319 Ω

353 Ω

3.3V

OUTPUT

30 pF

Including

jig and

scope

319 Ω

3.3V

OUTPUT

353 Ω

Figure 1. Figure 2.

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IC61LV12816

AC WAVEFORMS

READ CYCLE NO. 1

ADDRESS

D

OUT

READ CYCLE NO. 2

ADDRESS

OE

(1,2)

(Address Controlled) (CE = OE = VIL, UB or LB = VIL)

t

RC

t

AA

t

OHA

PREVIOUS DATA VALID

(1,3)

t

AA

t

RC

DATA VALID

t

OHA

t

OHA

1

2

3

4

5

6

t

DOE

t

CE

t

LZCE

LB, UB

t

OUT

D

Notes:

1. WE is HIGH for a Read Cycle.

2. The device is continuously selected. OE, CE, UB, or LB = V

3. Address is valid prior to or coincident with CE LOW transition.

HIGH-Z

LZB

LZOE

t

ACE

t

BA

t

HZOE

7

t

HZCE

8

t

HZB

DATA VALID

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IL.

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IC61LV12816

WRITE CYCLE SWITCHING CHARACTERISTICS

(1,3)

(Over Operating Range)

-8 -10 -12 -15

Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Unit

tWC Write Cycle Time 8 — 10 — 12 — 15 — ns
tSCE CE to Write End 7 — 8 — 8 — 10 — ns
tAW Address Setup Time 7 — 8 — 8 — 10 — n s

to Write End

tHA Address Hold from Write End 0 — 0 — 0 — 0 — ns
tSA Address Setup Time 0 — 0 — 0 — 0 — ns
tPWB LB, UB Valid to End of Write 7 — 8 — 9 — 10 — ns

(4)

tPWE

WE Pulse Width 7 — 8 — 9 — 10 — ns

tSD Data Setup to Write End 4.5 — 5 — 6 — 7 — ns
tHD Data Hold from Write End 0 — 0 — 0 — 0 — ns

(2)

tHZWE
tLZWE

Notes:

1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V
and output loading specified in Figure 1.

2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.

3. The internal write time is defined by the overlap of CE LOW and UB or LB, and WE LOW. All signals must be in valid states to
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the write.

4.Tested with OE Hith.

WE LOW to High-Z Output — 3 — 4 — 5 — 6 ns

(2)

WE HIGH to Low-Z Output 0 — 0 — 0 — 0 — ns

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IC61LV12816

AC WAVEFORMS
WRITE CYCLE NO. 1

(1 ,2)

(CE Controlled, OE is HIGH or LOW)

t

WC

1

ADDRESS

t

SA

CE

WE

UB, LB

OUT

D

D

IN

Notes:

1. WRITE is an internally generated signal asserted during an overlap of the LOW states on the CE and WE inputs and at least
one of the LB and UB inputs being in the LOW state.

2. WRITE = (CE)

[ (LB) = (UB) ] (WE).

DATA UNDEFINED

VALID ADDRESS

t

SCE

t

AW

t

PWE1

t

PWE2

t

PWB

t

HZWE

HIGH-Z

t

SD

DATAIN VALID

t

t

HD

t

LZWE

HA

2

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IC61LV12816

WRITE CYCLE NO. 2

(1)

(WE Controlled. OE is HIGH During Write Cycle)

t

WC

ADDRESS

OE

CE

WE

UB, LB

D

OUT

D

WRITE CYCLE NO. 3

VALID ADDRESS

LOW

t

AW

t

PWE1

t

SA

t

DATA UNDEFINED

IN

(WE Controlled. OE is LOW During Write Cycle)

HZWE

t

PWB

HIGH-Z

t

SD

DATAIN VALID

t

HA

t

LZWE

t

HD

ADDRESS

OE

CE

WE

UB, LB

D

OUT

D

IN

LOW

LOW

t

SA

DATA UNDEFINED

t

WC

VALID ADDRESS

t

AW

t

PWE2

t

t

HZWE

PWB

HIGH-Z

t

SD

DATAIN VALID

t

HA

t

LZWE

t

HD

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IC61LV12816

WRITE CYCLE NO. 4

ADDRESS

(1,3)

(LB, UB Controlled, Back-to-Back Write)

t

WC

ADDRESS 1 ADDRESS 2

t

WC

1

OE

t

SA

CE

LOW

t

HA

t

WE

t

PWB

UB, LB

t

HZWE

OUT

D

Notes:

1. The internal Write time is defined by the overlap of CE = LOW, UB and/or LB = LOW, and WE = LOW. All signals must be
in valid states to initiate a Write, but any can be deasserted to terminate the Write. The
referenced to the rising or falling edge of the signal that terminates the Write.

2. Tested with OE HIGH for a minimum of 4 ns before WE = LOW to place the I/O in a HIGH-Z state.

3. WE may be held LOW across many address cycles and the LB, UB pins can be used to control the Write function.

DATA UNDEFINED

D

IN

t

SD

WORD 1

HIGH-Z

DATA

VALID

IN

SA

t

PWB

WORD 2

t

HD

t

SD

DATA

IN

VALID

t

HA

t

LZWE

t

HD

t SA, t HA, t SD, and t HD timing is

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IC61LV12816

ORDERING INFORMATION
Commercial Range: 0°C to +70°C

Speed (ns) Order Part No. Package

8 IC61LV12816-8B 6*8mm TF-BGA
8 IC61LV12816-8K 400mil SOJ
8 IC61LV12816-8T 400mil TSOP-2

10 IC61LV12816-10B 6*8mm TF-BGA
10 IC61LV12816-10K 400mil SOJ
10 IC61LV12816-10T 400mil TSOP-2

12 IC61LV12816-12B 6*8mm TF-BGA
12 IC61LV12816-12K 400mil SOJ
12 IC61LV12816-12T 400mil TSOP-2

15 IC61LV12816-15B 6*8mm TF-BGA
15 IC61LV12816-15K 400mil SOJ
15 IC61LV12816-15T 400mil TSOP-2

ORDERING INFORMATION
Industrial Range: –40°C to +85°C

Speed (ns) Order Part No. Package

8 IC61LV12816-8BI 6*8mm TF-BGA
8 IC61LV12816-8KI 400mil SOJ
8 IC61LV12816-8TI 400mil TSOP-2

10 IC61LV12816-10BI 6*8mm TF-BGA
10 IC61LV12816-10KI 400mil SOJ
10 IC61LV12816-10TI 400mil TSOP-2

12 IC61LV12816-12BI 6*8mm TF-BGA
12 IC61LV12816-12KI 400mil SOJ
12 IC61LV12816-12TI 400mil TSOP-2

15 IC61LV12816-15BI 6*8mm TF-BGA
15 IC61LV12816-15KI 400mil SOJ
15 IC61LV12816-15TI 400mil TSOP-2

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IC61LV12816

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Integrated Circuit Solution, Inc.

HEADQUARTER:

NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK,

HSIN-CHU, TAIWAN, R.O.C.

TEL: [phone]

Fax: [phone]

BRANCH OFFICE:

TH

7F, NO. 106, SEC. 1, HSIN-TAI 5

HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C.

TEL: [phone]

FAX: [phone]

http://www.icsi.com.tw

ROAD,

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