• Form, Fit and Function Compatible with the DEC 21140AF
• Available in 144 Pin PQFP Package
• Integrated Ethernet controller with PCI bus interface
• Supports 10 Mb/s and 10/100 Mb/s network interface
• PCS and scrambler/descrambler circuitry on chip
• Supports multiple PCI features:
- Unlimited PCI burst
- PCI read multiple
- PCI write and invalidate
- PCI read line
- PCI 5.0V and 3.3V environments
• Multiple interrupt sources
• Contains two independent 3K FIFOs to minimize external memory additions
• Provides sleep or snooze low-power modes
• Interfaces with MicroWire Serial ROM
• Provides a JTAG test port with boundary scan function
• Complies with IEEE 802.3, ANSI 8802-3, and Ethernet standards
The IA21140AF is a "plug -and-play" drop-in replacement for the original IC. innovASIC produces
replacement ICs using its MILESTM, or Managed IC Lifetime Extension System, cloning technology. This
technology produces replacement ICs far more complex than "emulation" while ensuring they are compatible
with the origina l IC. MILESTM captures the design of a clone so it can be produced even as silicon
technology advances. MILESTM also verifies the clone against the original IC so that even the
"undocumented features" are duplicated. This data sheet documents all necessary engineering information
about the IA21140AF including functional and I/O descriptions, electrical characteristics, and applicable
timing.
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IA21140AF Preliminary Data Sheet
PCI FAST ETHERNET LAN CONTROLLER
Description
The innovASIC IA21140AF Fast Ethernet LAN controller provides a direct interface connection to
the PCI (Peripheral Component Interface) bus. It interfaces with the PCI bus by using on-chip
control and status registers (CSR’s), and a shared CPU memory area. The memory is initialized once
during setup to minimize CPU overhead during normal operation. Large receive and transmit
FIFO’s are contained on-chip so no additional on board memory is required. The IA21140AF
includes two on chip direct memory access (DMA) controllers with programmable burst size
providing for low CPU utilization. A PCI clock frequency from dc to 33 MHz (20-33 MHz for
operational network interface) is supported. Two network ports are supported. A serial standard 7wire 10-Mbps port (SRL) and a media independent interface/symbol 10/100-Mbps port
(MII/SYM). The 10 Mbps implements a direct interface to the external 10 Mbps front-end decoder
(ENDEC). The 10/100 Mbps port supports two modes. The first is a 100BASE -X physical coding
sublayer (PCS). The second is a full implementation of the MII standard. The IA21140AF functions
in a full-duplex environment for either network port.
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IA21140AF PreliminaryData Sheet
When the IA21140AF is the bus master, this signal is asserted during write
bit ad bus. It is asserted
during read operations to indicate the master is ready to accept data. It is
asserted during a write to indicate that valid data is on the AD lines. A data
ock when both irdy_n and
trdy_n are asserted. Wait cycles are inserted until both these signals are
When an external physical layer protocol (PHY) device detects a collision, it
An external PHY sets this bit when receive data is on the mii_sym_rxd lines
and is cleared at the end of the packet. This signal is synchronized with
or is detected by an external PHY device, this pin
gets set. It is synchronized to mii_sym_rclk and can be set for a minimum of
one receive clock. It sets the cyclic redundancy check (CRC) error bit in the
Goes to the PHY devices as timing reference for the transfer of information
selected. Cleared when the SRL port is
This clock, recovered by the PHY, supports either the 25 MHz or 2.5 MHz
When MII mode is selected, these four parallel data lines receive data that is
n by external PHY that attached the media. Synchronized to the
This 25 MHz or 2.5 MHz transmit clock is supplied by the external physical
These four parallel transmit data lines are synchronized and latched by the
This signal indicates a transmit to an external PHY device. It reflects the
Timing of the PCI related functions is based on this DC to 33 MHz clock. All
bus signals except int_n and rst_n are sampled on the rising edge of this
Used for reporting data parity errors during all PCI transactions except a
When asserted for at least 10 PCI clock cycles, the IA21140AF is reset to its
put pins are tristated and all PCI O/D signals are left
PCI FAST ETHERNET LAN CONTROLLER
NAME Type
irdy_n I/O
operations indicating valid data is present on the 32 -
phase is completed on any rising edge of the cl
asserted together.
mii_clsn I
asserts this signal.
Carrier sense
mii_crs
mii_dv I
mii_err I When a data decoding err
mii_mdc O
mii_mdio I/O Transfers control information and status between the IA21140AF and PHY.
mii_srl O Set when the MII/SYM port is
mii_sym_rclk I
mii_sym_rxd[3:0] I
mii_sym_tclk I
mii_sym_txd[3:0] O
mii_txen O
Nc O No connection pins
Par I/O Even parity bit for the 32-bit ad bus and the 4-bit c_be_n lines. It is driven by
pci_clk I
I The PHY sets this bit when the media is active.
mii_sym_rclk.
receive descriptor (RDES0) when it is set during a packet reception.
on the mii_mdio signal.
selected.
receive clock.
drive
mii_sym_rclk signal.
layer medium dependent device (PMD) and must always be active.
external PHY on the rising edge of the mii_sym_tclk signal.
transmit activity of the MAC sublayer when in the PCS mode (CSR6[23]).
the master for address and write data phases and driven by the target for
read data phases.
Description
clock.
perr_n I/O
special cycle.
rcv_match O Set when a received packet passes address recognition.
req_n O Request to the bus arbiter for the IA21140AF to use the bus.
rst_n I
initial state. PCI out
floating.
sd I Supplied by an external PMD device.
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IA21140AF PreliminaryData Sheet
Reports errors other than parity. Signal must be valid for at least one clock
hernet cable to the IA21140AF.
Asserted and deasserted asynchronously by the external ENDEC with
Carries the recovered receive clock supplied by an external ENDEC. May be
rries the input receive data from the external ENDEC. Incoming data
Set when receive data is present on the Ethernet cable and cleared at the
usly to the receive clock by the
Carries the transmit clock supplied by an external ENDEC. Must be always
Carries the serial output data from the IA21140AF and is synchronized to
The current target is requesting the bus master to stop the current
This signal and the four receive lines mii_sym_rxd[3:0], provide five parallel
data lines in symbol form for use in PCS mode. Data is driven by an external
gnal and the four transmit lines mii_sym_txd[3:0], provide five parallel
data lines in symbol form for use in PCS mode. Data is synchronized on the
data
During JTAG test operations this pin serially shifts test data and instruction
resistor and
During JTAG test operations this pin serially shifts test data and instructions
Controls the state operation of JTAG testing in the IA21140AF. The pin is
Indicates the readiness of the target’s agent to complete the current data
phase of the transaction. During reads, this signal indicates that valid data is
arget is ready to
accept data. A data phase is completed on any clock when both irdy_n and
PCI FAST ETHERNET LAN CONTROLLER
NAME Type
serr_n O/D
cycle. This pin pulled up by an external resistor.
sr_ck O Serial ROM clock.
sr_cs O Serial ROM chip -select pin pulled down by an internal 2 k O resistor.
sr_di O Serial ROM data-in.
sr_do I Serial ROM data-out pin pulled up by an internal 5 k O resistor.
srl_clsn I Indicates a collision occurrence on the Et
respect to the receive clock.
srl_rclk I
inactive during idle periods.
srl_rxd I Ca
should be synchronous with receive clock (srl_rclk) signal.
srl_rxen I
end of a frame. Set and cleared asynchrono
external ENDEC.
srl_tclk I
active, even during reset.
srl_txd O
transmit clock signal.
srl_txen O Signals an external ENDEC that the IA21140AF transmit is in progress.
stop_n I/O
transaction.
sym_link O Descrambler is locked to the input data signal.
sym_rxd[4] I
Description
PMD device and is synchronized with respect to the mii_sym_rclk signal.
sym_txd[4] O This si
rising edge of mii_sym_tclk.
tck I During JTAG test operations this clock shifts state information and test
into and out of the IA21140AF. The pin should not be left unconnected.
Tdi I
into the IA21140AF. The pin is pulled up by an internal 5 k O
should not be left unconnected.
tdo O
out of the IA21140AF.
tms I
pulled up by an internal 5 k O resistor and should not be left unconnected.
trdy_n I/O
present on AD lines. During writes, this signal indicates the t
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IA21140AF Preliminary Data Sheet
PCI FAST ETHERNET LAN CONTROLLER
PCI Other Signals:
Timing Diagram
clk
Tval (max)Tval (min)
output
TonToff
input
Th
Tsu
Note: Vtest is 1.5 V in a 5.0 V signaling environment and is
0.4 * vdd_clamp in a 3.3 V signaling environment.
Timing Characteristics
Symbol Parameter Min Max Unit
Vtest*
Tval clk-to-signal valid delay 2 11 ns
Ton Float-to-active delay from clk 2 - ns
Toff Active-to-float delay from clk - 28 ns
Tsu Input signal valid setup time before clk 7 - ns
Th Input signal hold time from clk 0 - ns
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IA21140AF Preliminary Data Sheet
PCI FAST ETHERNET LAN CONTROLLER
Serial Port Timing Waveforms:
Transmit:
Timing Diagram
TtcfTtcr
TtclTtch
srl_tclk
Ttcc
TtdpTtdh
srl_txd[3:0]
TtepTteh
srl_txen
Timing Characteristics
Symbol Definition Min Max units
Ttcl srl_tclk low time 45 55 ns
Ttch srl_tclk high time 45 55 ns
Ttcr srl_tclk rise time - 8 ns
Ttcf srl_tclk fall time - 8 ns
Ttdp srl_tclk fall time to srl_txd valid - 26 ns
Ttdh srl_txd hold after srl_tclk fall time 5 - ns
Ttep srl_tclk fall time to srl_txen valid - 26 ns
Tteh srl_txen hold after srl_tclk fall time 5 - ns
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IA21140AF Preliminary Data Sheet
PCI FAST ETHERNET LAN CONTROLLER
Timing Characteristics
Symbol Definition Min Max Units
Trcc srl_rclk cycle time 85 118 ns
Trcl srl_rclk low time 38 80 ns
Trch srl_rclk high time 38 80 ns
Trcr srl_rclk rise time - 8 ns
Trcf srl_rclk fall time - 8 ns
Trds srl_rxd setup to srl_rclk fall time 10 - ns
Trdh srl_rxd hold after srl_rclk fall time 5 - ns
Trel srl_rxen low time 120 - ns
treh srl_rxen hold after srl_rclk rise time 10 100 ns