Datasheet I74F113D Datasheet (Philips)

INTEGRATED CIRCUITS

74F113

Dual J-K negative edge-triggered flip-flops without reset

Product specification IC15 Data Handbook

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1991 Feb 14

Philips Semiconductors Product specification

Dual J-K negative edge-triggered flip-flops without reset

FEA TURE

•Industrial temperature range available (–40°C to +85°C)

DESCRIPTION

The 74F113, dual negative edge-triggered JK-type flip-flop, features individual J, K, clock (CP outputs. The asynchronous S to the steady state levels as shown in the function table regardless of the level at the other inputs.

A high level on the clock (CP data will be accepted. The logic levels at the J and K inputs may be allowed to change while the CP according to the function table as long as minimum setup and hold times are observed. Output changes are initiated by the high-to-low transition of the CP

TYPE TYPICAL f

74F113 100MHz 15mA

ORDERING INFORMATION

DESCRIPTION

14-pin plastic DIP N74F113N I74F1 13N SOT27–1

14-pin plastic SO N74F113D I74F1 13D SOT108–1

), set (SD) inputs, true and complementary

D input, when low, forces the outputs

) input enables the J and K inputs and

is high and flip-flop will perform

.

COMMERCIAL RANGE

VCC = 5V ±10%,

T

= 0°C to +70°C

amb

max

ORDER CODE

PIN CONFIGURATION

CP

1

0

2

K0

J0

3

S

D0

4

Q0

5

0

6

Q

GND

TYPICAL SUPPLY CURRENT (TOTAL)

INDUSTRIAL RANGE

VCC = 5V ±10%,

T

= –40°C to +85°C

amb

14 13 12 11 10

9 87

SF00140

V CP

K1 J1 SD1 Q1 Q1

74F1 13

CC

1

PKG. DWG. #

INPUT AND OUTPUT LOADING AND FAN-OUT TABLE

PINS DESCRIPTION 74F (U.L.) HIGH/LOW LOAD VALUE HIGH/LOW

J0, J1 J inputs 1.0/1.0 20µA/0.6mA

K0, K1 K inputs 1.0/1.0 20µA/0.6mA CP0, CP1 Clock inputs (active falling edge) 1.0/4.0 20µA/2.4mA SD0, SD1 Set inputs (active low) 1.0/5.0 20µA/3.0mA

Q0, Q1, Q0, Q1 Data outputs 50/33 1.0mA/20mA

NOTE:

One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state.

LOGIC SYMBOL

1

4 13 10

VCC = Pin 14 GND = Pin 7

CP0 SD0

CP1 SD1

311

J1 K0

Q0 Q0

56

212

K1J0

Q1 Q1

98

SF00141

IEC/IEEE SYMBOL

3 1 2 4

11

13 12 10

1J

C1

1K 1S

2J

C2

2K 2S

5

6

9

8

SF00142

1996 Mar 14 853–0339 16575

2

Philips Semiconductors Product specification

OPERATING MODE

T

Operating free-air temperature range

SYMBOL

PARAMETER

UNIT

T

Operating free-air temperature range

Dual J-K negative edge-triggered flip-flops without reset

LOGIC DIAGRAM

5, 9

Q

4, 10

S

D

2, 12

K

V

= Pin 14

CC

GND = Pin 7

1, 13

CP

6, 8

3, 11

SF00143

Q

J

74F113

FUNCTION TABLE

INPUTS OUTPUTS

SD CP J K Q Q

L X X X H L Asynchronous set H ↓ h h q q Toggle H ↓ h l H L Load ”1” (set) H ↓ l h L H Load ”0” (reset) H ↓ l l q q Hold ’no change”

NOTES:

H = High-voltage level h = High-voltage level one setup time prior to high-to-low

clock transition L = Low-voltage level l = Low-voltage level one setup time prior to high-to-low clock

transition q = Lower case indicate the state of the referenced output

prior to the high-to-low clock transition X = Don’t care ↓ = high-to-low clock transition

ABSOLUTE MAXIMUM RATINGS

(Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range.)

SYMBOL

V

CC

V

IN

I

IN

V

OUT

I

OUT

amb

T

stg

Supply voltage –0.5 to +7.0 V Input voltage –0.5 to +7.0 V Input current –30 to +5 mA Voltage applied to output in High output state –0.5 to V Current applied to output in Low output state 40 mA

p

Storage temperature range –65 to +150 °C

PARAMETER RATING UNIT

Commercial range 0 to +70 °C

Industrial range –40 to +85 °C

RECOMMENDED OPERATING CONDITIONS

V V V I I I

CC IH

IL IK OH OL

amb

Supply voltage 4.5 5.0 5.5 V High-level input voltage 2.0 V Low-level input voltage 0.8 V Input clamp current –18 mA High-level output current –1 mA Low-level output current 20 mA

p

Commercial range 0 +70 °C

Industrial range –40 +85 °C

CC

LIMITS

MIN NOM MAX

V

1996 Mar 14

3

Philips Semiconductors Product specification

SYMBOL

PARAMETER

TEST CONDITIONS

1

UNIT

,

VOHHigh-level output voltage

V

CC

MIN, V

IL

MAX,

I

MAX

,

VOLLow-level output voltage

V

CC

MIN, V

IL

MAX,

I

MAX

Dual J-K negative edge-triggered flip-flops without reset

DC ELECTRICAL CHARACTERISTICS

(Over recommended operating free-air temperature range unless otherwise noted.)

LIMITS

MIN TYP2MAX

V

= MIN, V

p

V

IK

I

IH

Input clamp voltage VCC = MIN, II = I Input current at maximum input voltage VCC = MAX, VI = 7.0V 100 µA High-level input current VCC = MAX, VI = 2.7V 20 µA

VIH = MIN

V

= MIN, V

VIH = MIN

= MAX

IK

OH

OL

=

±10%V

±5%V

±10%V

±5%V

Jn, Kn –0.6 mA

I

IL

Low-level input current

CPn

VCC = MAX, VI = 0.5V

SDn –3.0 mA

I

OS

I

CC

Short-circuit output current Supply current4 (total) VCC = MAX 15 21 mA

3

VCC = MAX -60 –150 mA

NOTES:

1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.

2. All typical values are at V

3. Not more than one output should be shorted at a time. For testing I

CC

= 5V, T

techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting

amb

= 25°C.

, the use of high-speed test apparatus and/or sample-and-hold

OS

of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, I

4. Measure I

with the clock input grounded and all outputs open, then with Q and Q outputs high in turn.

CC

tests should be performed last.

OS

2.5 V

CC

2.7 3.4 V

CC

–0.73 –1.2 V

74F113

0.30 0.50 V

–2.4 mA

AC ELECTRICAL CHARACTERISTICS

LIMITS

SYMBOL PARAMETER

TEST

CONDITION

VCC = +5.0V

T

= +25°C

amb

= 50pF

C

L

R

= 500Ω

L

VCC = +5.0V ± 10%

T

= 0°C to +70°C

amb

= 50pF

C

L

R

= 500Ω

L

VCC = +5.0V ± 10%

T

= –40°C to +85°C

amb

= 50pF

C

L

R

= 500Ω

L

MIN TYP MAX MIN MAX MIN MAX

f

max

t

PLH

t

PHL

t

PLH

t

PHL

Maximum clock frequency Waveform 1 85 100 80 80 ns Propagation delay

CPn to Qn or Q

n

Propagation delay SDn, to Qn or Qn

Waveform 1

Waveform 2

2.0

4.0

4.5

6.0

6.5

2.0

7.0

7.5

2.0

7.5

7.0

8.0

7.5

AC SETUP REQUIREMENTS

LIMITS

VCC = +5.0V

T

SYMBOL PARAMETER

TEST

CONDITION

amb

C R

L L

= +25°C = 50pF = 500Ω

MIN TYP MAX MIN MAX MIN MAX

t

(H)

su

tsu(L) t

(H)

h

t

(L)

h

t

(H)

w

t

(L)

w

t

(L) SDn pulse width, low Waveform 2 4.5 5.0 5.0 ns

w

t

rec

Setup time, high or low Jn, Kn to CPn

Hold time, high or low Jn, Kn to CPn

CP pulse width, high or low

Recovery time SDn to CPn

Waveform 1

4.0

3.5

0.0

4.5

Waveform 2 4.5 5.0 5.0 ns

VCC = +5.0V ± 10%

T

= 0°C to +70°C

amb

C

= 50pF

L

R

= 500Ω

L

5.0

4.0

0.0

5.0

VCC = +5.0V ± 10%

T

= –40°C to +85°C

amb

C

= 50pF

L

R

= 500Ω

L

5.0

4.5

0.0

5.0

UNIT

ns

UNIT

ns

1996 Mar 14

4

Philips Semiconductors Product specification

Dual J-K negative edge-triggered flip-flops without reset

AC WAVEFORMS

For all waveforms, VM = 1.5V. The shaded areas indicate when the input is permitted to change for predictable output performance.

Kn

Jn, Kn

CPn

Qn

V

M

Jn

tsu(L) th(L) = 0

V

M

t

PLH

t

PHL

1/f

max

(L)

t

w

V

M

V

M

Waveform 1. Propagation Delay for Data to Output, Data Setup Time and Hold Times, and Clock Width,

and Maximum Clock Frequency

Jn

V

M

Kn

tsu(H)

tw(H)

V

M

t

(H) = 0

h

V

M

t

PHL

V

M

t

PLH

V

74F113

M

SF00144

Jn, Kn

SDn

CPn

Qn

t

PLH

t

PHL

tw(L)

V

M

V

M

t

rec

V

M

V

M

V

M

SF00145

Waveform 2. Propagation Delay for Set to Output, Set Pulse Width, and Recovery Time for Set to Clock

1996 Mar 14

5

Philips Semiconductors Product specification

Dual J-K negative edge-triggered flip-flops without reset

TEST CIRCUIT AND WAVEFORMS

V

CC

NEGATIVE PULSE

V

PULSE

GENERATOR

IN

R

T

Test Circuit for Totem-Pole Outputs

DEFINITIONS:

= Load resistor;

R

L

see AC ELECTRICAL CHARACTERISTICS for value.

= Load capacitance includes jig and probe capacitance;

C

L

see AC ELECTRICAL CHARACTERISTICS for value.

R

= T ermination resistance should be equal to Z

T

pulse generators.

D.U.T.

V

OUT

R

C

L

POSITIVE PULSE

of

OUT

family

74F

90%

10%

amplitude

3.0V

t

w

V

M

10%

)

t

THL (tf

)

t

TLH (tr

90%

V

M

t

w

TLH (tr

THL (tf

10%

)

90%

V

M

V

Input Pulse Definition

INPUT PULSE REQUIREMENTS

V

M

1.5V

rep. rate

1MHz 500ns

t

w

90%

M

10%

t

TLHtTHL

2.5ns 2.5ns

74F113

AMP (V)

0V

AMP (V)

0V

SF00006

1996 Mar 14

6

Philips Semiconductors Product specification

Dual J-K negative edge-triggered flip-flops without reset

DIP14: plastic dual in-line package; 14 leads (300 mil) SOT27-1

74F113

1996 Mar 14

7

Philips Semiconductors Product specification

Dual J-K negative edge-triggered flip-flops without reset

SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1

74F113

1996 Mar 14

8

Philips Semiconductors Product specification

Dual J-K negative edge-triggered flip-flops without reset

NOTES

74F113

1996 Mar 14

9

Philips Semiconductors Product specification

Dual J-K negative edge-triggered flip-flops without reset

Data sheet status

Objective specification

Preliminary specification

Product specification

Product status

Development

Qualification

Production

Definition

This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice.

This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product.

This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.

[1]

74F113

[1] Please consult the most recently issued datasheet before initiating or completing a design.

Definitions

Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For

detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one

or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.

Disclaimers

Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can

reasonably be expected to result in personal injury . Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.

Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.

Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381

 Copyright Philips Electronics North America Corporation 1998

print code Date of release: 10-98 Document order number: 9397-750-05072

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