Datasheet I74F112N Datasheet (Philips)

INTEGRATED CIRCUITS

74F112

Dual J-K negative edge-triggered flip-flop

Product specification IC15 Data Handbook

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1990 Feb 09

Philips Semiconductors Product specification

74F1 12Dual J-K negative edge-triggered flip-flop

FEA TURE

PIN CONFIGURATION

•Industrial temperature range available (–40°C to +85°C)

1

0

CP

2

DESCRIPTION

The 74F112, Dual Negative Edge-Triggered JK-Type Flip-Flop, feature individual J, K, Clock (CP inputs, true (Qn) and complementary (Q

The SD and RD inputs, when Low, set or reset the outputs as shown in the Function Table, regardless of the level at the other inputs.

A High level on the clock (CP

n), Set (SD) and Reset (RD)

n) outputs.

n) input enables the J and K inputs and

K0

J0

3

S

4

D0

5

Q0

0

6

Q Q

1

data will be accepted. The logic levels at the J and K inputs may be allowed to change while the CP

n is High and flip-flop will perform according to the Function Table as long as minimum setup and hold times are observed. Output changes are initiated by the High-to-Low transition of the CP

n.

TYPE TYPICAL PROPAGATION DELAY TYPICAL SUPPLY CURRENT (TOTAL)

74F112 100MHz 15mA

ORDERING INFORMATION

ORDER CODE

DESCRIPTION

16-pin plastic DIP N74F112N I74F1 12N SOT38-4

16-pin plastic SO N74F112D I74F1 12D SOT109-1

COMMERCIAL RANGE

VCC = 5V ±10%, T

= 0°C to +70°C

amb

VCC = 5V ±10%, T

INDUSTRIAL RANGE

= –40°C to +85°C

amb

16 15 14 13 12 11 107

98GND Q1

SF00103

V R R

CP1 K1 J1 SD1

CC

D0 D1

PKG DWG #

INPUT AND OUTPUT LOADING AND FAN-OUT TABLE

PINS DESCRIPTION 74F (U.L.) HIGH/LOW LOAD VALUE HIGH/LOW

J0, J1 J inputs 1.0/1.0 20µA/0.6mA

K0, K1 K inputs 1.0/1.0 20µA/0.6mA SD0, SD1 Set inputs (active Low) 1.0/5.0 20µA/3.0mA RD0, RD1 Reset inputs (active Low) 1.0/5.0 20µA/3.0mA CP0, CP1 Clock Pulse input (active falling edge) 1.0/4.0 20µA/2.4mA

Q0, Q0; Q1, Q1 Data outputs 50/33 1.0mA/20mA

NOTE:

One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state.

February 9, 1990 853–0338 98775

2

Philips Semiconductors Product specification

OPERATING MODE

74F112Dual J-K negative edge-triggered flip-flop

LOGIC SYMBOL

1

4 15 13 10 14

VCC = Pin 16 GND = Pin 8

LOGIC DIAGRAM

311

J1 K0

CP0 SD0 RD0 CP1 SD1 RD1

Q0 Q0 Q1 Q1

56 97

Qn

4, 10

S

Dn

2, 12

Kn

212

SF00104

5, 9

IEC/IEEE SYMBOL

3 1

K1J0

2

15

4

11 13

12 14 10

1J

C1

1K

R S

2J

C2

2K

R S

6, 7

n

Q

15, 14

R

Dn

3, 11

Jn

5

6

9

7

SF00105

VCC = Pin 16 GND = Pin 8

CP

1, 13 n

FUNCTION TABLE

INPUTS OUTPUTS

SD RD CP J K Q Q

L H X X X H L Asynchronous Set

H L X X X L H Asynchronous Reset

L L X X X H* H* Undetermined * H H ↓ h h q q Toggle H H ↓ l h L H Load “0” (Reset) H H ↓ h l H L Load “1” (Set) H H ↓ l l q q Hold “no change” H H H X X Q Q Hold “no change”

H = High voltage level h = High voltage level one setup time prior to High-to-Low clock transition L = Low voltage level l = Low voltage level one setup time prior to High-to-Low clock transition q = Lower case letters indicate the state of the reference output prior to the High-to-Low clock transition X = Don’t care ↓ = High-to-Low clock transition * = Both outputs will be High while both S

D and RD are Low, but the output states are unpredictable if SD and RD go High simultaneously.

SF00106

February 9, 1990

3

Philips Semiconductors Product specification

T

Operating free-air temperature range

SYMBOL

PARAMETER

UNIT

T

Operating free-air temperature range

SYMBOL

PARAMETER

TEST CONDITIONS

1

UNIT

VOHHigh-level output voltage

V

VOLLow-level output voltage

V

74F112Dual J-K negative edge-triggered flip-flop

ABSOLUTE MAXIMUM RATINGS

(Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range.)

SYMBOL

V V I

IN

V I

OUT

T

CC IN

OUT

amb

stg

Supply voltage –0.5 to +7.0 V Input voltage –0.5 to +7.0 V Input current –30 to +5 mA Voltage applied to output in High output state –0.5 to V Current applied to output in Low output state 40 mA

p

Storage temperature range –65 to +150 °C

RECOMMENDED OPERATING CONDITIONS

V V V I I I

CC IH

IL IK OH OL

amb

Supply voltage 4.5 5.0 5.5 V High-level input voltage 2.0 V Low-level input voltage 0.8 V Input clamp current –18 mA High-level output current –1 mA Low-level output current 20 mA

p

PARAMETER RATING UNIT

CC

V

Commercial range 0 to +70 °C

Industrial range –40 to +85 °C

LIMITS

MIN NOM MAX

Commercial range 0 +70 °C

Industrial range –40 +85 °C

DC ELECTRICAL CHARACTERISTICS

(Over recommended operating free-air temperature range unless otherwise noted.)

LIMITS

MIN TYP

p

V

IK

I

IH

Input clamp voltage VCC = MIN, II = I Input current at maximum input voltage VCC = MAX, VI = 7.0V 100 µA

High-level input current VCC = MAX, VI = 2.7V 20 µA

VCC = MIN, VIL = MAX ±10%V VIH = MIN, IOH = MAX ±5%V VCC = MIN, VIL = MAX ±10%V VIH = MIN, IOL = MAX ±5%V

IK

CC

2.5

2.7 3.4

Jn, Kn –0.6 mA

I

IL

Low-level input current

CPn

VCC = MAX, VI = 0.5V

SDn, RDn –3.0 mA

I

OS

I

CC

Short-circuit output current Supply current (total)

3

4

VCC = MAX –60 –150 mA VCC = MAX 15 21 mA

NOTES:

1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.

2. All typical values are at V

3. Not more than one output should be shorted at a time. For testing I

CC

= 5V, T

techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting

amb

= 25°C.

, the use of high-speed test apparatus and/or sample-and-hold

OS

of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, I

4. Measure I

with the clock input grounded and all outputs open, with the Q and Q outputs High in turn.

CC

tests should be performed last.

OS

2

MAX

0.35 0.50

–0.73 –1.2 V

–2.4 mA

February 9, 1990

4

Philips Semiconductors Product specification

74F112Dual J-K negative edge-triggered flip-flop

AC ELECTRICAL CHARACTERISTICS

LIMITS

SYMBOL PARAMETER

f

MAX

t

PLH

t

PHL

t

PLH

t

PHL

Maximum clock frequency Waveform 1 85 100 80 80 MHz

Propagation delay CP to Qn or Qn

Propagation delay SDn, RD to Qn or Qn

AC SETUP REQUIREMENTS

SYMBOL PARAMETER

tS(H) tS((L)

th(H) th(L)

tW(H) t

(L)

W

tW(L)

t

REC

Setup time, High or Low Jn, Kn to CP

Hold time, High or Low Jn, Kn to CP

CP Pulse width High or Low

SDn, RD Pulse width Low

Recovery time SDn, RD to CP

VCC = +5.0V

T

TEST

CONDITION

amb

C R

L L

= +25°C = 50pF = 500Ω

MIN TYP MAX MIN MAX MIN MAX

2.0

Waveform 1

Waveform 2,3

2.0

5.0

4.5

VCC = +5.0V

T

TEST

CONDITION

amb

C R

L L

= +25°C = 50pF = 500Ω

MIN TYP MAX MIN MAX MIN MAX

Waveform 1

4.0

3.5

0.0

4.5

Waveform 2,3 4.5 5.0 5.0 ns

VCC = +5.0V ± 10%

T

amb

6.5

2.0

VCC = +5.0V ± 10%

T

amb

5.0

4.0

0.0

5.0

= 0°C to +70°C

C

= 50pF

L

= 500Ω

R

L

7.5

LIMITS

= 0°C to +70°C

C

= 50pF

L

R

= 500Ω

L

VCC = +5.0V ± 10%

T

= –40°C to +85°C

amb

C

= 50pF

L

= 500Ω

R

L

2.0

1.5

VCC = +5.0V ± 10%

T

= –40°C to +85°C

amb

C

= 50pF

L

R

= 500Ω

L

5.0

4.0

0.0

5.0

7.5

UNIT

ns

UNIT

ns

AC WAVEFORMS

For all waveforms, VM = 1.5V.

Jn, Kn

CPn

Qn

V

The shaded areas indicate when the input is permitted to change for predictable output performance.

Waveform 1. Propagation Delay for Data to Output, Data Setup Time and Hold Times, and Clock Pulse Width

February 9, 1990

M

ts(L) th(L)

V

M

V

M

t

PLH

t

PHL

tw(L)

V

ts(H) th(H)

f

max

V

M

V

M

V

M

(H)

t

w

V

M

V

M

t

PHL

t

M

V

PLH

M

V

M

SF00107

5

Philips Semiconductors Product specification

74F112Dual J-K negative edge-triggered flip-flop

Jn, Kn

t

PLH

t

PHL

tw(L)

V

M

t

REC

V

M

V

M

V

M

SF00108

SDn

CPn

Qn

V

M

Waveform 2. Propagation Delay for Set to Output, Set Pulse Width, and Recovery Time for Set to Clock

Jn, Kn

t

PHL

t

PLH

tw(L)

V

M

t

REC

V

M

V

M

RDn

CPn

Qn

V

M

Waveform 3. Propagation Delay for Reset to Output, Reset Pulse Width, and Recovery Time for Reset to Clock

February 9, 1990

Qn

V

M

SF00109

6

Philips Semiconductors Product specification

74F112Dual J-K negative edge-triggered flip-flop

TEST CIRCUIT AND WAVEFORMS

V

CC

PULSE

GENERATOR

V

IN

R

T

D.U.T.

V

OUT

R

C

L

Test Circuit for Totem-Pole Outputs

DEFINITIONS:

= Load resistor;

R

L

see AC ELECTRICAL CHARACTERISTICS for value.

= Load capacitance includes jig and probe capacitance;

C

L

see AC ELECTRICAL CHARACTERISTICS for value.

R

= Termination resistance should be equal to Z

T

pulse generators.

OUT

of

NEGATIVE PULSE

POSITIVE PULSE

family

74F

90%

10%

amplitude

t

w

V

M

10%

)

V

90%

M

t

THL (tf

t

TLH (tr

)

t

TLH (tr

t

THL (tf

t

w

Input Pulse Definition

INPUT PULSE REQUIREMENTS

V

rep. rate

M

3.0V

1.5V

1MHz 500ns

10%

)

90%

t

w

V

M

V

M

90%

10%

t

TLHtTHL

2.5ns 2.5ns

AMP (V)

0V

AMP (V)

0V

SF00006

February 9, 1990

7

Philips Semiconductors Product specification

Dual J-K negative edge-triggered flip-flop

DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4

74F112

1990 Feb 09

8

Philips Semiconductors Product specification

Dual J-K negative edge-triggered flip-flop

SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1

74F112

1990 Feb 09

9

Philips Semiconductors Product specification

Dual J-K negative edge-triggered flip-flop

Data sheet status

Objective specification

Preliminary specification

Product specification

Product status

Development

Qualification

Production

Definition

This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice.

This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product.

This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.

[1]

74F112

[1] Please consult the most recently issued datasheet before initiating or completing a design.

Definitions

Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For

detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one

or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.

Disclaimers

Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can

reasonably be expected to result in personal injury . Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.

Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.

Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381

 Copyright Philips Electronics North America Corporation 1998

print code Date of release: 10-98 Document order number: 9397-750-05071

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