Datasheet HY628100AG-55, HY628100AG-70, HY628100AG-85, HY628100ALG-55, HY628100ALG-70 Datasheet (HEI)

This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. No patent licenses are implied.

Rev.05 /Feb.99 Hyundai Semiconductor

HY628100A Series

128Kx8bit CMOS SRAM

DESCRIPTION

The HY628100A is a high speed, low power and
1M bit CMOS Static Random Access Memory
organized as 131,072 words by 8bit. The
HY628100A uses high performance CMOS
process technology and designed for high speed
low power circuit technology. It is particulary well
suited for used in high density low power system
application. This device has a data retention
mode that guarantees data to remain valid at a
minimum power supply voltage of 2.0V.

FEATURES

• Fully static operation and Tri-state output

• TTL compatible inputs and outputs

• Battery backup(L/LL-part)

- 2.0V(min) data retention

• Standard pin configuration

- 32pin 525mil SOP

- 32pin 8x20mm TSOP-I(Standard)

Product Voltage Speed Operation Standby Current(uA) Temperature

No (V) (ns) Current(mA) L LL

(°C)
HY628100A 5.0 55/70/85 10 1mA 100 20 0~70
Comment : 50ns is available with 30pF test load.

PIN CONNECTION

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

Vcc
A15

/WE
A13
A8
A9
A11
/OE
A10
/CS1
I/O8
I/O7
I/O6
I/O5
I/O4

NC
A16
A14
A12

A7
A6
A5
A4
A3
A2
A1

A0
I/O1
I/O2
I/O3

Vss

CS2

1
2
3
4
5
6
7
8
9

11
12
13
14
15
16

32
30

29
28
27
26
25
24

22
21
20
19
18
17

/OE
DQ8

DQ7
DQ6
DQ5
DQ4
Vss
DQ3

DQ1
A0
A1
A2
A3

A11

A9

A13
/WE
CS2

A15

Vcc

NC

A16

A12

A7
A6
A5
A4

/CS1

SOP TSOP-I(Standard)

PIN DESCRIPTION BLOCK DIAGRAM

Pin Name Pin Function

/CS1 Chip Select 1
CS2 Chip Select 2
/WE Write Enable
/OE Output Enable
A0 ~ A16 Address Input
I/O1 ~ I/O8 Data Input/Output
Vcc Power(5.0V)
Vss Ground

CS2

A16

COLUMN DECODER

A0

ROW DECODER

MEMORY ARRAY

1024x1024

SENSE AMP

OUTPUT BUFFER

I/O1

I/O8

ADD INPUT BUFFER

/CS1

/OE

/WE

WRITE DRIVER

CONTROL

LOGIC

HY628100A Series

Rev.05 /Feb.99

2

ORDERING INFORMATION

Part No. Speed Power Temp Package

HY628100AG 55/70/85 SOP
HY628100ALG 55/70/85 L-part SOP
HY628100ALLG 55/70/85 LL-part SOP
HY628100AT1 55/70/85 TSOP-I(Standard)
HY628100ALT1 55/70/85 L-part TSOP-I(Standard)
HY628100ALLT1 55/70/85 LL-part TSOP-I(Standard)
Comment : 50ns is available with 30pF test load.

ABSOLUTE MAXIMUM RATING (1)

Symbol Parameter Rating Unit

Vcc, VIN, VOUT Power Supply, Input/Output Voltage -0.5 to 7.0 V
TA Operating Temperature 0 to 70

°C

TSTG Storage Temperature -65 to 125

°C
PD Power Dissipation 1.0 W
IOUT Data Output Current 50 mA
TSOLDER Lead Soldering Temperature & Time

260 •10 °C•sec

Note

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is stress rating only and the functional operation of the device under these or
any other conditions above those indicated in the operation of this specification is not implied.
Exposure to the absolute maximum rating conditions for extended period may affect reliablity.

RECOMMENDED DC OPERATING CONDITION

TA=0°C to 700°C /-400°C to 85°C

Symbol Parameter Min. Typ. Max. Unit

Vcc Supply Voltage 4.5 5.0 5.5 V
Vss Ground 0 0 0 V
VIH Input High Voltage 2.2 - Vcc+0.5 V
VIL Input Low Voltage -0.5(1) - 0.8 V

Note :

1. VIL = -3.0V for pulse width less than 30ns

TRUTH TABLE

/CS1 CS2 /WE /OE MODE I/O OPERATION

H X X X Standby High-Z
X L X X High-Z

L H H H Output Disabled High-Z
L H H L Read Data Out
L H L X Write Data In

Note :

1. H=VIH, L=VIL, X=don't care

HY628100A Series

Rev.05 /Feb.99

3

DC ELECTRICAL CHARACTERISTICS

Vcc = 5.0V±10%, TA = 0°C to 70°C, unless otherwise specified

Symbol Parameter Test Condition Min. Typ. Max. Unit

ILI Input Leakage Current Vss < VIN < Vcc -1 - 1 uA
ILO Output Leakage Current Vss < VOUT < Vcc, /CS1 = VIH or

CS2 = VIL or /OE = VIH or /WE = VIL

-1 - 1 uA

Icc Operating Power Supply

Current

/CS1 = VIL, CS2 = VIH,
VIN = VIH or VIL, II/O = 0mA

- 5 10 mA

ICC1 Average Operating

Current

/CS1 = VIL CS2 = VIH,
Min Duty Cycle = 100%, II/O = 0mA

- 30 50 mA

ISB TTL Standby Current

(TTL Input)

/CS1 = VIH or CS2 = VIL - 1 2 mA

ISB1 Standby Current /CS1 > Vcc - 0.2V - - 1 mA

(CMOS Input) CS2 > 0.2V or L - 2 100 uA

CS2 > Vcc - 0.2V LL - 1 20 uA
VOL Output Low Voltage IOL = 2.1Ma - - 0.4 V
VOH Output High Voltage IOH = -1mA 2.4 - - V

Note : Typical values are at Vcc = 5.0V, TA = 25°C

AC CHARACTERISTICS

Vcc = 5.0V±10%, TA = 0°C to 70°C (Normal), unless otherwise specified

-55 -70 -85

Min. Max. Min. Max. Min Max.

1 TRC Read Cycle Time 55 - 70 - 85 - ns
2 tAA* Address Access Time - 55 - 70 - 85 ns
3 tACS* Chip Select Access Time - 55 - 70 - 85 ns
4 TOE Output Enable to Output Valid - 25 - 35 - 45 ns
5 TCLZ Chip Select to Output in Low Z 10 - 10 - 10 - ns
6 TOLZ Output Enable to Output in Low Z 5 - 5 - 5 - ns
7 tCHZ Chip Deselection to Output in High Z 0 20 0 25 0 30 ns
8 tOHZ Out Disable to Output in High Z 0 20 0 25 0 30 ns
9 tOH Output Hold from Address Change 10 - 10 - 10 - ns

10 tWC Write Cycle Time 55 - 70 - 85 - ns
11 tCW Chip Selection to End of Write 45 - 60 - 70 - ns
12 tAW Address Valid to End of Write 45 - 60 - 70 - ns
13 tAS Address Set-up Time 0 - 0 - 0 - ns
14 tWP Write Pulse Width 40 - 50 - 55 - ns
15 tWR Write Recovery Time 0 - 0 - 0 - ns
16 tWHZ Write to Output in High Z 0 20 0 25 0 30 ns
17 tDW Data to Write Time Overlap 25 - 30 - 35 - ns
18 tDH Data Hold from Write Time 0 - 0 - 0 - ns
19 tOW Output Active from End of Write 5 - 5 - 5 - ns

Comment : tAA* and tACS* can meet 50ns with 30pF test load.

READ CYCLE

WRITE CYCLE

Symbol

Parameter

#

Unit

HY628100A Series

Rev.05 /Feb.99

4

AC TEST CONDITIONS

TA = 0°C to 70°C (Normal), unless otherwise specified

PARAMETER Value

Input Pulse Level 0.8V to 2.4V
Input Rise and Fall Time 5ns
Input and Output Timing Reference Level 1.5V
Output Load CL = 100pF + 1TTL Load

CL* = 30pF + 1TTL Load
Comment
* : Test load is 30pF for 50ns

AC TEST LOADS

CL(1)

TTL

Note : Including jig and scope capacitance

CAPACITANCE

Temp = 25°C, f= 1.0MHz

Symbol Parameter Condition Max. Unit

CIN Input Capacitance VIN = 0V 6 pF
COUT Output Capacitance VI/O = 0V 8 pF

Note : These parameters are sampled and not 100% tested

HY628100A Series

Rev.05 /Feb.99

5

TIMING DIAGRAM

READ CYCLE 1

ADDR

OE

CS1

CS2

Data
Out

Data Valid

tRC

tACS

tCLZ

tOE

tOLZ

tAA

tOH

tOHZ

tCHZ

High-Z

Note(READ CYCLE):

1. tCHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are
not referenced to output voltage levels

2. At any given temperature and voltage condition, tCHZ max. is less than tCLZ min. both for a given
device and from device to device.

3. /WE is high for the read cycle.

READ CYCLE 2

tRC

tAA

Data ValidPrevious Data

tOH

tOH

ADDR

Data
Out

Note(READ CYCLE):

1. /WE is high for the read cycle.

2. Device is continuously selected /CS1 = VIL, CS2 = VIH.

3. /OE =VIL.

HY628100A Series

Rev.05 /Feb.99

6

WRITE CYCLE 1(/WE Controlled)

ADDR

CS1

CS2

Data
Out

Data Undefined

tWC

tDW

tOHZ

tAW

tOW

High-Z

WE

tCW

tWR

Data Valid

tDH

tWP

tAS

Data In

WRITE CYCLE 2 (/CS1 Controlled)

ADDR

CS1

CS2

Data
Out

Data Valid

tWC

tWP

tCLZ

tCW

tAW

tAS

tDH

High-Z

tWR

tWHZ

tDW

High-Z

High-Z

Data In

WE

HY628100A Series

Rev.05 /Feb.99

7

WRITE CYCLE 3 (CS2 Controlled)

ADDR

CS1

CS2

Data

Out

Data Valid

tWC

tWP

tCLZ

tCW

tAW

tAS

tDH

High-Z

tWR

tWHZ

tDW

High-Z

High-Z

Data In

WE

Notes(WRITE CYCLE):

1. A write occurs during the overlap of a low /CS1, CS2 and low /WE. A write begines at the latest transition
among /CS1 going low, CS2 going high and /WE going low: A write ends at the earliest transition among
/CS1 going high, CS2 low and /WE going high. tWP is measured from the beginning of write to the end of
write. .

2. tCW is measured from the later of /CS1 going low or CS2 going high to the end of write .

3. tAS is measured from the address valid to the beginning of write.

4. tWR is measured from the end of write to the address change. tWR is applied in case a write ends as
/CS1, or /WE going high, and tWR is applied in case a write ends at CS2 going low.

5. If /OE, CS2 and /WE are in the read mode during this period, the I/O pins are in the output low-Z state,
input of opposite phase of the output must not be applied because bus contention can occur.

6. If /CS1 goes low simultaneously with /WE going low, the outputs remain in high impedance state.

7. Dout is the read data of the new address.

8. When /CS1 is low and CS2 is high, I/O pins are in the output state. The input signals in the opposite
phase leading to the outputs should not be applied.

HY628100A Series

Rev.05 /Feb.99

8

DATA RETENTION ELECTRIC CHARACTERISTIC

SYM Parameter Test Condition Min Typ Max Unit

VDR Vcc for Data Retention /CS1 > Vcc - 0.2V 2.0 - - V

CS2 < 0.2V or
> Vcc - 0.2V,
Vss<VIN<Vcc

ICCDR Data Retention Current Vcc = 3.0V, /CS1>Vcc - 0.2V L - 2 50 uA

CS2< 0.2V or > Vcc - 0.2V, LL - 1 10 uA

Vss<VIN<Vcc
tCDR Chip Deselect to Data Retention Time 0 - - ns
tR Operating Recovery Time tRC(2) - - ns

Notes:

1. Typical values are under the condition of TA = 25°C.

2. tRC is read cycle time.

DATA RETENTION TIMING DIAGRAM 1

CS1

VDR

CS1>VCC-0.2V

tCDR

tR

VSS

VCC

4.5V

2.2V

DATA RETENTION MODE

DATA RETENTION TIMING DIAGRAM 2

0.4V

VDR

tCDR

tR

VSS

VCC

4.5V

CS2

DATA RETENTION MODE

CS2<0.2V

HY628100A Series

Rev.05 /Feb.99

9

RELIABILITY SPEC.

TEST MODE TEST SPEC.

ESD HBM > 2000V
MM > 250V
LATCH - UP < -100mA

> 100mA

PACKAGE INFORMATION

32pin 525mil Small Outline Package(G)

UNIT : INCH(mm)

0.444(11.278)

0.438(11.125)

0.564(14.326)

0.546(13.868)

0.810(20.574)

0.804(20.422)

0.109(2.769)

0.099(2.515)

0.011(0.279)

0.004(0.102)

0.020(0.508)

0.014(0.356)

0.050(1.27)BSC

0.0125(0.318)

0.0061(0.155)

0.0425(1.080)

0.0235(0.597)

0 deg
8 deg

32pin 8x20mm Thin Small Outline Package Standard(T1)

UNIT : INCH(mm)

0.319(8.103)

0.311(7.900)

0.728(18.491)

0.720(18.288)

0.792(20.117)

0.784(19.914)

0.025(0.64)

0.021(0.54)

0.008(0.21)

0.004(0.10)

0.020(0.50)
BSC

0.011(0.27)

0.041(1.05)

0.037(0.95)

0.006(0.15)

0.002(0.05)

#1

#32

#16

#17

0.007(0.17)