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HY62256B Series
/WE
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
/WE
OUTPUT BUFFER
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DataSheet
32Kx8bit CMOS SRAM
DESCRIPTION
FEATURES
The HY62256B is a high-speed, low power and
32,786 X 8-bits CMOS Static Random Access
Memory fabricated using Hyundai's high
performance CMOS process technology. It is
suitable for use in low voltage operation and
battery back-up application. This device has a
data retention mode that guarantees data to
remain valid at the minimum power supply
voltage of 2.0 volt.
• Fully static operation and Tri-state output
• TTL compatible inputs and outputs
• Low power consumption
• Battery backup(L/LL-part)
- 2.0V(min.) data retention
• Standard pin configuration
- 28 pin 600 mil PDIP
- 28 pin 330mil SOP
- 28 pin 8x13.4 mm TSOP-I
(Standard and Reversed)
Product Voltage Speed Operation Standby Current(uA) Temperature
No. (V) (ns) Current(mA) L LL
(°C)
HY62256B 5.0 55/70/85 8 1mA 100 25 0~70(Normal)
Note 1. Current value is max.
PIN CONNECTION
A14
1
A12
2
A7
3
A6
4
A5
5
A4
6
A3
7
A2
8
A1
9
A0
10
I/O1
11
I/O2
12
I/O3
13
14
Vss
PDIP SOP TSOP-I(Standard) TSOP-I(Reversed)
Vcc
28
27
26
25
24
23
22
21
20
19
18
17
16
15
/WE
A13
A8
A9
A11
/OE
A10
/CS
I/O8
I/O7
I/O6
I/O5
I/O4
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O1
I/O2
I/O3
Vss
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Vcc
28
/WE
27
26
25
24
23
22
21
20
19
18
17
16
15
A13
A8
A9
A11
/OE
A10
/CS
I/O8
I/O7
I/O6
I/O5
I/O4
/OE
A11
A13
Vcc
A14
A12
1
2
A9
3
A8
4
5
6
7
8
9
10
A7
11
A6
A5
12
13
A4
14
A3
A10
/CS
I/O8
I/O7
I/O6
I/O5
I/O4
Vss
I/O3
I/O2
I/O1
A0
A1
A2
A12
A14
Vcc
A13
A11
/OE
A3
14
A4
13
A5
12
A6
11
A7
10
9
8
7
6
5
4
A8
A9
3
2
1
15
16
17
18
19
20
21
22
23
24
25
26
27
28
28
27
26
25
24
23
22
21
20
19
18
17
16
15
PIN DESCRIPTION BLOCK DIAGRAM
A2
A1
A0
Vss
/CS
A10
Pin Name Pin Function
A0
/CS Chip Select
/WE Write Enable
/OE Output Enable
A0 ~ A14 Address Inputs
I/O1 ~ I/O8 Data Input/Output
Vcc
Power(+5.0V)
Vss Ground
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
A14
/CS
/OE
/WE
responsibility for use of circuits described. No patent licenses are implied.
Rev.04 /Jan.99 Hyundai Semiconductor
ADD INPUT BUFFER
CONTROL
ROW DECODER
MEMORY ARRAY
COLUMN DECODER
LOGIC
I/O1
SENSE AMP
512x512
I/O8
WRITE DRIVER
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HY62256B Series
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ORDERING INFORMATION
Part No. Speed Power Package
HY62256BP 55/70/85 PDIP
HY62256BLP 55/70/85 L-part PDIP
HY62256BLLP 55/70/85 LL-part PDIP
HY62256BJ 55/70/85 SOP
HY62256BLJ 55/70/85 L-part SOP
HY62256BLLJ 55/70/85 LL-part SOP
HY62256BT1 55/70/85 TSOP-I Standard
HY62256BLT1 55/70/85 L-part TSOP-I Standard
HY62256BLLT1 55/70/85 LL-part TSOP-I Standard
HY62256BR1 55/70/85 TSOP-I Reversed
HY62256BLR1 55/70/85 L-part TSOP-I Reversed
HY62256BLLR1 55/70/85 LL-part TSOP-I Reversed
ABSOLUTE MAXIMUM RATING (1)
Symbol Parameter Rating Unit
Vcc, VIN, VOUT Power Supply, Input/Output Voltage -0.5 to 7.0 V
TA Operating Temperature 0 to 70
TSTG Storage Temperature -65 to 150
PD Power Dissipation 1.0 W
IOUT Data Output Current 50 mA
TSOLDER Lead Soldering Temperature & Time
260 •10 °C•sec
°C
°C
Note
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is stress rating only and the functional operation of the device under these or
any other conditions above those indicated in the operation of this specification is not implied.
Exposure to the absolute maximum rating conditions for extended period may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
Symbol Parameter Min. Typ. Max. Unit
Vcc Power Supply Voltage 4.5 5.0 5.5 V
Vss Ground 0 0 0 V
VIH Input High Voltage 2.2 - Vcc+0.5 V
VIL Input Low Voltage -0.5(1) - 0.8 V
Note
1. VIL = -3.0V for pulse width less than 30ns
TRUTH TABLE
/CS /WE /OE Mode I/O Operation
H X X Standby High-Z
L H H Output Disabled High-Z
L H L Read Data Out
L L X Write Data In
Note
1. H=VIH, L=VIL, X=Don't Care
Rev.04 /Jan.99
2
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HY62256B Series
READ CYCLE
WRITE CYCLE
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DC CHARACTERISTICS
Vcc = 5V ±10%, TA = 0°C to 70°C (Normal), unless otherwise specified.
Symbol Parameter Test Condition Min. Typ. Max. Unit
ILI Input Leakage Current Vss < VIN < Vcc -1 - 1 uA
ILO Output Leakage Current Vss < VOUT < Vcc, /CS = VIH or
/OE = VIH or /WE = VIL
Icc Operating Power Supply
Current
ICC1 Average Operating Current /CS = VIL,
ISB TTL Standby Current
(TTL Inputs)
ISB1 CMOS Standby Current /CS > Vcc - 0.2V - - 1 mA
(CMOS Inputs) L - 2 100 uA
VOL Output Low Voltage IOL = 2.1mA - - 0.4 V
VOH Output High Voltage IOH = -1mA 2.4 - - V
Note : Typical values are at Vcc =5.0V, TA = 25°C
/CS = VIL,
VIN = VIH or VIL, II/O = 0mA
Min. Duty Cycle = 100%, II/O = 0mA
/CS= VIH - 0.4 1 mA
LL - 1.5 25 uA
-1 - 1 uA
- 5 8 mA
- 30 60 mA
AC CHARACTERISTICS(I)
Vcc = 5V ±10%, TA = 0°C to 70°C (Normal) unless otherwise specified.
Symbol
#
1 tRC Read Cycle Time 55 - 70 - 85 - ns
2 tAA Address Access Time - 55 - 70 - 85 ns
3 tACS Chip Select Access Time - 55 - 70 - 85 ns
4 tOE Output Enable to Output Valid - 25 - 35 - 45 ns
5 tCLZ Chip Select to Output in Low Z 5 - 5 - 5 - ns
6 tOLZ Output Enable to Output in Low Z 5 - 5 - 5 - ns
7 tCHZ Chip Disable to Output in High Z 0 20 0 30 0 30 ns
8 tOHZ Out Disable to Output in High Z 0 20 0 30 0 30 ns
9 tOH Output Hold from Address Change 5 - 5 - 5 - ns
10 tWC Write Cycle Time 55 - 70 - 85 - ns
11 tCW Chip Selection to End of Write 50 - 65 - 75 - ns
12 tAW Address Valid to End of Write 50 - 65 - 75 - ns
13 tAS Address Set-up Time 0 - 0 - 0 - ns
14 tWP Write Pulse Width 40 - 50 - 60 - ns
15 tWR Write Recovery Time 0 - 0 - 0 - ns
16 tWHZ Write to Output in High Z 0 20 0 30 0 30 ns
17 tDW Data to Write Time Overlap 25 - 35 - 40 - ns
18 tDH Data Hold from Write Time 0 - 0 - 0 - ns
19 tOW Output Active from End of Write 5 - 5 - 5 - ns
Parameter
-55 -70 -85
Min. Max. Min. Max. Min Max.
Unit
Rev.04 /Jan.99
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HY62256B Series
ADDR
OE
Out
Data Valid
tRC
tACS
tCLZ
tOE
tAA
tOHZ
tCHZ
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AC TEST CONDITIONS
TA = 0°C to 70°C (Normal) / -40°C to 85°C (E.T.) unless otherwise specified.
Parameter Value
Input Pulse Level 0.8V to 2.4V
Input Rise and Fall Time 5ns
Input and Output Timing Reference Levels 1.5V
Output Load CL = 100pF + 1TTL Load
AC TEST LOADS
TTL
CL(1)
Note : Including jig and scope capacitance
CAPACITANCE
TA = 25°C, f = 1.0MHz
Symbol Parameter Condition Max. Unit
CIN Input Capacitance VIN = 0V 6 pF
CI/O Input /Output Capacitance VI/O = 0V 8 pF
Note : These parameters are sampled and not 100% tested
TIMING DIAGRAM
READ CYCLE 1
CS
Data
Rev.04 /Jan.99
High-Z
tOLZ
tOH
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HY62256B Series
tRC
tAA
OE
tWC
tOHZ
WE
tWP
Data In
tWR
tCW
tAW
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Note(READ CYCLE):
1. tCHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and arenot
referenced to output voltage levels.
2. At any given temperature and voltage condition, tCHZ max. is less than tCLZ min. both for a given device
and from device to device.
3. /WE is high for the read cycle.
READ CYCLE 2
ADDR
tOH
Data
Out
Note(READ CYCLE):
1. /WE is high for the read cycle.
2. Device is continuously selected /CS= VIL.
3. /OE =VIL.
WRITE CYCLE 1(/OE Clocked)
ADDR
CS
tOH
Data ValidPrevious Data
Data
Out
Rev.04 /Jan.99
tAS
tDW
tDH
Data Valid
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WRITE CYCLE 2 (/OE Low Fixed)
tWHZ
tDH
tWP
tAS
tWR
tCW
tAW
(8)
tOW
CS
tWC
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DataSheet
ADDR
WE
HY62256B Series
tDW
Data In
Data
Out
Data Valid
(7)
Notes(WRITE CYCLE):
1. A write occurs during the overlap of a low /CS and a low /WE. A write begins at the latest transition
among /CS going low and /WE going low: A write ends at the earliest transition among /CS going high
and /WE going high. tWP is measured from the beginning of write to the end of write.
2. tCW is measured from the later of /CS going low to the end of write .
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end of write to the address change. tWR is applied in case a write ends as /CS,
or /WE going high.
5. If /OE and /WE are in the read mode during this period, and the I/O pins are in the output low-Z state,
input of opposite phase of the output must not be applied because bus contention can occur.
6. If /CS goes low simultaneously with /WE going low, or after /WE going low, the outputs remain in high
impedance state.
7. DOUT is the same phase of the latest written data in this write cycle.
8. DOUT is the read data of the new address.
DATA RETENTION CHARACTERISTIC
TA=0°C to 70°C (Normal)
Symbol Parameter Test Condition Min Typ Max Unit
VDR Vcc for Data Retention CS>Vcc-0.2V, 2.0 - - V
ICCDR Data Retention Current Vcc=3.0V, L - 1 50 uA
tCDR Chip Deselect to Data Retention Time See Data Retention 0 - - ns
tR Operating Recovery Time Timing Diagram tRC(2) - - ns
Notes
1. Typical values are under the condition of TA = 25°C.
2. tRC is read cycle time.
Rev.04 /Jan.99
Vss<VIN<Vcc
/CS>Vcc - 0.2V, LL - 1 15 uA
Vss<VIN<Vcc
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DATA RETENTION TIMING DIAGRAM
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DataSheet
HY62256B Series
DATA RETENTION MODE
VCC
4.5V
2.2V
VDR
CS
VSS
tCDR
RELIABILITY SPEC.
TEST MODE TEST SPEC.
ESD HBM > 2000V
MM > 250V
LATCH - UP < -100mA
> 100mA
tR
CS>VCC-0.2V
PACKAGE INFORMATION
28pin 600mil Dual In-Line Package(P)
•
1.467(37.262)
1.447(36.754)
0.090(2.286)
0.070(1.778)
0.100(2.54)BSC
0.065(1.650)
0.050(1.270)
0.021(0.533)
0.015(0.381)
0.155(3.937)
0.145(3.683)
0.035(0.889)
0.020(0.508)
0.140(3.556)
0.120(3.048)
UNIT : INCH(mm)
0.600(15.240)BSC
0.550(13.970)
0.530(13.462)
3 deg
11 deg
0.014(0.356)
0.008(0.200)
MAX.
MIN.
Rev.04 /Jan.99
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28pin 330mil Small Outline Package(J)
0.008(0.20)
0.002(0.05)
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DataSheet
HY62256B Series
0.346(8.788)
0.338(8.585)
0.728(18.491)
0.720(18.288)
0.050(1.270)BSC 0.020(0.508)
0.014(0.356)
0.480(12.192)
0.460(11.684)
0.110(2.794)
0.094(2.388)
0.014(0.356)
0.002(0.051)
UNIT : INCH(mm)
0.050(1.270)
0.030(0.762)
28pin 8x13.4mm Thin Small Outline Package Standard(T1)
MAX
MIN.
0.012(0.305)
0.008(0.203)
0.027(0.7)
0.012(0.3)
0.468(11.9)
0.460(11.7)
0.536(13.6)
0.520(13.2)
0.008(0.2)
0.004(0.1)
UNIT : INCH(mm)
0.319(8.1)
0.311(7.9)
0.022(0.55 BSC)
MAX.
MIN.
0.040(1.02)
0.036(0.91)
Rev.04 /Jan.99
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HY62256B Series
0.008(0.20)
0.002(0.05)
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DataSheet
28pin 8x13.4mm Thin Small Outline Package Reversed(R1)
0.027(0.7)
0.012(0.3)
0.468(11.9)
0.460(11.7)
0.536(13.6)
0.520(13.2)
0.008(0.2)
0.004(0.1)
UNIT : INCH(mm)
0.319(8.1)
0.311(7.9)
0.022(0.55 BSC)
MAX.
MIN.
0.040(1.02)
0.036(0.91)
Rev.04 /Jan.99
9
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