Datasheet HY62256ALLP-70, HY62256ALLP-85, HY62256ALLR1-55, HY62256ALLR1-70, HY62256ALLR1-85 Datasheet (HEI)

HY62256A-(I) Series

32Kx8bit CMOS SRAM

Description Features

The
HY62256A/HY62256A-I
is a high-speed, low
power and 32,786 x 8-bits
CMOS Static Random
Access Memory
fabricated using
Hyundai's high
performance CMOS
process technology. The
HY62256A/HY62256A-I
has a data retention mode
that guarantees data to
remain valid at the
minimum power supply
voltage of 2.0 volt. Using
the CMOS technology,
supply voltages from 2.0
to 5.5 volt has little effect
on supply current in the
data retention mode. The
HY62256A/HY62256A-I
is suitable for use in low
voltage operation and
battery back-up
application.

·

Fully static operation and
Tri-state outputs

·

TTL compatible inputs
and outputs

·

Low power consumption

-2.0V(min.) data
retention

·

Standard pin
configuration

-28 pin 600 mil PDIP

-28 pin 330 mil SOP

-28 pin 8x13.4 mm
TSOP-1
(standard and reversed)

1 of 2 22/10/97 12:30

Data Sheet-sram/62256ald1 http://www.hea.com/hean2/sram/62256ald1.htm

Product No.

Voltage

(V)

Speed

(ns)

Operation

Current(mA)

Standby

Current(uA)

Temperature

(°C)

L LL
HY62256A 5.0 55/70/85 50 1mA 100 25 0-70(Normal)
HY62256A-I 5.0 55/70/85 50 1mA 100 - -40-85(E.T.)
Note

1. E T. Extended Temperature, Normal: Normal Temperature

2. Current value is max.

Features | Pins | Ratings | Timing | Package | Ordering

3101 North First Street, San Jose, CA 95134

Phone: [phone] URL: http://www.hea.com/

SRAM Data Sheets | Memory Products | email: [email protected]

Copyright © 1997 Hyundai Electronics America.

2 of 2 22/10/97 12:30

Data Sheet-sram/62256ald1 http://www.hea.com/hean2/sram/62256ald1.htm

HYUNDAI ELECTRONICS AMERICA
HY62256A-(I) Series
32Kx8bit CMOS SRAM

PIN INFORMATION

PIN CONNECTION

BLOCK DIAGRAM

PIN DESCRIPTION

Pin Name Pin Function

/CS Chip Select
/WE Write Enable
/OE Output Enable
A0-A14 Address Inputs
I/O1-I/O8 Data Input/Output
Vcc Power(+5.0V)
Vss Ground

Features | Pins | Ratings | Timing | Package | Ordering

3101 North First Street, San Jose, CA 95134

1 of 2 22/10/97 12:32

-sram/62256alp1 http://www.hea.com/hean2/sram/62256alp1.htm

Phone: [phone] URL: http://www.hea.com/

SRAM Data Sheets | Memory Products | email: [email protected]

Copyright © 1997 Hyundai Electronics America.

2 of 2 22/10/97 12:32

-sram/62256alp1 http://www.hea.com/hean2/sram/62256alp1.htm

HYUNDAI ELECTRONICS AMERICA
HY62256A-(I) Series
32Kx8bit CMOS SRAM

RATINGS INFORMATION

ABSOLUTE MAXIMUM RATING (1)

Symbol Parameter Rating Unit Remark

VCC VIN
VOUT

Power Supply Input/Output
Voltage

-0.5 to 7.0 V

TA Operating Temperature

0 to 70 °C HY62256A

-40 to 85 °C HY62256A-I
TSTG Storage Temperature -65 to 150 °C
PD Power Dissipation 1.0 W
IOUT Data OutPut Current 50 mA

TSOLDER

Lead Soldering Temperature
& Time

260 /10 °C / sec

Note

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is stress rating only and the
functional operation of the device under these or any other conditions above
those indicated in the operation of this specification is not implied. Exposure to
the absolute maximum rating conditions for extended period may affect
reliability.

RECOMMENDED DC OPERATING CONDITIONS

TA=0°C to 70°C / TA= -40°C to 85°C (E.T.)

Symbol Parameter Min Typ Max Unit

VCC Power Supply Voltage 4.5 5.0 5.5 V
VIH Input High Voltage 2.2 - VCC+0.5 V
VIL Input Low Voltage -0.5(1) - 0.8 V
Note

1. VIL = -3.0V for pulse width less than 30ns

1 of 4 22/10/97 12:33

-sram/62256ala1 http://www.hea.com/hean2/sram/62256ala1.htm

TRUTH TABLE

/CS /WE /OE MODE I/O OPERATION

H X X Standby High-Z
L H H Output Disabled High-Z
L H L Read Data Out
L L X Write Data In
Note:

1. H=VIH, L=VIL, X=Don't Care

Features | Pins | Ratings | Timing | Package | Ordering

DC CHARACTERISTICS
Vcc = 5V ?% TA = 0°C to 70°C (Normal) / -40°C to 85°C (E.T.) unless otherwise

specified

Symbol Parameter Test Condition Min Typ Max Unit

ILI Input Leakage Current Vss <= VIN <= Vcc -1 - 1 uA

ILO Output Leakage Current

Vss <= VOUT <= Vcc
/CS=VIH or
/OE=VIH or /WE =
VIL

-1 - 1 uA

Icc

Operating Power Supply
Current

/CS= VIL,
VIN=VIH or VIL, II/O=
0mA

- 30 50 mA

Icc1

Average Operating
Current

/CS = VIL
Min. Duty Cycle =
100%, II/O =0mA

- 40 70 mA

ISB

TTL Standby Current
(TTL Inputs)

/CS = VIH VIN = VIH
or VIL

- 0.4 2 mA

ISB1

CMOS
Standby
Current
(CMOS
Input)

HY62256A

/CS >= Vcc-

0.2V
VIN <= 0.2V or
VIN >=
VCC-0.2V

- - 1 mA
L - 2 100 uA
LL - 1 25 uA

HY62256A-I

- - 1 mA
L - 2 100 uA

VOL Output Low Voltage IOL= 2.1 mA - - 0.4 V
VOH Output High Voltage IOH = 1mA 2.4 - - V
Note: Typical values are at Vcc = 5.0V TA = 25°C

2 of 4 22/10/97 12:33

-sram/62256ala1 http://www.hea.com/hean2/sram/62256ala1.htm

AC CHARACTERISTICS

Vcc = 5V(±)10%, TA = 0°C to 70°C (Normal)/ -40°C to 85°C (E.T.) unless otherwise
specified.

# Symbol Parameter

-55 -70 -85
Unit

Min. Max. Min. Max. Min. Max.
READ CYCLE
1 tRC Read Cycle Time 55 - 70 - 85 - ns
2 tAA Address Access Time - 55 - 70 - 85 ns
3 tACS Chip Select Access Time - 55 - 70 - 85 ns

4 tOE

Output Enable to Output
Valid

- 30 - 35 - 45 ns

5 tCLZ

Chip Select to Output in
Low Z

5 - 5 - 5 - ns

6 tOLZ

Output Enable to Output in
Low Z

5 - 5 - 5 - ns

7 tCHZ

Chip Deselection to Output
in High Z

0 20 0 30 0 30 ns

8 tOHZ

Out Disable to Output in
High Z

0 20 0 30 0 30 ns

9 tOH

Output Hold from Address
Change

5 - 5 - 5 - ns
WRITE CYCLE

10 tWC Write Cycle Time 55 - 70 - 85 - ns
11 tCW

Chip Selection to End of
Write

50 - 65 - 75 - ns

12 tAW

Address Valid to End of
Write

50 - 65 - 75 - ns
13 tAS Address Set-up Time 0 - 0 - 0 - ns

14 tWP Write Pulse Width 40 - 50 - 55 - ns
15 tWR Write Recovery Time 0 - 0 - 0 - ns
16 tWHZ Write to Output in High Z 0 20 0 30 0 30 ns
17 tDW Data to Write Time Overlap 25 - 35 - 40 - ns
18 tDH Data Hold from Write Time 0 - 0 - 0 - ns

19 tOW

Output Active from End of
Write

5 - 5 - 5 - ns

AC TEST CONDITIONS

TA = 0°C to 70°C (Normal) / -40°C to 85°C (E.T.) unless otherwise specified.

PARAMETER VALUE

Input Pulse Level 0.8V to 2.4V
Input Rise and Fall Time 5ns
Input and Output Timing Reference Levels 1.5V

Output Load

70/85/100ns CL = 100pF + 1TTL Load
55ns CL = 50pF + 1TTL Load

3 of 4 22/10/97 12:33

-sram/62256ala1 http://www.hea.com/hean2/sram/62256ala1.htm

AC TEST LOADS

Note: Including jig and scope capacitance

CAPACITANCE

TAA= 25 °C, f = 1.0MHz

Symbol Parameter Condition Max Unit

CIN Input Capacitance VIN = 0V 6 pF
CI/O Input/Output Capacitance VI/O= 0V 8 pF
Note: These parameters are sampled and not 100% tested

Features | Pins | Ratings | Timing | Package | Ordering

3101 North First Street, San Jose, CA 95134

Phone: [phone] URL: http://www.hea.com/

SRAM Data Sheets | Memory Products | email: [email protected]

Copyright © 1997 Hyundai Electronics America.

4 of 4 22/10/97 12:33

-sram/62256ala1 http://www.hea.com/hean2/sram/62256ala1.htm

HYUNDAI ELECTRONICS AMERICA
HY62256A-I
32K x 8bit CMOS SRAM

TIMING INFORMATION

TIMING DIAGRAM

READ CYCLE 1

Note (READ CYCLE):

1. tCHZ and tOHZ are defined as the time at which the outputs achieve the open
circuit conditions and are not referenced to output voltage levels.

2. At any given temperature and voltage condition, tCHZ max. is less than tCLZ min.
both for a given device and from device to device.

3. /WE is high for the read cycle.

READ CYCLE 2

Note (READ CYCLE):

1. /WE is high for the read cycle.

2. Device is continuously selected /CS= VIL.

3. /OE =VIL.

WRITE CYCLE 1 (/OE Clocked)

1 of 3 22/10/97 12:35

-sram/62256alt1 http://www.hea.com/hean2/sram/62256alt1.htm

WRITE CYCLE 2 (/OE Low Fixed)

Notes (WRlTE CYCLE):

1. A write occurs during the overlap of a low /CS and a low /WE. A write begins at
the latest transition among /CS going low and /WE going low: A write ends at
the earliest transition among /CS going high and /WE going high. tWP is
measured from the beginning of write to the end of write.

2. tcw is measured from the later of /CS going low to the end of write .

3. tAS is measured from the address valid to the beginning of write.

4. tWR is measured from the end of write to the address change. tWR is applied in
case a write ends as /CS, or /WE going high.

5. If /OE and /WE are in the read mode during this period, and the I/O pins are in
the output low-Z state, input of opposite phase of the output must not be applied
because bus contention can occur.

6. If /CS goes low simultaneously with /WE going low, or after /WE going low,
the outputs remain in high impedance state.

7. DOUT is the same phase of latest written data in this write cycle.

8. DOUT is the read data of the new address.

2 of 3 22/10/97 12:35

-sram/62256alt1 http://www.hea.com/hean2/sram/62256alt1.htm

DATA RETENTION CHARACTERISTIC

TA= 0°C to 70°C (normal) /-40°C to 85°C (E.T.)

Symbol Parameter Test Condition Min Typ Max Unit

VDR Vcc for Data Re! ention

/CS >= Vcc-0.2V
Vss <= VIN <=
Vcc

2 - - V

ICCDR

Data
Retention
Current

HY62256A

Vcc = 3.0V
/CS >= Vcc

-0.2V
Vss <= VIN
<= Vcc

L - 1 50 uA
LL - 1 15(2) uA

HY62256A-1 L - 1 50 uA

tCDR

Chip Disable to Data Retention
Time

See Data
Retention Timing
Diagram

0 - - ns

tR Operating Recovery Time tRC(3) - - ns
Notes

1. Typical values are under the condition of TA = 25°C

2. 3uA max. at TA= 0°C to 40°C

3. tRC is read cycle time.

Data Retention Timing Diagram

RELIABILITY SPEC.

TEST MODE TEST SPEC.

ESD

HBM
MM

>= 2000V
>= 250V

LATCH-UP

<= -100mA
>= 100mA

Features | Pins | Ratings | Timing | Package | Ordering

3101 North First Street, San Jose, CA 95134

Phone: [phone] URL: http://www.hea.com/

SRAM Data Sheets

|

Memory Products

|

email: [email protected]

Copyright © 1997 Hyundai Electronics America.

3 of 3 22/10/97 12:35

-sram/62256alt1 http://www.hea.com/hean2/sram/62256alt1.htm

HYUNDAI ELECTRONICS AMERICA
HY62256A-(I) Series
32Kx8bit CMOS SRAM

PACKAGE INFORMATION

28pin 600mil Dual In-Line Package(P)

28pin 330mil Small Outline Package(J)

28pin 8X13.4mm Thin Small Outline Package Standard(T1)

1 of 2 22/10/97 12:37

-sram/62256alpk1 http://www.hea.com/hean2/sram/62256alpk1.htm

28pin 8X13.4mm Thin Small Outline Package SReversed(R1)

Features | Pins | Ratings | Timing | Package | Ordering

3101 North First Street, San Jose, CA 95134

Phone: [phone] URL: http://www.hea.com/

SRAM Data Sheets | Memory Products | email: [email protected]

Copyright © 1997 Hyundai Electronics America.

2 of 2 22/10/97 12:37

-sram/62256alpk1 http://www.hea.com/hean2/sram/62256alpk1.htm

HYUNDAI ELECTRONICS AMERICA
HY62256A-(I) Series
32Kx8bit CMOS SRAM

ORDERING INFORMATION

Part No. Speed Power Temp. Package

HY62256AP 55/70/85 PDIP
HY62256ALP 55/70/85 L-part PDIP
HY62256ALLP 55/70/85 LL-part PDIP
HY62256AJ 55/70/85 SOP
HY62256ALJ 55/70/85 L-part SOP
HY62256ALLJ 55/70/85 LL-part SOP
HY62256AT1 55/70/85 TSOP-I Standard
HY62256ALT1 55/70/85 L-part TSOP-I Standard
HY62256ALLT1 55/70/85 LL-part TSOP-I Standard
HY62256AR1 55/70/85 TSOP-I Reversed
HY62256ALR1 55/70/85 L-part TSOP-I Reversed
HY62256ALLR1 55/70/85 LL-part TSOP-I Reversed
HY62256AP-I 55/70/85 E.T. PDIP
HY62256ALP-I 55/70/85 L-part E.T. PDIP
HY62256AJ-I 55/70/85 E.T. SOP
HY62256ALJ-I 55/70/85 L-part E.T. SOP
HY62256AT1-I 55/70/85 E .T. TSOP-I
HY62256ALT1-I 55/70/85 L-part E.T. TSOP-I
HY62256AR2-I 55/70/85 E.T. TSOP-I Reversed
HY62256ALR2-I 55/70/85 L-part E.T. TSOP-I Reversed

Features | Pins | Ratings | Timing | Package | Ordering

3101 North First Street, San Jose, CA 95134

Phone: [phone] URL: http://www.hea.com/

SRAM Data Sheets | Memory Products | email: [email protected]

Copyright © 1997 Hyundai Electronics America.

1 of 1 22/10/97 12:38

-sram/62256alo1 http://www.hea.com/hean2/sram/62256alo1.htm