Datasheet HV9925, HV9925SG-G Datasheet (Supertex)

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Page 1

Programmable-Current LED Lamp Driver IC

with PWM Dimming

HV9925

Features

Programmable Output Current to 50mA

►

PWM Dimming / Enable

►

Universal 85-264VAC Operation

►

Fixed OFF-Time Buck Converter

►

Internal 500V Power MOSFET

►

Over Temperature Protection with Hysteresis

►

Applications

Decorative Lighting

►

Low Power Lighting Fixtures

►

Typical Application Circuit

General Description

The HV9925 is a pulse width modulated (PWM) high-efﬁ ciency LED driver control IC with PWM dimming capabilities. It allows efﬁ cient operation of high brightness LED strings from voltage sources ranging up to 400VDC. The HV9925 includes an internal high-voltage switching MOSFET controlled with a ﬁ xed off-time T driven at constant current, thus providing constant light output and enhanced reliability. Selecting a value of a current sense resistor can externally program the output LED current of the HV9925.

The peak current control scheme provides good regulation of the output current throughout the universal AC line voltage range of 85VAC to 264VAC or DC input voltage of 20V to 400V. The HV9925 is designed with a built in thermal shutdown to prevent excessive power dissipation in the IC.

of approximately 10µs. The LED string is

OFF

Enable

Drain

PWMD

Drain

HV9925

SENSE

GND

Page 2

HV9925

Ordering Information

DEVICE

HV9925 HV9925SG-G

-G indicates package is RoHS compliant (‘Green’)

Package Options

8-Pin SOIC w/ Heat Slug

Absolute Maximum Ratings*

Parameter Value

Supply voltage, V

PWMD, R

SENSE

Supply current, I

voltage -0.3 to +10V

Operating ambient temperature range -40°C to +85°C

Operating junction temperature range -40°C to +125°C

Storage temperature range -65°C to +150°C

Power dissipation @ 25°C 800mW**

All voltages referenced to GND pin.

**The power dissipation is given for the standard minimum pad without a heat slug, and based on R case and case-to-ambient thermal resistance, where the latter is determined by the user’s board design. The junction-to-ambient thermal resistance is R copper, and R

= 105°C/W when the part is mounted on a 0.04 in2 pad of 1 oz

θJA

= 60°C/W when mounted on a 1 in2 pad of 1 oz copper.

θJA

=125°C/W. R

θJA

is the sum of the junction-to-

θJA

-0.3 to +10V

+5mA

Pin Conﬁ guration

RSENSE

GND

PWMD

VDD

Drain

HV9925

(top view)

(Heat Slug Potential is at ground)

Pin Description

Pin # Function Description

Source terminal of the output

SENSE

2 GND Common connection for all circuits

3 PWMD PWM Dimming input to the IC

6,7,8 Drain

switching MOSFET provided for current sense resistor connection

Power supply pin for internal control circuits. Bypass this pin with a 0.1uF low impedance capacitor.

Drain terminal of the output switching MOSFET and a linear regulator input

Electrical Characteristics

(The * denotes the speciﬁ cations which apply over the full operating temperature range of -40°C < TA < +85°C, otherwise the speciﬁ cations are at TA = 25°C. V

Symbol Parameter Min Typ Max Units Conditions

UVLO

ΔV

UVLO

Output (DRAIN)

DRAIN

SAT

Current Sense Comparator

BLANK

ON(MIN)

= 100V, unless otherwise noted)

DRAIN

VDD regulator output - 7.5 - V --

VDD undervoltage threshold 5.0 - - V --

VDD undervoltage lockout hysteresis - 200 - mV --

Operating supply current - 300 500 μA V

Breakdown voltage 500 - - V * --

supply voltage 20 - - V --

DRAIN

ON resistance - 100 200 Ω I

Output capacitance - 1.0 5.0 pF V

DRAIN saturation current 100 150 - mA --

Threshold voltage 0.44 0.47 0.50 V --

Leading edge blanking delay 200 300 400 ns * --

Minimum ON time - - 650 ns --

DD(EXT)

DRAIN

= 8.5V

= 50mA

= 400V

Page 3

Electrical Characteristics (cont.)

Symbol Parameter Min Typ Max Units Conditions

OFF-Time Generator

OFF

OFF time 8.0 10.5 13 μs --

PWM Dimming

PWMD,HI

PWMD,LO

PWMD

PWMD input high voltage 2.0 - - V * --

PWMD input low voltage - - 0.8 V * --

PWMD pull down resistance 100 200 300 kΩ V

PWMD

= 5V

Thermal Shutdown

HYST

Over temperature trip limit - 140 - °C --

Temperature hysteresis - 60 - °C --

Functional Block Diagram

HV9925

PWMD

0.5V

HV9925

OFF

= 10μs

= 300ns

BLANK

DRAINGND

REG

Over Temp.

SENSE

Page 4

HV9925

Typical Performance Characteristics (T

Threshold Voltage VTH vs Temperature T

-40 -15 10 35 60 85 110

Current Sense Threshold, V

0.485

0.480

0.475

0.470

0.465

0.460

Junction Temperature, °C

13.0

12.5

12.0

11.5

OFF Time T

vs Temperature T

OFF

= 25OC unless otherwise noted)

ON Resistance R

-40 -15 10 35 60 85 110

Output Capacitance C

ON Resistance, Ohm

200

180

160

140

120

100

1000

100

vs Temperature T

Junction Temperature, °C

vs V

DRAIN

11.0

10.5

OFF Ti m e, μs

10.0

9.5

9.0

-40 -15 10 35 60 85 110

Junction Temperature, °C

DRAIN Breakdown Voltage BV vs T

-40 -15 10 35 60 85 110

DRAIN Breakdown Voltage, V

580

570

560

550

540

530

520

510

500

490

Junction Tem perature , °C

DRAIN Capacitance, pF

010203040

DRAIN Volta ge, V

180

160

140

120

100

DRAIN Current, mA

Output Characteristics I

TJ = 25OC

= 125OC

0 10203040

DRAIN

vs V

DRAIN

DRAIN V o lt age , V

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Functional Description

HV9925

The HV9925 is a PWM peak current control IC for driving a buck converter topology in continuous conduction mode (CCM). The HV9925 controls the output current (rather than output voltage) of the converter that can be programmed by a single external resistor (R

), for the purpose of driving a

SENSE

string of light emitting diodes (LED). An external enable input (PWMD) is provided that can be utilized for PWM dimming of an LED string. The typical rising and falling edge transitions of the LED current when using the PWM dimming feature of the HV9925 are shown in Fig. 6 and Fig. 7.

When the input voltage of 20 to 400V appears at the DRAIN pin, the internal linear regulator seeks to maintain a voltage of 7.5VDC at the VDD pin. Until this voltage exceeds the internally programmed under-voltage threshold, no output switching occurs. When the threshold is exceeded, the integrated high-voltage switch turns on, pulling the DRAIN low. A 200mV hysteresis is incorporated with the undervoltage comparator to prevent oscillation.

When the voltage at R

exceeds 0.47V, the switch turns

SENSE

off and the DRAIN output becomes high impedance. At the same time, a one-shot circuit is activated that determines the off-time of the switch (10µs typ.).

A “blanking” delay of 300ns is provided upon the turn-on of the switch that prevents false triggering of the current sense comparator due to the leading edge spike caused by circuit parasitics.

Application Information

Selecting L1 and D1

variation. Therefore, the output current will remain unaffected by the varying input voltage.

Adding a ﬁ lter capacitor across the LED string can reduce the output current ripple even further, thus permitting a reduced value of L1. However, one must keep in mind that the peak-to-average current error is affected by the variation of T

. Therefore, the initial output current accuracy might

OFF

be sacriﬁ ced at large ripple current in L1.

Another important aspect of designing an LED driver with HV9925 is related to certain parasitic elements of the circuit, including distributed coil capacitance of L1, junction capacitance, and reverse recovery of the rectiﬁ er diode D1, capacitance of the printed circuit board traces C capacitance C

of the controller itself. These parasitic

DRAIN

and output

PCB

elements affect the efﬁ ciency of the switching converter and could potentially cause false triggering of the current sense comparator if not properly managed. Minimizing these parasitics is essential for efﬁ cient and reliable operation of HV9925.

Coil capacitance of inductors is typically provided in the manufacturer’s data books either directly or in terms of the self-resonant frequency (SRF).

SRF L C

=⋅12/( )π

where L is the inductance value, and CL is the coil capacitance. Charging and discharging this capacitance every switching cycle causes high-current spikes in the LED string. Therefore, connecting a small capacitor CO (~10nF) is recommended to bypass these spikes.

The required value of L1 is inversely proportional to the ripple current ∆IO in it. Setting the relative peak-to-peak ripple to 20~30% is a good practice to ensure noise immunity of the current sense comparator.

⋅

OOFF

1 =

(1)

VO is the forward voltage of the LED string. T

∆

is the off-

OFF

time of the HV9925. The output current in the LED string (IO) is calculated then as:

=−⋅

SENSE

∆

(2)

where VTH is the current sense comparator threshold, and R

is the current sense resistor. The ripple current

SENSE

introduces a peak-to-average error in the output current setting that needs to be accounted for. Due to the constant off-time control technique used in the HV9925, the ripple current is nearly independent of the input AC or DC voltage

Using an ultra-fast rectiﬁ er diode for D1 is recommended to achieve high efﬁ ciency and reduce the risk of false triggering of the current sense comparator. Using diodes with shorter reverse recovery time trr, and lower junction capacitance CJ, achieves better performance. The reverse voltage rating VR of the diode must be greater than the maximum input voltage of the LED lamp.

The total parasitic capacitance present at the DRAIN output of the HV9925 can be calculated as: (3)

CC C CC

=+++

P DRAIN PCB L J

When the switch turns on, the capacitance CP is discharged into the DRAIN output of the IC. The discharge current is limited to about 150mA typically. However, it may become lower at increased junction temperature. The duration of the leading edge current spike can be estimated as:

⋅

(4)

SPIKE

IN P

SAT

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HV9925

In order to avoid false triggering of the current sense comparator, CP must be minimized in accordance with the following expression:

IT t

⋅−

()

SAT BLANK MIN rr

(5)

where T V

BLANK(MIN)

is the maximum instantaneous input voltage.

IN(MAX)

The typical DRAIN and R

()

IN MAX

is the minimum blanking time of 200ns, and

voltage waveforms are shown

SENSE

in Fig. 3 and Fig. 4.

Estimating Power Loss

Discharging the parasitic capacitance CP into the DRAIN output of the HV9925 is responsible for the bulk of the switching power loss. It can be estimated using the following equation:

VI t F

IN SAT rr S

⎞

⋅

⎟ ⎟

⎠

is the saturated

SAT

(6)

SWITCH

=+⋅

⎜ ⎜

⎝

where Fs is the switching frequency and I

⎛

DRAIN current of the HV9925. The switching loss is the greatest at the maximum input voltage.

When the LED driver is powered from the full-wave rectiﬁ ed AC line input, the exact equation for calculating the conduction loss is more cumbersome. However, it can be estimated using the following equation:

PKIRKIV

=⋅⋅ +⋅⋅

COND C O ON d DD AC

(10)

where VAC is the input AC line voltage. The coefﬁ cients KC and Kd can be determined from the minimum duty ratio Dm=0.71Vo/(ηVAC).

0.7

0.6

0.5

Kd Dm()

Kc Dm()

0.4

0.3

0.2

The switching frequency is given by the following:

−η1

−⋅

IN O

(7)

⋅

IN OFF

where η is the efﬁ ciency of the power converter.

When the HV9925 LED driver is powered from the full-wave rectiﬁ ed AC input, the switching power loss can be estimated as:

SWITCH

≈

⋅

VC I tV V

⋅+⋅ ⋅

()

AC P SAT rr AC O

OFF

()

−

−⋅

(8)

VAC is the input AC line voltage.

The switching power loss associated with turn-off transitions of the DRAIN output can be disregarded. Due to the large amount of parasitic capacitance connected to this switching node, the turn-off transition occurs essentially at zerovoltage.

When the HV9925 LED driver is powered from DC input voltages, conduction power loss can be calculated as:

PDIRIVD

COND O ON DD IN

=⋅ ⋅ + ⋅ ⋅−

()

(9)

where D = VO /ηVIN is the duty ratio, RON is the ON resistance, IDD is the internal linear regulator current.

0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7

Fig. 1. Conduction Loss Coefﬁ cients KC and K

EMI Filter

As with all off-line converters, selecting an input ﬁ lter is critical to obtaining good EMI. A switching side capacitor, albeit of small value, is necessary in order to ensure low impedance to the high frequency switching currents of the converter. As a rule of thumb, this capacitor should be approximately 0.1-

0.2 µF/W of LED output power. A recommended input ﬁ lter is shown in Figure 2 for the following design example.

Design Example 1

Let us design an HV9925 LED lamp driver meeting the following speciﬁ cations:

Input: Universal AC, 85-264VAC Output Current: 20mA Load: String of 10 LED (LW541C by OSRAM

VF = 4.1V max. each)

The schematic diagram of the LED driver is shown in Fig.2.

Page 7

HV9925

Step 1. Calculating L1.

The output voltage V

= 10 · VF ≈ 41V (max.). Use equation

(1) assuming a 30% peak-to-peak ripple.

41 10

⋅

03 20

⋅

mH1

68=

Select L1 68mH, I=30mA. Typical SRF = 170KHz. Calculate the coil capacitance.

() ( )ππ

LSRF mH KHz

⋅⋅

68 2 170

⋅⋅

≈

Step 2. Selecting D1

Usually, the reverse recovery characteristics of ultrafast rectiﬁ ers at IF = 20~50mA are not provided in the manufacturer’s data books. The designer may want to experiment with different diodes to achieve the best result.

Select D1 MUR160 with VR = 600V, t

≈ 20ns (IF = 20mA, I

= 100mA) and CJ ≈ 8pF (VF>50V).

Step 3. Calculating total parasitic capacitance using:

C pFpF pFpF pF

=++ +=55138 31

(3)

Step 4. Calculating the leading edge spike duration using (4) and (5):

VpF

⋅⋅

SPIKE BLANK MIN

264 2 31

100

ns ns T

+≈ <

20 136

()

Step 5. Estimating power dissipation in HV9925 at 264VAC using (8) and (10)

Step 6. Selecting input capacitor C

Output Power =⋅ =41 20 820VmA mW

Select CIN ECQ-E4104KF by Panasonic (0.1µF, 400V, Metalized Polyester Film).

Design Example 2

Let us now design a PWM-dimmable LED lamp driver using the HV9925:

Input: Universal AC, 85-135VAC Output Current: 50mA Load: String of 12 LED (Power TOPLED® by

OSRAM, VF = 2.5V max. each)

The schematic diagram of the LED driver is shown in Fig.3. We will use an aluminum electrolytic capacitor for CIN in order to prevent interruptions of the LED current at zero crossings of the input voltage. As a “rule of thumb”, 2~3μF per each watt of the input power is required for CIN in this case.

Step 1. Calculating L1.

The output voltage VO = 12 · VF = 30V (max.). Use equation (1) assuming a 30% peak-to-peak ripple.

30 10 5

⋅

03 50

⋅

..µ mA

mH1

21=

Select L1 22mH, I = 60mA. Typical SRF = 270KHz. Calculate the coil capacitance.

() ( )ππ

LSRF mH KHz

⋅⋅

22 2 270

⋅⋅

≈

Step 2. Selecting D1

Let us assume that the overall efﬁ ciency η = 0.7.

Switching power loss:

≈

210

≈ 125

⋅

VpF mA ns V

⋅+⋅ ⋅

264 31 2 100 20 264

()

SWITCH

PmW

SWITCH

⎛

−

⎜ ⎝

⎞ ⎟

07µ .

⎠

Select D1 ES1G with VR = 400V, t

Step 3. Calculating total parasitic capacitance using (3):

C pFpF pFpF pF

Step 4. Calculating the leading edge spike duration using (4) and (5):

Minimum duty ratio:

DVV

=⋅ ⋅ ≈0 71 41 0 7 264 0 16./(. ).

Conduction power loss:

PmA AVmW

=⋅

..Ωµ

COND

()

⋅+⋅ ⋅≈0 25 20 210 0 63 200 264 55

SPIKE BLANK MIN

Step 5. Estimating power dissipation in HV9925 at 135VAC using (6), (7) and (9)

Switching power loss:

Total power dissipation at V

PmWmWmW

=+=125 55 180

TOTAL

AC(max)

≈ 35ns and CJ < 10pF.

=++ +=55138 31

VpF

⋅⋅

135 2 35

135 2 30 0 7

135 2 10

100

⋅−

⋅⋅

ns ns T

+≈ <

35 100

kHz

()

Page 8

HV9925

PpFVVmAnskHz

SWITCH

PmW

SWITCH

=⋅

(

()

≈ 52

+⋅⋅ ⋅

)

⋅35 135 135 2 100 35 78

Minimum duty ratio:

DV V

=⋅⋅≈30 0 7 135 2 0 23/( . ) .

Total power dissipation in HV9925:

PmWmWmW

=+ =52 217 269

TOTAL

Step 6. Selecting input capacitor C

Output Power =⋅ =30 50 1 5VmA W.

Select CIN 3.3µF, 250V.

Conduction power loss:

VmA

⋅⋅

30 50 200

COND

PmW

= 217

COND

()

07 85 2

⋅⋅

Ω

+⋅⋅−

05 85 2

mA V

⎛ ⎜

⎝

⎞ ⎟

⎠

Figure 2. Universal 85-264VAC LED Lamp Driver

(IO = 20mA, VO = 50V) from Example 1

IN2

D2 D3

D4 D5

LED

-LED

AC Line 85-264V

VRD1

HV9925

SENSE

Figure 3. 85-135VAC LED Lamp Driver with PWM Dimming

D2 D3

AC Line

85-135V

100~200Hz

D4 D5

HV9925

-LED

LED

SENSE

Page 9

HV9925

Figure 4. Switching Waveforms. CH1: V

RSENSE

, CH2: V

Figure 6. PWM Dimming – Rising Edge. CH4: 10×I

DRAIN

OUT

Figure 5. Switch-On Transition – Leading Edge Spike.

CH1: VR

SENSE

, CH2: V

DRAIN

Figure 7. PWM Dimming – Falling Edge. CH4: 10×IOUT

Page 10

HV9925

8-Lead SOIC (Narrow Body w/Heat Slug) Package Outline (SG)

4.90x3.90mm body, 1.70mm height (max), 1.27mm pitch

Note 1

(Index Area

D/2 x E1/2)

Top View

Side View

Seating

Plane

Exposed Thermal Pad Zone

Bottom View

View

θ1

View B

Gauge

Plane

Seating

Plane

Note 1

View A-A

Note 1:

This chamfer feature is optional. If it is not present, then a Pin 1 identiﬁ er must be located in the index area indicated.The Pin 1 identiﬁ er may be either a mold, or an embedded metal or marked feature.

Symbol A A1 A2 b D D1 E E1 E2 e h L L1 L2 θ θ1

Dimension

(mm)

JEDEC Registration MS-012, Variation BA, Issue E, Sept. 2005. Dimensions marked with (*) are non-JEDEC dimensions.

Drawings not to scale.

MIN 1.25 0.00 1.25 0.31 4.80 3.30* 5.80 3.80 2.29*

NOM - - - - 4.90 - 6.00 3.90 - - - - -

MAX 1.70 0.15 1.70 0.51 5.00 3.81* 6.20 4.00 2.79* 0.50 1.27 8

1.27

BSC

0.25 0.40

1.04 REF

0.25 BSC

(The package drawing(s) in this data sheet may not reﬂ ect the most current speciﬁ cations. For the latest package outline information go to http://www.supertex.com/packaging.html.)

Doc.# DSFP-HV9925 NR 11150 6