Page 1
32-Channel Serial To Parallel Converter
With High Voltage Push-Pull Outputs
Ordering Information
Package Options
Device 44 J-Lead Quad Die
Plastic Chip Carrier in waffle pack
HV9708 HV9708PJ HV9708X
HV9808 HV9808PJ HV9808X
HV9708
HV9808
Features
❏ Processed with HVCMOS® technology
❏ Output voltages up to 80V
❏ Low power level shifting
❏ Shift register speed 8MHz
❏ Latched data outputs
❏ Forward and reverse shifting options
❏ Diode to V
❏ 5V CMOS compatible inputs
Absolute Maximum Ratings
Supply voltage, V
Output voltage, V
Logic input levels
Ground current
Continuous total power dissipation
Operating temperature range -40°C to +85°C
Storage temperature range -65°C to +150°C
Lead temperature 1.6mm (1/16 inch) 260°C
from case for 10 seconds
Notes:
1. Device will survive (but operation may not be specified or guaranteed) at
these extremes.
2. All voltages are referenced to GND.
3. Duty cycle is limited by the total power dissipated in the package.
4. For operation above 25°C ambient, derate linearly to 70°C at 12mW/°C.
allows efficient power recovery
PP
2
DD
2
PP
2
3
4
1
-0.5V to +7V
VDD to +90V
-0.5V to VDD +0.5V
1.5A
1200mW
General Description
The HV97 and HV98 are low-voltage serial to high-voltage parallel converters with push-pull outputs. These devices have been
designed for use as drivers for AC-electroluminescent displays.
They can also be used in any application requiring multiple output
high-voltage current sourcing and sinking capabilities such as
driving plasma panels, vacuum fluorescent displays, or large
matrix LCD displays. The inputs are fully CMOS compatible.
These devices consist of a 32-bit shift register, 32 latches, and
control logic to perform the polarity select and blanking of the
outputs. HV
through the polarity and blanking logic. Data is shifted through the
shift register on the logic low to high transition of the clock. The
HV97 shifts data in the clockwise direction when viewed from the
top of the package and the HV98 shifts in the counterclockwise
direction. A data output buffer is provided for cascading devices.
This output reflects the current status of the last bit of the shift
register (HV
by the LE (latch enable), BL (blanking), or the POL (polarity) inputs. Transfer of data from the shift register to the latch occurs
when the LE (latch enable) input is high. The data in the latch is
stored when LE is low.
1 is connected to the first stage of the shift register
OUT
32). Operation of the shift register is not affected
OUT
02/96/022
Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability
indemnification insurance agreement." Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of devices determined to be defective due to
workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications, refer to the
Supertex website: http://www.supertex.com. For complete liability information on all Supertex products, refer to the most current databook or to the Legal/Disclaimer page on the Supertex website.
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HV9708/HV9808
Electrical Characteristics (V
= 60V, VDD = 5V, TA =25°C)
PP
DC Characteristics
Symbol Parameter Min Max Units Conditions
I
PP
I
DDQ
I
DD
V
(Data) Shift Register Output Voltage VDD-0.5 V IO = -100µA
OH
V
(Data) Shift Register Output Voltage 0.5 V IO = 100µA
OL
I
IH
I
IL
V
OC
V
OH
V
OL
VPP Supply Current 100 µAHV
outputs HIGH to LOW
OUT
IDD Supply Current (Quiescent) 100 µA All inputs = VDD or GND
IDD Supply Current (Operating) 15 mA VDD = VDD max,
= 8 MHz
f
CLK
Current Leakage, any input 1 µA Input = V
DD
Current Leakage, any input -1 µA Input = GND
HV
Output Clamp Diode Voltage -1.5 V IOC = -5mA
OUT
HV
Output when Sourcing 52 V IOH = -20mA, 0 to 70°C
OUT
HV
Output when Sinking 4 V IOL = 5mA, 0 to 70°C
OUT
AC Characteristics
Symbol Parameter Min Max Units Conditions
f
CLK
tWL or t
WH
t
SU
t
H
t
(Data) Data Output Delay after L to H CLK 110 ns CL = 15pF
DLH
t
(Data) Data Output Delay after H to L CLK 110 ns CL = 15pF
DHL
t
DLE
t
WLE
t
SLE
t
ON
t
OFF
Clock Frequency 8 MHz
Clock width, HIGH or LOW 62 ns
Setup time before CLK rises 25 ns
Hold time after CLK rises 10 ns
LE Delay after L to H CLK 50 ns
Width of LE Pulse 50 ns
LE Setup Time before L to H CLK 50 ns
Delay from LE to HV
Delay from LE to HV
, L to H 500 ns
OUT
, H to L 500 ns
OUT
Recommended Operating Conditions
Symbol Parameter Min Max Units Comments
V
DD
V
PP
V
IH
V
IL
f
CLK
T
A
Notes:
Power-up sequence should be the following:
1. Connect ground.
2. Apply V
3. Set all inputs (Data, CLK, Enable, etc.) to a known state.
4. Apply V
Power-down sequence should be the reverse of the above.
5. The V
Logic Voltage Supply 4.5 5.5 V
High Voltage Supply 8.0 80 V
Input HIGH Voltage VDD-0.5 V
Input LOW Voltage 0 0.5 V
Clock Frequency 0 8 MHz
Operating free-air temperature -40 +85 °C
.
DD
.
PP
should not drop below VDD or float during operations.
PP
2
DD
V
Page 3
Input and Output Equivalent Circuits
HV9708/HV9808
V
DD
Input
GND
Logic Inputs
Switching Waveforms
Clock
Data Out
50% 50% 50%
V
GND
DD
Data Out
Logic Data Output
V
GND
PP
High Voltage Outputs
HV
OUT
V
IH
Data Valid50% 50%Data Input
V
t
SU
t
H
IL
V
IH
50%
V
t
WL
t
WH
IL
V
OH
50%
V
t
DLH
t
50%
DHL
OL
V
OH
V
OL
Latch Enable
HV
OUT
w/ S/R LOW
HV
OUT
w/ S/R HIGH
t
3
DLE
50%
t
t
OFF
ON
t
WLE
10%
90%
10%
90%
50%
t
SLE
V
IH
V
OL
V
OH
V
OL
V
OH
V
OL
Page 4
Functional Block Diagram
V
PP
Polarity
Blanking
Latch Enable
Data Input
Latch
HV9708/HV9808
HV
1
OUT
Clock
2
HV
Latch
OUT
32-Bit
Data Out
Shift
Register
Latch
Latch
(Outputs 3 to 30
not shown)
HV
31
OUT
32
HV
OUT
Function Table
Inputs Outputs
Function Shift Reg HV Outputs Data Out
All on X X X L L * *…*HH…H*
All off X X X L H * *…*LL…L*
Invert mode X X L H L * *…***…**
Load S/R H or L ↑ LHHH or L *…***…**
Load
latches
Transparent
latch mode
Notes:
H = high level, L = low level, X = irrelevant,
* = dependent on previous stage’s state before the last CLK or last LE high.
Data CLK LE BL POL
12…32 1 2…32 *
XH or L ↑ HH**…***…**
XH or L ↑ HL**…***…**
L
↑ HHHL*…*L*…**
H ↑ H HHH*…*H*…**
↑ = low-to-high transition.
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HV9708/HV9808
Pin Configurations
HV97
44 Pin J-Lead Package
Pin Function Pin Function
1HV
2HV
3HV
4HV
5HV
6HV
7HV
8HV
9HV
10 HV
11 HV
12 HV
13 HV
14 HV
15 HV
16 HV
17 HV
18 Data Out 40 HV
19 NC 41 HV
20 NC 42 HV
21 Polarity 43 HV
22 Clock 44 HV
17 23 GND
OUT
16 24 V
OUT
15 25 V
OUT
14 26 Latch Enable
OUT
13 27 Data In
OUT
12 28 Blanking
OUT
11 29 NC
OUT
10 30 HVout 32
OUT
931HV
OUT
832HV
OUT
733HV
OUT
634HV
OUT
535HV
OUT
436HV
OUT
337HV
OUT
238HV
OUT
139HV
OUT
PP
DD
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
Package Outline
39 38 37 36 35 34
40
41
42
43
44
1
2
3
4
5
6
7 8 9 10 11 12
top view
44-pin J-Lead Package
33 32 31 30 29
28
27
26
25
24
23
22
21
20
19
18
13 14 15 16 17
HV98
44 Pin J-Lead Package
Pin Function Pin Function
1HV
2HV
3HV
4HV
5HV
6HV
7HV
8HV
9HV
10 HV
11 HV
12 HV
13 HV
14 HV
15 HV
16 HV
17 HV
18 Data Out 40 HV
19 NC 41 HV
20 NC 42 HV
21 Polarity 43 HV
22 Clock 44 HV
©2002 Supertex Inc. All rights reserved. Unauthorized use or reproduction prohibited.
16 23 GND
OUT
17 24 V
OUT
18 25 V
OUT
19 26 Latch Enable
OUT
20 27 Data In
OUT
21 28 Blanking
OUT
22 29 NC
OUT
23 30 HV
OUT
24 31 HV
OUT
25 32 HV
OUT
26 33 HV
OUT
27 34 HV
OUT
28 35 HV
OUT
29 36 HV
OUT
30 37 HV
OUT
31 38 HV
OUT
32 39 HV
OUT
PP
DD
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
02/06//02
1235 Bordeaux Drive, Sunnyvale, CA 94089
TEL: (408) 744-0100 • FAX: (408) 222-4895
5
www.supertex.com
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