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High Voltage Current Mode PWM Controller
Ordering Information
+V
IN
Min Max
15V 250V < ± 1% 49% HV9605CP HV9605CNG HV9605CX
Feedback Max
Accuracy Duty Cycle
14 Pin 14 Pin
Plastic DIP Narrow Body SOIC
Package Options
Die
HV9605C
Preliminary
Features
❏ BiCMOS/DMOS technology
❏ Current mode control
❏ 49% duty cycle operation
❏ Programmable START/STOP capability
❏ 15V to 250V input range internal start-up regulator
❏ 6.0µA standby supply current for +V
❏ 0.9mA operating supply current
❏ 5.0V VDD supply operation
❏ 30KHz to 300KHz internal oscillator
❏ 15KHz to 150KHz converter output frequency
❏ 1.0MHz low offset error amplifier
❏ 1.25V 2% band gap reference
❏ Output driver optimized for under 10W applications
❏ Low driver output impedance with V
❏ Fast (90nsec) over current shutdown
❏ All pins are ESD protected
<20V
IN
= 0V
DD
Applications
❏ ISDN network terminations
❏ ISDN terminals
❏ ISDN terminal adapters
❏ Feature phones
❏ SLIC circuits
❏ PBX systems
❏ Modems
❏ Distributed power systems
❏ DC/DC converters
General Description
The Supertex HV9605C is a BiCMOS/DMOS single-output,
current mode, pulse width modulator IC designed to meet the
requirements of ETR-080 for ISDN applications. In a 14 pin
package, it provides all the necessary functions to implement a
single-switch PWM with a minimum of external parts.
Utilizing Supertex’s proprietary BiCMOS/DMOS technology, it
requires less than one tenth of the operating power of conventional
bipolar PWM ICs. Dynamic range for regulation is also increased
to approximately 8 times that of similar bipolar parts. It operates
directly from any DC input voltage between 15 and 250 VDC. The
START and STOP input voltage thresholds can be programmed
within the operating input voltage range by means of a resistor
divider, provided +V
push-pull CMOS, eliminating the need for external clamping
diodes. The clock frequency is set with a single external resistor.
IN(START)
> +V
. The output stage is
IN(STOP)
Absolute Maximum Ratings*
+VIN, Input Voltage -0.5V to +250V
Supply Voltage, V
Operating Temperature Range -40°C to +85°C
Storage Temperature Range -65°C to +150°C
Power Dissipation @ 25°C, SOIC 750mW
Power Dissipation @ 25°C, Plastic DIP 1000mW
*All voltages referenced to GND
DD
-0.5V to +10V
11/12/01
Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability
indemnification insurance agreement." Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of devices determined to be defective due to
workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications, refer to the
Supertex website: http://www.supertex.com. For complete liability information on all Supertex products, refer to the most current databook or to the Legal/Disclaimer page on the Supertex website.
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Electrical Characteristics
Symbol Parameters Min Typ Max Unit Conditions
Pre-Regulator/Start-Up
HV9605C
+V
+I
+I
+I
+I
V
IN
IN
IN
IN
START
DD
Regulator input voltage 15 250 V
Input leakage current 6.0 µA+VIN=20V, Start=0V, Stop=0V
Input leakage current 15 µA+VIN = 50V, VDD = 4.7V
Input leakage current 70 µA+VIN = 250V, VDD = 4.7V
Pre-regulator start-up current 5.0 mA +VIN = 15V,
Regulator output voltage 4.4 4.5 4.6 V
UVLO Under voltage lockout threshold 4.1 4.2 4.4 V V
HYST Under voltage hysteresis 0.1 0.3 0.4 V
Supply
V
DD
I
DD
Operating range 4.7 8.0 V
Supply current 0.9 1.3 mA OUT open,
Start/Stop Control
V
START
I
START
I
STOP
V
CLAMP
Start threshold 6.72 7.30 7.88 V
Start input current 0.05 µA+VIN = 18V
Stop input current 0.05 µA+VIN = 18V
Zener clamp voltage on STOP Pin 15 V
Start & Stop 10MΩ to + V
rising
DD
= 20KHz to 150KHz,
f
OUT
= 5V
V
DD
IN
MOSFET Driver Output
V
OUT(HIGH)
V
OUT(LOW)
t
R
t
F
Output high voltage 4.85 4.90 V I
Output low voltage 0.05 0.15 V I
Rise time 30 50 nsec CL = 250pF
Fall time 20 50 nsec CL = 250pF
Oscillator
150 KHz RT = 91KΩ
f
OUT
T
C
∆f/f Voltage stability 1 3 % f
Output converter frequency 45 50 55 KHz RT = 357KΩ
31.5 35 38.5 KHz R
18 20 22 KHz R
Temperature coefficient 100 300 PPM/°Cf
= 10mA, VDD = 5.00V
OUT
= -10mA
OUT
= 536KΩ
T
= 1.0MΩ
T
= 50KHz
OUT
= 50KHz, 4.5V< VDD<5.5V
OUT
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Electrical Characteristics (continued)
Symbol Parameters Min Typ Max Unit Conditions
PWM
HV9605C
D
MAX
D
MIN
Maximum duty cycle 49.0 49.9 % f
Minimum duty cycle 0 %
Minimum pulse width before pulse drop out 80 125 nsec
Reference
V
REF
V
REF
V
REF
V
REF
I
REF(SHORT)
Reference output voltage 1.225 1.250 1.275 V TA = 25°C
Load regulation 1.0 5.0 mV 0 < I
Line regulation 2.0 5.0 mV 4.5V < VDD < 5.5V
Reference output voltage 1.207 1.250 1.293 V -40°C < TA < 85°C
Long term stability 3.0 mV T
Short circuit current 0.5 1.0 mA V
Current Sensing
V
CS
V
CS (LIMIT)
t
DELAY
Usable control current sense range VCS (limit) V
Current limit threshold 0.6 0.7 0.8 V
Current limit delay to output 90 120 nsec VCS = 1.5V
= 20KHz
OUT
< 0.3mA
REF
= 125°C, 1000hrs
A
= SGND
REF
Error Amplifier
V
FB
or I
I
FB
NI
V
OS
V
CM
A
VOL
BW Unity gain bandwidth 1.0 1.5 MHz
I
SOURCE
I
SINK
PSRR Power supply rejection 50 72 dB 4.5V < VDD < 5.5V, f=1KHz
Feedback voltage 1.238 1.250 1.263 V REF shorted to NI, FB
shorted to Comp, T
= 25°C
A
Input bias current 25 200 nA VFB = 3.0V, VNI = 2.5V
Input offset voltage 5.0 25 mV
Common mode input range 0 VDD-1 V
Open loop voltage gain 65 90 dB
Output current sourcing -2 -1 mA VFB < V
Output current sinking 2 4 mA VFB > V
NI
NI
Status Output
I
SINK
I
SOURCE
V
STATUS(HIGH)
V
STATUS(LOW)
Output current sinking 5.0 10 mA V
STATUS
= 2.0V
Output current sourcing 5.0 10 15 µA
High output voltage VDD-0.2 V
DD
V No load
Low output voltage 1.0 2.0 V Sinking 5mA
0.02 0.04 V Sinking 100µA
t
R
Rise time 1.0 5.0 msec 4.7nF From Status to GND
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Pin Description
HV9605C
SGND – Common connection for all low level signal and
digital circuits. While SGND and PGND must be
electrically connected together, having separate
common pins enhances the ability of the designer
to prevent coupling of noise into critical circuits.
PGND – This pin provides common return for the high
transient current of the output driver circuits. While
PGND and SGND must be electrically connected,
having a separate connection prevents common
noise created by the high transient currents of the
output driver from being injected into critical circuits.
+V
– This is the start-up linear pre-regulator input which
IN
can accept DC input voltages in the range of 15V
to 250V. With START and STOP set to more than
20V, the leakage current on this pin is less than
6.0µA at +VIN = 20V.
START – The resistive divider from +V
STOP – The resistive divider from +V
V
DD
– This is the supply pin for the PWM circuits. When
the input voltage to the +V
sets the start voltage.
IN
sets the stop voltage.
IN
pin exceeds the start
IN
voltage the input regulator seeks to regulate the
voltage on the capacitor connected to this pin to a
nominal 4.5V.
OUT – This high current push-pull CMOS output is intended
to drive the gate of a power MOSFET. In order to
protect the power MOSFET in high electrical noise
environment, this output appears as low impedance
to PGND when V
is at zero volts.
DD
CS – This is the current sense input to the PWM
comparators. Under normal operation the over
current limit is triggered when the voltage on this
pin is at 0.70V and the loop control operating peak
current may be set to any level below this, typically
in the range of 0.2 to 0.5V.
COMP – The low impedance output of the error amplifier.
FB – The high impedance inverting input of the error
amplifier.
NI – The high impedance non-inverting input of the error
amplifier.
REF – This pin provides a 2% accuracy 1.25V low output
impedance buffered reference which is current
limited to 0.5mAmps and should be bypassed,
REF to SGND, with a 0.1µF ceramic capacitor.
RT – The resistor connected from this pin to SGND sets
the frequency of the internal oscillator by setting
the charging current for the internal timing capacitor.
The oscillator frequency is twice the PWM output
frequency.
STATUS – This output is held low until the +V
voltage reaches
IN
the programmed START voltage. It remains low
until the bootstrap supply to VDD forces the voltage
above the internal regulator set point. It is further
held low while the control amplifier output on the
COMP pin is forced to its high limit by a low output
from the converter. Once all these conditions are
satisfied, this output will rise to V
with a time
DD
constant set by the external capacitor indicating
that normal operation has been reached. This
output may be used to control the reset of a
microprocessor.
Pin Configuration
1
+V
IN
STOP
START
REF
PGND
2
3
4
5
V
DD
6
7
CS
14 Pin SOIC/DIP Package
14
13
12
11
10
9
8
COMP
FB
NI
STATUS
RT
SGND
OUT
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Functional Block Diagram
+V
IN
+
—
START
Enable
C
STOP
H
L
START
V
Start-Up
Regulator
+
—
V
REF
Bootstrap Good
C
UVLO
HV9605C
V
DD
Clock
Oscillator
RT
CLK
DQ
CLR
V
DD
Bandgap
Reference
Generator
Q
Typical Application Circuit
HV9605C
48V INPUT
+
+
-
+V
IN
STOP
START
+
A
—
REF NI FB COMP
V
DD
STATUS
OUT
CS
-
+
C
PWM Good
Q
S
R
MOSFET Driver
++
TN2124K1
or
TN2524N8
V
DD
STATUS
OUT
CS
PGND
SGND
+
ISOLATED
OUTPUT
+
40V
-
RESET
COMPFBNIREFRT
©2001 Supertex Inc. All rights reserved. Unauthorized use or reproduction prohibited.
PGND
SGND
+5.0V
REFERENCED
TO INPUT (-)
TERMINAL
11/12/01
1235 Bordeaux Drive, Sunnyvale, CA 94089
TEL: (408) 744-0100 • FAX: (408) 222-4895
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www.supertex.com
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