Page 1
High-Voltage Switchmode Controllers with MOSFET
Ordering Information
HV9100
HV9102
HV9103
+V
IN
Min Max
10V 70V ± 1.0% 49% 150V 5.0Ω HV9100P HV9100PJ
10V 120V ± 1.0% 49% 200V 7.0Ω HV9102P HV9102PJ
10V 120V ±1.0% 99% 200V 7.0Ω HV9103P HV9103PJ
Standard temperature range for all parts is industrial (-40° to +85°C).
Feedback Max
Voltage Duty Cycle
Features
❏ 10 to 120V input range
❏ 200V, 7.0Ω output MOSFET
❏ Current-Mode Control
❏ High Efficiency
❏ Up to 1MHz Internal Oscillator
❏ Internal Start-up Circuit
Applications
❏ DC/DC Converters
❏ Distributed Power Systems
❏ ISDN Equipment
❏ PBX Systems
❏ Modems
MOSFET Switch Package Options
BV
DSS
R
DS (ON)
14 Pin Plastic DIP 20 Pin Plastic PLCC
General Description
The Supertex HV9100 through HV9103 are a series of BiCMOS/
DMOS single-output, pulse width modulator ICs intended for use
in high-speed high-efficiency switchmode power supplies. They
provide all the functions necessary to implement a single-switch
current-mode PWM, in any topology, with a minimum of external
parts.
Utilization of Supertex proprietary BiCMOS/DMOS technology
results in a device with one tenth of the operating power of
conventional bipolar PWM ICs, which can operate at more than
twice their switching frequency. Dynamic range for regulation is
also increased, to approximately 8 times that of similar bipolar
parts. They start directly from any DC input voltage between 10
and 70VDC for the HV9100 or 10 to 120VDC for the HV9102 and
HV9103, requiring no external power resistor. The output stage
for the HV9100 is a 150V, 5.0 ohm MOSFET and for the HV9102
and HV9103 is a 200V, 7.0 ohm MOSFET. The clock frequency
is set with a single external resistor.
Accessory functions are included to permit fast remote shutdown
(latching or nonlatching), and undervoltage shutdown.
Absolute Maximum Ratings
+VIN, Input Voltage 120V
V
DS
VDD, Logic Voltage 15.0V
Input Voltage Logic, Linear, FB and Sense -0.3V to VDD+0.3V
ID (Peak) 2.5A
Storage Temperature -65°C to 150°C
Power Dissipation, Plastic DIP 750mW
Power Dissipation, PLCC 1400mW
11/12/01
Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability
indemnification insurance agreement." Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of devices determined to be defective due to
workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications, refer to the
Supertex website: http://www.supertex.com. For complete liability information on all Supertex products, refer to the most current databook or to the Legal/Disclaimer page on the Supertex website.
200V
For detailed circuit and application information, please refer
to application notes AN-H13 and AN-H21 to AN-H24.
1
Page 2
HV9100/HV9102/HV9103
Electrical Characteristics
(V
= 10V, +V
DD
Symbol Parameters Min Typ Max Unit Conditions
Reference
= 48V, Discharge = -V
IN
= 0V, R
IN
= 390KΩ, R
BIAS
= 330KΩ,TA = 25°C, unless otherwise specified)
OSC
V
REF
Z
OUT
I
SHORT
∆V
Output Voltage HV9100/02/03 3.92 4.00 4.08 V RL = 10MΩ
Output Impedance
Short Circuit Current 100 250 µAV
Change in V
REF
Oscillator
f
MAX
f
OSC
Oscillator Frequency 1.0 3.0 MHz R
Initial Accuracy
Voltage Stability 15 % 9.5V < V
Temperature Coefficient 170 ppm/°C
PWM
D
MAX
D
MIN
Maximum Duty Cycle HV9100/02 49.0 49.4 49.6 %
Deadtime HV9103 100 nsec
Minimum Duty Cycle 0 %
Minimum Pulse Width 110 175 nsec
Before Pulse Drops Out
HV9102/03 3.86 4.00 4.14 V IN = V
1
with Temperature 0.25 mV/°C
REF
2
15 30 45 KΩ
80 100 120 KHz R
160 200 240 R
HV9103 99.0 99.4 99.6
1
, RL = 10MΩ
IN
= -55°C to 125°C
T
A
= -V
REF
OSC
OSC
OSC
IN
= 0Ω
= 330KΩ
= 150KΩ
< 13.5V
DD
Error Amplifier
V
FB
I
IN
V
OS
A
VOL
gbw Unity Gain Bandwidth
Z
OUT
I
SOURCE
I
SINK
PSRR Power Supply Rejection See Fig. 1
Feedback Voltage HV9100/02/03 3.96 4.00 4.04 V VFB Shorted to Comp
Input Bias Current 25 500 nA V
Input Offset Voltage nulled at trim mV Except 9101
Open Loop Voltage Gain
Output Impedance
1
1
1
60 80 dB
1.0 1.3 MHz
See Fig. 2 Ω
Output Source Current -2.0 -1.4 mA V
Output Sink Current 0.12 0.15 mA V
Current Limit
V
SOURCE
t
d
Notes:
1. Guaranteed by design. Not subject to production test.
2. Stray capacitance on OSC In pin ≤5pF.
Threshold Voltage 1.0 1.2 1.4 V V
Delay to Output
1
150 ns V
= 4.0V
FB
= 3.4V
FB
= 4.5V
FB
= 0V, RL = 100Ω
FB
= 1.5V, RL = 100Ω
SOURCE
2
Page 3
HV9100/HV9102/HV9103
Electrical Characteristics (Continued)
(V
= 10V, +V
DD
Symbol Parameters Min Typ Max Unit Conditions
Pre-Regulator/Startup
= 48V, Discharge = -V
IN
= 0V, R
IN
= 390KΩ, R
BIAS
= 330KΩ,TA = 25°C, unless otherwise specified)
OSC
+V
IN
V
TH
V
LOCK
Supply
I
DD
I
BIAS
V
DD
Logic
t
SD
t
SW
t
RW
t
LW
V
IL
V
IH
I
IH
I
IL
Allowable Input Voltage HV9100 70 V I
= 10µA
IN
HV9102/03 120
Input Leakage Current 10 µAV
VDD Pre-regulator Turn-off 7.8 8.6 9.4 V I
> 9.4V
DD
PREREG
= 10µA
Threshold Voltage
Undervoltage Lockout 7.0 8.1 8.9 V RL = 100Ω from Drain to V
Supply Current 0.60 1.0 mA
0.55 mA Shutdown = -V
IN
Bias Current 20 µA
Operating Range 9.0 13.5 V
Shutdown Delay Time
Shutdown Pulse Width
RESET Pulse Width
Latching Pulse Width
1
1
1
1
50 ns
50 ns
25 ns
50 100 ns V
SOURCE
= -V
IN
Input Low Voltage 2.0 V
Input High Voltage 7.0 V
Input High Current 1.0 5.0 µAVIN = 10V
Input Low Current -25 -35 µAVIN = 0V
DD
MOSFET Switch
BV
R
DS(ON)
I
DSS
C
DS
Note:
1. Guaranteed by design. Not subject to production test.
Breakdown Voltage HV9100 150 V V
DSS
HV9102/03 200 I
Drain-to-Source HV9100 3.5 5.0 Ω V
On-resistance HV9102/03 7.0 Ω
OFF State Drain Leakage Current 10 µAV
Drain Capacitance 35 pF V
Truth Table
Shutdown Reset Output
H H Normal Operation
HH → L Normal Operation, No Change
L H Off, Not Latched
L L Off, Latched
L → H L Off, Latched, No Change
= Shutdown = 0V,
SOURCE
= 100µA,
D
T
= -55°C to 125°C
A
= 0V, ID = 100mA
SOURCE
= Shutdown = 0V,
SOURCE
= 100V
V
DRAIN
= 25V, Shutdown = 0V
DS
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Page 4
Switching Waveforms
1.5V
Source
Drain
Shutdown
Reset
V
DD
50%
0
t
d
0
V
DD
50%
0
V
DD
0
t
≤ 10ns
R
50%
HV9100/HV9102/HV9103
t
V
DD
Shutdown
50%
0
t
SD
V
Drain
DD
90%90%
0
t
SW
50%
t
LW
50%
t
RW
50%
≤ 10ns
F
, tF ≤ 10ns
t
R
Functional Block Diagram
COMP Discharge
Error
Amplifier
–
+
4V
To
Internal
Circuits
–
+
8.6V
V
BIAS
V
+V
REF
DD
IN
FB
14
(20)
10 (14)
REF
GEN
1 (2)
Current
Sources
6 (9)
2 (3)
Pre-regulator/Startup
13
(18)9(12)
2V
1.2V
8.1V
–
+
+
–
–
+
OSC
8
(11)
Current-mode
Comparator
C/L
Comparator
Undervoltage
Comparator
In
OSC
OSC
Out
(10)
R
S
7
TQ
9103
Q
V
DD
9100
9102
(5) 3
Drain
(8) 5
-V
IN
V
DD
S
Q
R
(7) 4
(16) 11
(17) 12
Source
Shutdown
Reset
Pin numbers in parentheses are for PLCC pacage.
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Page 5
Typical Performance Curves
HV9100/HV9102/HV9103
Fig. 1
Fig. 2
PSRR – Error Amplifier and Reference
0
-10
-20
-30
-40
(dB)(Ω)
-50
-60
-70
-80
10Hz 100Hz 10KHz 1MHz
100KHz1KHz
Error Amplifier Output Impedance (Z0)
6
10
5
10
4
10
3
10
2
10
10
Fig. 3
Fig. 4
OUT
f (Hz)
80
70
60
50
40
30
Open Loop Gain/Phase
Gain (dB)
20
10
0
-10
100Hz 1KHz 10KHz
Output Switching Frequency
1M
100k
vs. Oscillator Resistance
HV9100, 9101, 9102
Error Amplifier
100KHz 1MHz
Frequency
HV9103
180°
120°
60°
-60°
-120°
-180°
0°
Phase
1.0
0.1
.01
100Hz 1KHz 10KHz
Test Circuits
+10V
(V
)
DD
(FB)
Reference
GND
(–V
)
IN
0.1µF
100KHz
Error Amp Z
1.0V swept 100Hz – 2.2MHz
–
+
OUT
V
1
1MHz
Tektronix
P6021
(1 turn
secondary)
10MHz
V
2
60.4K
40.2K
10k
10k
0.1V swept 10Hz – 1MHz
10.0V
4.00V
100K1%
Reference
R
0.1µF
100 k
OSC
PSRR
+
(Ω)
–
100K1%
1M
V
1
V
2
NOTE: Set Feedback Voltage so that
V
COMP
= V
± 1mV before connecting transformer
DIVIDE
5
Page 6
Technical Description
HV9100/HV9102/HV9103
Preregulator
The preregulator/startup circuit for the HV910x consists of a highvoltage N-channel depletion-mode DMOS transistor driven by an
error amplifier to form a controlled current path between the V
terminal and the VDD terminal. Maximum current (about 20 mA)
occurs when V
shuts off altogether when V
and 9.4V, so that if V
= 0, with current reducing as VDD rises. This path
DD
DD
rises to somewhere between 7.8
DD
is held at 10 or 12V by an external source
(generally the supply the chip is controlling) no current other than
leakage is drawn through the high voltage transistor. This minimizes dissipation.
An external capacitor between VDD and VSS is generally required
to store energy used by the chip during the time between shutoff
of the high voltage path and the V
supply’s output rising enough
DD
to take over the powering of the chip. This capacitor generally also
serves as the output filter capacitor for that output from the supply.
1µF is generally sufficient to assure against double-starting.
Capacitors as small as 0.1µF can work when faster response from
the V
line is required. Whatever capacitor is chosen should
DD
have very good high frequency characteristics. Stacked polyester
or ceramic capacitors work well. Electrolytic capacitors are generally not suitable.
A common resistor divider string is used to monitor VDD for both
the undervoltage lockout circuit and the shutoff circuit of the high
voltage FET. Setting the undervoltage sense point about 0.6V
lower on the string than the FET shutoff point guarantees that the
undervoltage lockout always releases before the FET shuts off.
Bias Circuit
An external bias resistor, connected between the bias pin and V
is required to set currents in a series of current mirrors used by the
analog sections of the chip. Nominal external bias current requirement is 15 to 20µA, which can be set by a 390KΩ to 510KΩ
resistor if a 10V V
is used. A precision resistor is NOT required; ± 5% is fine.
V
DD
is used, or a 510KΩ to 680KΩ resistor if a 12V
DD
For extremely low power operation, the value of bias current can
be reduced to as low as 5µA by further increases in the value of
the bias resistor. This will reduce quiescent current by about a
third, reduce bandwidth of the error amp by about half, and slow
the current sense comparator by about 30%.
SS
Clock Oscillator
The clock oscillator of the HV910x consists of a ring of CMOS
inverters, timing capacitors, a capacitor discharge FET, and, in
the 50% maximum duty cycle versions, a frequency dividing flipflop. A single external resistor between the OSC In and OSC Out
pins is required to set oscillator frequency (see Fig. 4). For the
50% maximum duty cycle versions the ‘Discharge’ pin is internally
connected to GND. For the 99% duty cycle version, ‘Discharge’
can either be connected to V
through a resistor used to set a deadtime.
One difference exists between the Supertex HV910x and competitive parts. The oscillator of the HV910x is shut off when a
shutoff command is received. This saves about 150µA of quiescent current, which aids in situations where an absolute minimum
of quiescent power dissipation is required.
directly or connected to V
SS
SS
Reference
The reference consists of a stable bandgap reference followed by
a buffer amplifier which scales the voltage up to approximately
IN
4.0V. The scaling resistors of the reference buffer amplifier are
trimmed during manufacture so that the output of the error
amplifier when connected in a gain of -1 configuration is as close
to 4.000V as possible. This nulls out any input offset of the error
amplifier. As a consequence, even though the observed reference voltage of a specific part may not be exactly 4V, the feedback
voltage required for proper regulation will be 4V.
A resistor of approximately 50KΩ is placed internally between the
output of the reference buffer amplifier and the circuitry it feeds
(reference output pin and NON-INVERTING input to the error
amplifier). This allows overriding the internal reference with a lowimpedance voltage source ≤6V. Using an external reference
reinstates the input offset voltage of the error amplifier, and its
effect of the exact value of feedback voltage required. In general,
because the reference voltage of the Supertex HV910x is not
noisy, as some previous devices have been, overriding the
reference should seldom be necessary.
Because the reference is a high impedance node, and usually
there will be significant electrical noise near it, a bypass capacitor
between the reference pin and V
is strongly recommended. The
SS
reference buffer amplifier is intentionally compensated to be
stable with a capacitive load of 0.01 to 0.1µF.
Error Amplifier
The error amplifier is a true low-power differential input operational amplifier intended for around-the-amplifier compensation.
It is of mixed CMOS-bipolar construction: a PMOS input stage is
used so the common-mode range includes ground and the input
impedance is very high. This is followed by bipolar gain stages
which provide high gain without the electrical noise of all-MOS
amplifiers. The amplifier is unity-gain stable.
Current Sense Comparators
The HV910x uses a true dual comparator system with independent comparators for modulation and current limiting. This allows
the designer greater latitude in compensation design, as there are
no clamps (except ESD protection) on the compensation pin. Like
the error amplifier, the comparators are of low-noise BiCMOS
construction.
Remote Shutdown
The shutdown and reset pins can be used to perform either
latching or non-latching shutdown of a converter as required.
These pins have internal current source pull-ups so they can be
driven from open-drain logic. When not used, they should be left
open, or connected to V
DD
.
Main Switch
The main switch is a normal N-channel power MOSFET. Unlike
the situation with competitive devices, the body diode can be used
if desired without destroying the chip.
6
Page 7
Pinout
HV9100/HV9102/HV9103
BIAS
+V
Drain
Source
–V
V
DD
OSC Out
COMP
Reset
Shutdown
18 17 16
1
2
IN
3
4
5
IN
6
7
14
13
12
11
10
9
8
Feedback
COMP
Reset
Shutdown
V
REF
Discharge
OSC In
NC
Feedback
NC
BIAS
+V
19
20
1
•
2
3
IN
15 14
NC
V
REF
13
NC
12
Discharge
OSC In
11
OSC Out
10
V
9
DD
top view
14-pin DIP
4 5 6
NC
Drain
top view
20-pin PJ Package
NC
7 8
IN
–V
Source
©2001 Supertex Inc. All rights reserved. Unauthorized use or reproduction prohibited.
11/12/01
1235 Bordeaux Drive, Sunnyvale, CA 94089
TEL: (408) 744-0100 • FAX: (408) 222-4895
7
www.supertex.com
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