Datasheet HV510WG, HV510X Datasheet (Supertex)

240V, 12-Channel Serial to Parallel Converter

with High Voltage Push-Pull Outputs

Ordering Information

Package Options

Recommended Operating

Device VPP Max 24 Lead SOW Die

HV510 240V HV510WG HV510X

HV510

Features

❏ HVCMOS® technology

❏ Operating output voltage of 240V

❏ Low power level shifting from 5V to 240V

❏ Shift register speed 8MHz @ V

❏ 12 latched data outputs

❏ Output polarity and blanking

❏ CMOS compatible inputs

❏ Forward and reverse shifting options

Absolute Maximum Ratings

Supply voltage, V Supply voltage, V Logic input levels -0.5V to V Ground current High voltage supply current Continuous total power dissipation Operating temperature range -40°C to +85°C Storage temperature range -65°C to +150°C

Notes:

1. All voltages are referenced to GND.

2. Connection to all power and ground pads is required. Duty cycle is limited by the total power dissipated in the package.

3. For operation above 25°C ambient derate linearly to 85°C at 12mW/°C.

DD

PP

3

2

DD

3

= 5V

1

-0.5V to +6V V

to 260V

DD

+0.5V

DD

0.3A

0.25A

750mW

General Description

The HV510 is a low voltage serial to high voltage parallel converter with 12 high voltage push-pull outputs. This device has been designed to drive small capacitive loads such as piezo electric transducers. It can also be used in any application requiring multiple high voltage outputs, low current sourcing and sinking capabilities.

The device consists of a 12-bit shift register, 12 latches, and control logic to perform the polarity select and blanking of the outputs. A DIR pin controls the direction of data shift through the device. With DIR grounded, D data is shifted from HV

is Data In and D

D

IOB

HV

1 to HV

OUT

IOA

12. Data is shifted through the shift register on

is Data In and D

IOA

12 to HV

1. When DIR is at logic high,

OUT

is Data Out: data is then shifted from

the low to high transition of the clock. Data output buffers are provided for cascading devices. Operation of the shift register is not affected by the LE, BL, or the POL inputs. Transfer of data from the shift register to the latch occurs when the LE is high. The data in the latch is stored during LE transition from high to low.

is Data Out;

IOB

12/13/01

Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability indemnification insurance agreement." Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of devices determined to be defective due to workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications, refer to the Supertex website: http://www.supertex.com. For complete liability information on all Supertex products, refer to the most current databook or to the Legal/Disclaimer page on the Supertex website.

1

HV510

Electrical Characteristics (for V

= 5V, VPP = 240V, TA = 250C)

DD

DC Characteristics

Symbol Parameter Min Typ Max Units Conditions

I

DD

I

DDQ

I

PP

I

IH

I

IL

V

I

OH

OL

OC

VDD supply current 4 mA f

Quiescent VDD supply current 200 µA All VIN = 0V or V High voltage supply current 0.25 mA VPP = 240V All outputs high

0.25 mA V High-level logic input current 10 µAVIH = V Low-level logic input current -10 µAVIL = 0V High-level output

HV

Data out V

Low-level output HV

OUT

220 V VPP = 240V, IHV 175 V V

-1V V I

DD

25 V VDD = 5V, IHV

Data out 1.0 V I

HV

clamp voltage VPP +1.5 V IOL = 1mA

OUT

-1.5 V I

Output Source Current 1.0 mA VPP = 240V

0.8 mA VPP = 200V

= 8MHz, f

CLK

LE = LOW

= 240V All outputs low

PP

= 200V, lHV

PP

= -100µA

DOUT

= 100µA

DOUT

= -1mA

OL

DD

DATA

OUT

= 4MHz

DD

= -0.5mA

OUT

= -0.5mA

OUT

= 1mA

AC Characteristics

1

(For V

= 5V, VPP = 200V, TA = 25°C)

DD

Symbol Parameter Min Typ Max Units Conditions

f

CLK

t

W

t

SU

t

H

t

WLE

t

DLE

t

SLE

, t

t

ON

OFF

t

DHL

t

DLH

, t

t

r

f

Note:

1. Shift register speed can be as low as DC as long as Data Set-up and Hold Time meet the spec.

Clock frequency 8 MHz Clock width high and low 62 ns Data setup time before clock rises 35 ns Data hold time after clock rises 30 ns Width of latch enable pulse 80 ns LE delay time after rising edge of clock 35 ns LE setup time before rising edge of clock 40 ns Time from latch enable to HV

OUT

6.0 µsC

= 20pF

L

Delay time clock to data out high to low 125 ns CL = 20pF Delay time clock to data out low to high 125 ns CL = 20pF All logic inputs 5 ns

Recommended Operating Conditions

Symbol Parameter Min Typ Max Units

V

DD

V

PP

V

IH

V

IL

T

A

Notes:

Power-up sequence should be the following:

1. Connect ground. 4. Apply V

2. Apply V

3. Set all inputs (Data, CLK, Enable, etc.) to a known state.

Power-down sequence should be the reverse of the above.

.5.The VPP should not drop below VDD or float during operation.

DD

Logic supply voltage 4.5 5.0 5.5 V High voltage supply 60 240 V High-level input voltage VDD -0.9 V Low-level input voltage 0 0.9 V Operating free-air temperature -40 +85 °C

.

PP

DD

V

2

Input and Output Equivalent Circuits

HV510

V

DD

Input

GND

Logic Inputs

Switching Waveforms

(D

IOA/DIOB

Data Out

(D

IOA/DIOB

CLK

)

50% 50% 50%

)

t

WL

V

GND

DD

t

SU

Logic Data Output

Data Valid50% 50%Data In

V

PP

Data Out

HVGND

High Voltage Outputs

t

H

HV

OUT

V

IH

V

IL

V

IH

50%

V

t

WH

IL

V

OH

50%

V

t

DLH

t

50%

DHL

OL

V

OH

V

OL

LE

HV

OUT

w/ S/R LOW

HV

OUT

w/ S/R HIGH

3

t

DLE

50%

t

ON

OFF

t

WLE

10%

90%

10%

90%

50%

t

SLE

V

IH

V

OL

V

OH

V

OL

V

OH

V

OL

Functional Block Diagram

POL

BL LE

D

IOA

L/T

HV510

V

PP

HV

1

OUT

CLK

L/T

HV

OUT

2

•

8 Additional

Outputs

•

DIR

12-bit

Static Shift

Register

12 Latches

•

HV

OUT

11

12

L/T

D

IOB

L/T = Level Translator

Function Table

Inputs Outputs

Function Shift Reg HV Outputs Data Out

All on X X X L L X * *…*HH…H* All off X X X L H X * *…*L L…L* Invert mode X X L H L X * *…** *…** Load S/R H or L ↑ LHHXH or L *…** *…**

Store data in latches

Transparent latch mode

I/O relation

Notes:

H = high level, L = low level, X = irrelevant, ↑ = low-to-high transition, ↓ = high-to-low transition. * = dependent on previous stage’s state before the last CLK or last LE high.

Data CLK LE BL POL DIR

12…12 1 2…12 *

XX↓ HHX **…** *…** XX↓ HLX**…** *…** L ↑ HHHXL*…*L *…** H ↑ HHHXH*…*H *…**

D

IOA

D

IOB

↑ XXXLQ ↑ XXXHQ

→ Q

n

→ Q

n

n+1

n-1

—D —D

IOB

IOA

4

HV510

Pin Configurations

HV510 24 Pin SOW Package

Pin Function

1V 2D 3BL 4 POL 5V 6 DIR 7 LGND 8 HVGND 9 CLK 10 LE 11 D 12 V 13 HV 14 HV 15 HV 16 HV 17 HV 18 HV 19 HV 20 HV 21 HV 22 HV 23 HV 24 HV

PP

IOA

DD

IOB

PP

OUT

12/1 11/2 10/3 9/4 8/5 7/6 6/7 5/8 4/9 3/10 2/11 1/12

Package Outline

1

2

3

4

5

6

7

8

9

10

11

12

top view

24-pin SOW

24 23

22

21

20

19

18

17

16 15

14

13

Note:

Pin designation for DIR = H/L

Example: for DIR = H, Pin 13 is HV

for DIR = L, Pin 13 is HV

OUT

12

1

5