Datasheet HUF76121P3, HUF76121S3S Datasheet (Fairchild Semiconductor)

HUF76121P3, HUF76121S3S

Data Sheet January 2003

47A, 30V, 0.021 Ohm, N-Channel, Logic
Level UltraFET Power MOSFETs

These N-Channel pow er MOSFETs
are manufactured using the
innovati ve UltraFET™ process.

This advanced process technology
achieves the lowest possible on-resistance per silicon ar ea,
resultin g in outstanding performance. This device is capab le
of withstanding hi gh energy in the avalanche mode and the
diode exhibits very low reverse recovery time and stored
charge. It was design ed for use in applicati ons where power
efficiency is important, such as switching regulators,
switchi ng converters, motor drivers, relay drivers , low­voltage bus switches, and power manage me nt i n po rtab le
and battery-operated products.

Formerly developmental ty pe TA76121.

Ordering Information

PART NUMBER PACKAGE BRAND

HUF76121P3 TO-220AB 76121P
HUF76121S3S TO-263AB 76121S

NOTE: When ordering, use the entire part number. Add the suffix T to
obtain the TO-263AB variant in tape and reel, e.g., HUF76121S3ST.

Features

• Logic Level Gate Drive

• 47A, 30V

• Ultra Low On-Resistance, r

• Temperatur e Compensating PSPICE

• Temperatur e Compensating SABER

DS(ON)

= 0.021Ω

®

Model

©

Model

• Thermal Impedance SPICE Model

• Thermal Impedance SABER Model

• Peak Current vs Pulse Width Curve

• UIS Rating Curve

• Related Literature

- TB334, “Guidelines for Soldering Surface Mount
Components to PC Boards”

Symbol

D

G

S

Packaging

DRAIN

(FLANGE)

JEDEC TO-220AB JEDEC TO-263AB

SOURCE

DRAIN

GATE

GATE

SOURCE

(FLANGE)

DRAIN

©2003 Fairchild Semiconductor Corporation HUF76121P3, HUF76121S3S Rev. C1

HUF76121P3, HUF76121S3S

Absolute Maximum Ratings T

= 25oC, Unless Otherwise Specified

C

UNITS

Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

Drain to Gat e Voltage (R

= 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

GS

Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

DSS

DGR

GS

30 V
30 V

±20 V

Drain Curr e nt

Continuous (T

Continuous (TC = 100oC, VGS = 5V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I

= 25oC, VGS = 10V) (Figure 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I

C

Continuous (TC = 100oC, VGS = 4.5V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I

Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I

Pulsed Avalanche Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P

Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T

, T

J

STG

D
D
D

DM

AS

D

47
25
24

Figure 4

Figures 6, 17,18

75

0.6

-40 to 150

Maximum Temperature for Soldering

Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .T

Package Body for 10s, See Techbrief 334. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T

CAUTION: Stresses above those listed in “Absolute Maximum Rati ngs” may cause permane nt damage to the device. This is a stress only rating and oper ation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

L

pkg

300
260

A
A
A

W

W/oC

o

C

o

C

o

C

NOTE:

= 25oC to 150oC.

1. T

J

Electrical Specifications T

= 25oC, Unless Otherwise Specified

A

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

OFF STATE SPECIFICATIONS

Drain t o Source Breakdown Voltage BV
Zero Gat e V ol tag e D rain Curre nt I

Gate to Sour c e Le ak ag e C urr e nt I

ON STATE SPECIFICATIONS

Gate to Source Threshold Voltage V
Drain to Source On Resistance r

GS(TH)VGS

DS(ON)ID

THERMAL SPECIFICATIONS

Thermal R esis ta nc e Ju ncti on to Case R
Thermal Resistance Junction to Ambient R
SWITCHING SPECIFICATIONS (V

GS

= 4.5V)
Turn-On Time t
Turn-On Delay Time t

d(ON)

Rise Time t
Turn-Off Delay Time t

d(OFF)

Fall Time t
Turn-Off Time t

DSSID

DSS

GSS

θJC

θJA

ON

r

f

OFF

= 250µA, VGS = 0V (Figure 12) 30 - - V
VDS = 25V, VGS = 0V - - 1 µA
V

= 25V, VGS = 0V, TC = 150oC--250µA

DS

VGS = ±20V - - ±100 nA

= VDS, ID = 250µA (Figur e 11) 1 - 3 V

= 47A, VGS = 10V (Figures 9, 10) - 0.01 5 0.021 Ω
I

= 25A, VGS = 5V (Figure 9) - 0.019 0.028 Ω

D

I

= 24A, VGS = 4.5V (Figure 9) - 0.021 0.031 Ω

D

(Figur e 3) - - 1. 66
TO-22 0 and TO-263 - - 62

VDD = 15V, ID ≅ 24A, RL = 0.63Ω,
V

= 4.5V, RGS = 10.0Ω

GS

(Figures 15, 21 , 22)

--265ns

-15-ns

o

o

C/W
C/W

-160- ns

-14-ns

-31-ns

--70ns

©2003 Fairchild Semiconductor Corporation HUF76121P3, HUF76121S3S Rev. C1

HUF76121P3, HUF76121S3S

Electrical Specifications T

= 25oC, Unless Otherwise Specified (Continue d)

A

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

SWITCHING SPECIFICATIONS (VGS = 10V)

Turn-On Time t
Turn-On Delay Time t
Rise Time t
Turn-Off Delay Time t
Fall Time t
Turn-Off Time t

GATE CHARGE SPECIFICATIONS

Total Gate Charg e Q
Gate Charge at 5V Q
Threshold Gat e Ch arg e Q
Gate to Source Gate Charg e Q
Gate to Drai n “M ill er ” C ha r ge Q

CAPACITANCE SPECIFICATIONS

ON

d(ON)

d(OFF)

OFF

g(TOT)VGS

g(5)

g(TH)

VDD = 15V, ID ≅ 47A, RL = 0.32Ω,
V
(Figures 16, 21 , 22)

r

f

VGS = 0V to 5V - 13 16 nC
VGS = 0V to 1V - 1.0 1.2 nC

gs

gd

= 10V, RGS = 12.5Ω

GS

= 0V to 10V VDD = 15V, ID ≅ 25A,

R

= 0.6Ω

L

I

= 1.0mA

g(REF)

(Figures 14, 1 9, 20)

--80ns

-6-ns

-47-ns

-47-ns

-42-ns

--135ns

-2430nC

-2.50- nC

-7.80- nC

Input Capacitance C
Output Capacitance C
Reverse Transfer Capacitance C

ISS

OSS

RSS

Source to Drain Diode Specifications

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Source to Drain Diode Vol tage V
Reverse Recovery Time t
Reverse Recovered Charge Q

SD

rr

RR

Typical Performance Curves

1.2

1.0

0.8

0.6

0.4

0.2

POWER DISSIPATION MULTIPLIER

0

0 25 50 75 100 150

TA, AMBIENT TEMPERATURE (oC)

FIGURE 1. NORMALIZED PO WER DISSIPATION vs CASE

TEMPERATURE

125

VDS = 25V, VGS = 0V, f = 1MHz

-850- pF

(Figur e 13 )

-465- pF

-100- pF

ISD = 25A - - 1.25 V
ISD = 25A, dISD/dt = 100A/µs--65ns
ISD = 25A, dISD/dt = 100A/µs - - 100 nC

50

40

30

VGS = 4.5V

20

, DRAIN CURRENT (A)

D

I

10

0

25

50 75 100 125 150

TC, CASE TEMPERATURE (oC)

VGS = 10V

FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs

CASE TEMPERATURE

©2003 Fairchild Semiconductor Corporation HUF76121P3, HUF76121S3S Rev. C1

HUF76121P3, HUF76121S3S

Typical Performance Curves (Continued)

2

DUTY CYCLE - DESCENDING ORDER

0.5

1

0.2

0.1

0.05

0.02

0.01

0.1

, NORMALIZED

θJC

Z

THERMAL IMPEDANCE

SINGLE PULSE

0.01

-5

10

-4

10

-3

10

FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE

-2

10

t, RECT ANGULAR PULSE DURATION (s)

NOTES:
DUTY FACTOR: D = t
PEAK TJ = PDM x Z

-1

10

P

DM

t

1

t

2

1/t2

x R

JC

θ

10

+ T

JC

C

θ

0

1

10

, PEAK CURRENT (A)

DM

I

1000

100

1000

100

TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION

40

-5

10

VGS = 10V

VGS = 5V

-4

10

-3

10

10

-2

t, PULSE WIDTH (s)

FIGURE 4. PEAK CURRENT CAPABILITY

TJ = MAX RATED

= 25oC

T

C

100µs

500

100

TC = 25oC

FOR TEMPERATURES
ABOVE 25
CURRENT AS FOLLOWS:

-1

10

If R = 0
tAV = (L)(IAS)/(1.3*RATED BV

If R ≠ 0
t

= (L/R) ln [ (IAS*R)/(1.3*RATED BV

AV

o

C DERATE PEAK

25

0

10

- VDD)

DSS

150 - T

125

- VDD) +1]

I = I

DSS

STARTING TJ = 25oC

C

1

10

10

10

, DRAIN CURRENT (A)

D

I

OPERATION IN THIS
AREA MAY BE
LIMITED BY r

1

1 10 100

DS(ON)

, DRAIN TO SOURCE VOLTAGE (V)

V

DS

BV

DSS MAX

= 30V

1ms

10ms

, AVALANCHE CURRENT (A)
I

STARTING TJ = 150oC

AS

1

0.001 0.01 0.1 1 10 100
tAV, TIME IN AVALANCHE (ms)

NO TE: Refer to Fairchild App lication Notes AN9321 and AN9322.

FIGURE 5. FORWARD BIAS SAFE OPERATING AREA

©2003 Fairchild Semiconductor Corporation HUF76121P3, HUF76121S3S Rev. C1

FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING CAPABIL ITY

HUF76121P3, HUF76121S3S

Typical Performance Curves (Continued)

100

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX

80

60

40

, DRAIN CURRENT (A)

D

I

20

0

012345

VGS, GATE TO SOURCE VOLTAGE (V)

25oC

-40oC

V

DD

150oC

= 15V

100

VGS = 10V
V

= 5V

GS

80

60

40

, DRAIN CURRENT (A)

D

I

20

0

012345

VDS, DRAIN TO SOURCE VOLTAGE (V)

FIGURE 7. TRANSFER CHARACTERISTICS FIGURE 8. SATURATION CHARACTERISTICS

40

35

30

25

ID = 47A

ID = 28A

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX

1.6

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
V

= 10V, ID = 47A

GS

1.4

1.2

= 4.5V

V

GS

VGS = 4V

VGS = 3.5V

VGS = 3V

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX

, DRAIN TO SOURCE

20

ON RESISTANCE (mΩ)

DS(ON)

r

ID = 15A

15

10

246810

VGS, GATE TO SOURCE VOLTAGE (V)

FIGURE 9. SOURCE TO DRAIN ON RESISTANCE vs GATE

VOLTAGE AND DRAIN CURRENT

1.2

1.0

0.8

NORMALIZED GATE

THRESHOLD VOLTAGE

0.6

-60 0 60 120 180
TJ, JUNCTION TEMPERATURE (oC)

VGS = VDS, ID = 250µA

ON RESISTANCE

1.0

NORMALIZED DRAIN TO SOURCE

0.8

-60 0 60 120 180
TJ, JUNCTION TEMPERATURE (oC)

FIGURE 10. NORMALIZED DRAIN TO SOURCE ON

RESISTANCE vs JUNCTION TEMPERATURE

1.2
ID = 250µA

1.1

1.0

BREAKOWN VOLTAGE

NORMALIZED DRAIN TO SOURCE

0.9

-60.0 0.0 60.0 120 180
TJ, JUNCTION TEMPERATURE (oC)

FIGURE 11. NORMALIZED GATE THRESHOLD VOL TAGE vs

JUNCTION TEMPERATURE

©2003 Fairchild Semiconductor Corporation HUF76121P3, HUF76121S3S Rev. C1

FIGURE 12. NORMALIZED DRAIN TO SOURCE BREAKDOWN

VOLTAGE vs JUNCTION TEMPERATURE

HUF76121P3, HUF76121S3S

Typical Performance Curves (Continued)

1200

900

C

C

ISS

OSS

V

= 0V, f = 1MHz

GS

C

= CGS + C

ISS

C

= C

RSS

C

≈ CDS + C

OSS

GD

GD

GD

600

C, CAPACITANCE (pF)

300

0

0 5 10 15 20 25 30

C

RSS

VDS, DRAIN TO SOURCE VOLTAGE (V)

FIGURE 13. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE

500

VGS = 4.5V, VDD = 15V, ID = 24A, RL = 0.63Ω

400

300

200

t

SWITCHING TIME (ns)

100

d(OFF)

0

0

10 20 30 40 50

R

, GATE TO SOURCE RESISTANCE (Ω)

GS

t

r

t

d(ON)

t

f

10

8

6

4

WAVEFORMS IN

2

, GATE TO SOURCE VOLTAGE (V)

GS

V

0

0 5 10 15 20 25

VDD = 15V

Q

, GATE CHARGE (nC)

g

DESCENDING ORDER:

ID = 47A

= 28A

I

D

I

= 15A

D

NO TE: Refer to Fairchild App lication Notes AN7254 and AN7260.

FIGURE 14. GATE CHARGE WAVEFORMS FOR CONSTANT

GATE CURRENT

200

VGS = 10V, VDD = 15V, ID = 47A, RL = 0.32Ω

150

100

SWITCHING TIME (ns)

50

0

0

10 20 30 40 50

RGS, GATE TO SOURCE RESISTANCE (Ω)

t

d(OFF)

t

t

t

d(ON)

f

r

FIGURE 15. SWITCHING TIME vs GATE RESISTANCE FIGURE 16. SWITCHING TIME vs GATE RESISTANCE

Test Circuits and Waveforms

V

DS

BV

DSS

L

VARY t

TO OBTAIN

P

REQUIRED PEAK I

V

GS

AS

R

G

+

V

DD

-

DUT

0V

P

I

AS

0.01Ω

0

t

FIGURE 17. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 18. UNCLAMPED ENERGY WAVEFORMS

©2003 Fairchild Semiconductor Corporation HUF76121P3, HUF76121S3S Rev. C1

t

P

I

AS

t

AV

V

DS

V

DD

HUF76121P3, HUF76121S3S

Test Circuits and Waveforms (Continued)

V

DS

R

L

V

GS

DUT

I

g(REF)

FIGURE 19. GATE CHARGE TEST CIRCUIT FIGURE 20. GATE CHARGE WAVEFORMS

+

V

-

DD

V

DD

V

0

I

gREF)

0

GS

V

GS

= 1V

Q

g(TH)

Q

g(TOT)

V

DS

Q

g(5)

V

= 10V

GS

VGS = 5V

V

DS

R

L

V

GS

R

GS

V

GS

DUT

+

V

DD

-

V

DS

0

V

GS

10%

0

t

d(ON)

90%

t

ON

50%

t

10%

r

PULSE WIDTH

FIGURE 21. SWITCHING TIME TEST CIRCUIT FIGURE 22. SWITCHING TIME WAV EFORM

t

d(OFF)

90%

t

OFF

50%

t

f

90%

10%

©2003 Fairchild Semiconductor Corporation HUF76121P3, HUF76121S3S Rev. C1

HUF76121P3, HUF76121S3S

PSPICE Electrical Model

.SUBCKT HUF76121 2 1 3 ; rev March 1998

CA 12 8 1.2e -9
CB 15 14 1.23e-9
CIN 6 8 7.6e-10

DBODY 7 5 DBODYMOD
DBREAK 5 11 DBREAKMOD
DPLCAP 10 5 DPLCAPMOD

EBREAK 11 7 17 18 33.4
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8 1
EVTEMP 20 6 18 22 1

GATE

IT 8 17 1
LDRAIN 2 5 1e- 9

LGATE 1 9 3.57e- 9
LSOURCE 3 7 4.25e-9

MMED 16 6 8 8 MMEDM OD
MSTR O 16 6 8 8 M S T ROMOD
MWEAK 16 21 8 8 MWE AKMOD

RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 2.5e-3
RGATE 9 20 4
RLDRAIN 2 5 10
RLGATE 1 9 35.7
RLSOURCE 3 7 42.5
RSLC1 5 51 RSL CM OD 1e-6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 10e-3
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1

S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD

VBAT 22 19 DC 1

LGATE

1

RLGATE

RGATE

9

CA

ESG

+

EVTEMP

+

-

18
22

20

S1A

12

13

8

S1B

EGS EDS

-

13

10

6
8

+

+

RSLC2

6

S2A

14
13

S2B

6
8

-

-

DPLCAP

EVTHRES

+

19

8

CIN

15

CB

-

+

-

5

51

5

51

RDRAIN

21

MSTRO

14

5
8

RSLC1

+

ESLC

-

50

16

8

MMED

DBREAK

EBREAK

MWEAK

RSOURCE

RBREAK

17 18

IT

8

RVTHRES

LDRAIN

RLDRAIN

11

+

17
18

DBODY

DRAIN

2

-

LSOURCE

7

RLSOURCE

RVTEMP
19

SOURCE

3

-

VBAT

+

22

ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*181),4))}
.MODEL DBOD Y M OD D (IS = 4e-13 RS = 6.3e-3 TRS1 = 1e-3 TRS2 = 3e-6 CJO = 1.33e-9 TT = 2.8e-8 M = 0.4 XTI = 4.3 N = 0. 95 I KF = 5)

.MODEL DBREAKMOD D (RS = 1.05e-1 TRS1 = 0 TRS2 = 2.5e-5)
.MODEL DPLCAPMOD D (CJO = 7.8e-10 IS = 1e-30 N = 10 M = 0.63)
.MODEL MMEDMOD NMOS (VTO = 1.8 KP = 3.5 IS = 1e-3 0 N = 10 TOX = 1 L = 1u W = 1u RG = 4)
.MODEL MSTROM OD NMOS (VTO = 2. 08 K P = 65 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEAKMOD NMOS (VTO = 1.54 KP = 0.1 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 40 RS = 0.1)
.MODEL RBR EAKMOD RES (TC 1 = 9. 7e-4 TC2 = 7e-7)
.MODEL RDRAINMOD RES (TC1 = 1.6e-2 TC2 = 4e-5)
.MODEL RSLC M OD RES (TC1 = 5e- 3 TC2 = 8e-6)
.MODEL RSOURCEMOD RES (TC1 = 0 TC2 = 0)
.MODEL RVTHRESMOD RES (TC = -1.7e-3 TC2 = -4e-6 )
.MODEL RVT EMPMOD R ES (T C1 = -1.2e-3 TC2 = 1e-6)

.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -5 VOFF= -3)
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -3 VOFF= -5)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -0.5 VOFF= 2)
.MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 2 VOFF= -0.5)

.ENDS

NOTE: For further discussi on of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
T emperature Opti ons; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.

©2003 Fairchild Semiconductor Corporation HUF76121P3, HUF76121S3S Rev. C1

HUF76121P3, HUF76121S3S

SABER Electrical Model

REV March 1998
template huf76121 n2, n1, n3

elec trical n2 , n1, n3
{
var i iscl
d..model db odymod = (is = 4e-13 , xti = 4.3, cjo = 1.33e-9, tt = 2.8e-8, n = 0.95, m = 0.4)
d..model dbreakmod = ()
d..model dp lcapmod = (cjo = 7.8e-10, is = 1e-30, n = 10, m = 0.6 3)
m..model mme dm od = (type=_n, vt o = 1. 8, kp = 3.5, is = 1e-30, tox = 1)
m..model mst rongmod = (type=_n, vto = 2.08, kp = 65, is = 1e-30, tox = 1)
m..model mweakmod = (type =_n, vto = 1.54, kp = 0.1, i s = 1e- 30, tox = 1)
sw_vcsp.. mo del s 1am od = (ron = 1e-5, rof f = 0.1, von = -5, voff = -3)
sw_vcsp.. mo del s 1bm od = (ron = 1e-5, rof f = 0.1, von = -3, voff = -5)
sw_vcsp.. mo del s 2am od = (ron = 1e-5, rof f = 0.1, von = -0.5, voff = 2)
sw_vcsp.. mo del s 2bm od = (ron = 1e-5, rof f = 0.1, von = 2, voff = -0.5)

c.ca n12 n8 = 1.2e-9
c.cb n15 n14 = 1.23e-9
c.cin n6 n8 = 7.6e -10

d.dbody n7 n71 = model=dbodymod
d.dbreak n72 n11 = model=dbr eakmod

ESG

d.dplcap n10 n5 = m odel=dplcapmod
i.it n8 n17 = 1

GATE

l.ldrain n2 n5 = 1e-9
l.lgate n1 n9 = 3.57e-9
l.lsource n3 n7 = 4.25e-9

LGATE

1

RLGATE

9

RGATE

EVTEMP
+

20

m.mmed n16 n6 n8 n8 = m odel=mmed m od, l = 1u, w = 1u
m.mstrong n16 n6 n8 n8 = model=m s trongmod, l = 1u, w = 1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l = 1u, w = 1u

res.rbreak n17 n18 = 1, tc1 = 9.7e-4, tc2 = 7e-7
res.rdbody n71 n5 = 6.3e-3, tc1 = 1e-3, tc2 = 3e-6

12

S1A

res.rdbreak n72 n5 = 1.05e-1, tc1 = 0, tc2 = 2.5e- 5
res.rdrain n50 n16 = 2.5e-3, tc 1 = 1.6 e-2, tc2 = 4e-5
res.rgat e n9 n20 = 4
res.rldrai n n2 n5 = 10
res.rlgate n1 n9 = 35.7

S1B

CA

res.rlsource n3 n7 = 42.5
res.rslc1 n5 n51 = 1e-6, tc1 = 5e-3, tc2 = 8e-6
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 10e-3, tc1 = 0, tc2 = 0
res.rvtemp n18 n19 = 1, tc1 = -1.2 e-3, tc2 = 1e-6
res.rvthres n22 n8 = 1, tc1 = -1.7e -3, tc2 = -4e-6

spe.ebreak n11 n7 n17 n18 = 33.4
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
spe.evthres n6 n21 n19 n8 = 1

DPLCAP

10

RSLC2

-

6
8

EVTHRES

+

+

6

-

18
22

S2A

13

14

8

13

S2B

13

+

+

6

EGS EDS

8

-

-

5

RSLC1

51

ISCL

50
RDRAIN

16

21

-

19

8

MSTRO

CIN

15

CB

8

14

+

5
8

-

MMED

RDBREAK

72

DBREAK

11

MWEAK

EBREAK

RSOURCE

RBREAK

17 18

IT

8

RVTHRES

+

17
18

-

7

RVTEMP
19

-

+

22

LDRAIN

RLDRAIN

RDBODY

71

DBODY

LSOURCE

RLSOURCE

VBAT

DRAIN

2

SOURCE

3

sw_vcsp.s1 a n6 n12 n13 n8 = model=s 1amod
sw_vcsp.s1 b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2 a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2 b n13 n15 n14 n13 = mod el= s2bmod

v.vbat n22 n19 = dc = 1
equations {

i (n51->n50) + = iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v (n5,n51))))*((abs(v (n5,n51)*1e6/181))** 4))
}
}

©2003 Fairchild Semiconductor Corporation HUF76121P3, HUF76121S3S Rev. C1

HUF76121P3, HUF76121S3S

SPICE Thermal Model

REV March 1998

HUF76121

CTHERM1 th 6 1.1e-3
CTHERM2 6 5 2.9e-3
CTHERM3 5 4 3.2e-3
CTHERM4 4 3 1.5e-2
CTHERM5 3 2 3.9e-1
CTHERM6 2 tl 2.2

RTHERM1 th 6 1.0e-4
RTHERM2 6 5 2.0e-3
RTHERM3 5 4 3.4e-1
RTHERM4 4 3 4.6e-1
RTHERM5 3 2 1.8e-1
RTHERM6 2 tl 7.0e-2

SABER Thermal Model

Saber thermal model HUF76121
template thermal_model th tl

thermal_c th, tl
{
ctherm.ctherm1 th 6 = 1.1e-3
ctherm.ctherm2 6 5 = 2.9e-3
ctherm.ctherm3 5 4 = 3.2e-3
ctherm.ctherm4 4 3 = 1.5e-2
ctherm.ctherm5 3 2 = 3.9e-1
ctherm.ctherm6 2 tl = 2.2

rtherm.rtherm1 th 6 = 1.0 e-4
rtherm.rtherm2 6 5 = 2.0e -3
rtherm.rtherm3 5 4 = 3.4e -1
rtherm.rtherm4 4 3 = 4.6e -1
rtherm.rtherm5 3 2 = 1.8e -1
rtherm.rtherm6 2 tl = 7.0e-2
}

RTHERM1

RTHERM2

RTHERM3

RTHERM4

RTHERM5

RTHERM6

JUNCTION

th

CTHERM1

6

CTHERM2

5

CTHERM3

4

CTHERM4

3

CTHERM5

2

CTHERM6

CASE

tl

©2003 Fairchild Semiconductor Corporation HUF76121P3, HUF76121S3S Rev. C1

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PRODUCT STATUS DEFINITIONS
Definition of Terms

Datasheet Identification Product Status Definition

Adva nce Information Formative or In

Design

Preliminary First Production This datasheet contai ns preliminary data, and

No Identification Needed Full Production This datasheet contains final specifications. Fairchild

Obsolete Not In Producti on This datasheet contain s specifications on a product

This datasheet contains the design specifications for
product development. Specifications may change in
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supple m entary data will be published at a later date.
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Rev. I2