Datasheet HUF75925D3ST, HUF75925P3 Datasheet (Fairchild Semiconductor)

)

Data Sheet December 2001

11A, 200V, 0.275 Ohm, N-Channel, UltraFET® Power MOSFETs

HUF75925P3, HUF75925D3ST

Packaging

JEDEC TO-220AB JEDEC TO-252AA

HUF75925P3

Symbol

SOURCE

DRAIN

DRAIN (FLANGE)

G

GATE

Features

• Ultra Low On-Resistance

GATE

SOURCE

DRAIN

(FLANGE

-r

• Simulation Models

- Temperature Compensated PSPICE® and SABER™ Electrical Models

- Spice and SABER Thermal Impedance Models

DS(ON)

= 0.275Ω, V

GS

= 10V

- www.fairchildsemi.com

HUF75925D3ST

• Peak Cu rrent vs Pulse Width Curve

• UIS Rating Curve

Ordering Information

D

S

PART NUMBER PACKAGE BRAND

HUF75925P3 TO-220AB 75925P HUF75925D3ST TO-252AA 75925D

NOTE: When ordering, use the entire part number.

Absolute Maximum Ratings

Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

Drain to Gate Voltage (R

Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

Drain Current

Continuous (T

Continuous (TC= 100oC, VGS = 10V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I

Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I

Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UIS Figures 6, 14, 15

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P

Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T

Maximum Temperature for Soldering

Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T

Package Body for 10s, See Techbrief TB334. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T

NOTE:

1. T

= 25oC to 150oC.

J

CAUTION: Stresses above those listed in “ Absolute M aximum Ratings” may cause perm anent damage to th e device. This is a stress onl y rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

C

= 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

GS

= 25oC, VGS = 10V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I

TC = 25oC, Unless Otherwise Specified

HUF75925P3,

HUF75925D3ST UNITS

DSS

DGR

GS

D D

DM

D

, T

J

STG

L

pkg

200 V 200 V ±20 V

11

8

Figure 4

100

1.5

-55 to 175

300 260

A A

W

W/oC

o

C

o

C

o

C

HUF75925P3, HUF75925D3ST

Electrical Specifications

TC = 25oC, Unless Otherwise Specified

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

OFF STATE SPECIFICATIONS

Drain to Source Breakdown Voltage BV Zero Gate Voltage Drain Current I

Gate to Source Leakage Current I

ON STATE SPECIFICATIONS

Gate to Source Threshold Voltage V Drain to Source On Resistance r

THERMAL SPECIFICATIONS

Thermal Resistance Junction to Case R Thermal Resistance Junction to

Ambient

SWITCHING SPECIFICATIONS (V

GS

= 10V) Turn-On Time t Turn-On Delay Time t Rise Time t Turn-Off Delay Time t Fall Time t Turn-Off Time t

GATE CHARGE SPECIFICATIONS

Total Gate Charge Q Gate Charge at 10V Q Threshold Gate Charge Q Gate to Source Gate Charge Q Gate to Drain "Miller" Charge Q

CAPACITANCE SPECIFICATIONS

Input Capacitance C Output Capacitance C Reverse Transfer Capacitance C

DSSID

DSS

VDS = 190V, VGS = 0V - - 1 µA V

GSS

GS(TH)VGS

DS(ON)ID

θJC

R

θJA

VGS = ±20V - - ±100 nA

TO-220 - - 1.5 TO-220 - - 62 TO-252 - - 100

ON

VDD = 100V, ID = 11A V

d(ON)

d(OFF)

OFF

g(TOT)VGS

g(10)

g(TH)

ISS

OSS

RSS

R (Figures 18, 19)

r

f

VGS = 0V to 10V - 32 42 nC VGS = 0V to 2V - 2.0 3.2 nC

gs gd

VDS = 25V, VGS = 0V, f = 1MHz (Figure 12)

= 250µA, VGS = 0V (Figure 11) 200 - - V

= 180V, VGS = 0V, TC = 150oC - - 250 µA

DS

= VDS, ID = 250µA (Figure 10) 2 - 4 V

= 11A, VGS = 10V (Figure 9) - 0.220 0.275 ¾

o o o

- - 45 ns

= 10V,

GS GS

= 12Ω

-9-ns

-21-ns

-60-ns

- 27 - ns

- - 130 ns

= 0V to 20V VDD = 100V,

= 11A,

I

D

I

= 1.0mA

g(REF)

-5978nC

(Figures 13, 16, 17)

-4.0-nC

-11-nC

- 1030 - pF

- 120 - pF

-15-pF

C/W C/W C/W

Source to Drain Diode Specifications

PARAMETER SYMBOL TE ST CONDIT IONS MIN TYP MAX UNITS

Source to Drain Diode Voltage V

Reverse Recovery Time t Reverse Recovered Charge Q

SD

rr

RR

ISD = 11A - - 1.25 V

= 5A - - 1.00 V

I

SD

ISD = 11A, dISD/dt = 100A/µs - - 190 ns ISD = 11A, dISD/dt = 100A/µs - - 940 nC

Typical Performance Curves

5

1

HUF75925P3, HUF75925D3ST

1.2

1.0

0.8

0.6

0.4

0.2

POWER DISSIPATION MULTIPLIER

0

150

0255075100 17

125

TC, CASE TEMPERA TURE (oC)

FIGURE 1. NORMALIZED POWER DISSIP ATION vs CASE

TEMPERATURE

2

DUTY CYCLE - DESCENDING ORDER

0.5

1

0.2

0.1

0.05

0.02

0.01

12

9

V

= 10V

GS

6

, DRAIN CURRENT (A)

3

D

I

0

25 50 75 100 125 150 17

TC, CASE TEMPERA TURE (oC)

FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs

CASE TEMPERATURE

0.1

, NORMALIZED

θJC

Z

THERMAL IMPEDANCE

0.01

-5

10

200

100

, PEAK CURRENT (A)

DM

I

TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION

10

-5

10

VGS = 10V

NOTES:

SINGLE PULSE

-4

10

-3

10

DUTY FACTOR: D = t PEAK TJ = PDM x Z

-2

-1

10

t, RECTANGULAR PULSE DURATION (s)

FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE

-4

10

-3

10

-2

10

-1

10

t, PULSE WIDTH (s)

θJC

1/t2

x R

+ T

C

θJC

TC = 25oC FOR TEMPERATURES

ABOVE 25 CURRENT AS FOLLOWS:

I = I

25

10

P

DM

t

1

t

0

10

o

C DERATE PEAK

175 - T

C

150

0

2

1

10

FIGURE 4. PEAK CURRENT CAPAB ILIT Y

0 5

5

0

HUF75925P3, HUF75925D3ST

Typical Performance Curves

100

10

OPERATION IN THIS AREA MAY BE

1

, DRAIN CURRENT (A)

D

I

0.1

LIMITED BY r

110

DS(ON)

VDS, DRAIN TO SOURCE VOLTAGE (V)

SINGLE PULSE TJ = MAX RATED

T

C

(Continued)

= 25oC

100 50

FIGURE 5. FORWARD BIAS SAFE OPERATING AREA

20

PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX

V

= 15V

DD

15

10

TJ = 175oC

DRAIN CURRENT (A)

5

D,

I

0

234

VGS, GATE TO SOURCE VOLTAGE (V)

100µs

1ms

10ms

TJ = -55oC

TJ = 25oC

100

10

, AVALANCHE CURRENT (A)

AS

I

If R = 0 tAV = (L)(IAS)/(1.3*RATED BV

If R ≠ 0

= (L/R)ln[(IAS*R)/(1.3*RATED BV

t

AV

STARTING TJ = 150oC

1

0.001 0.01 0.1 1 tAV, TIME IN AVALANCHE (ms)

- VDD)

DSS

STARTING TJ = 25oC

- VDD) +1]

NOTE: Refer to Fairchild Application Notes AN9321 and AN9322.

FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING

CAPABILITY

20

15

10

, DRAIN CURRENT (A)

5

D

I

0

01234

VGS = 10V

= 5V

V

GS

PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX

= 25oC

T

C

VDS, DRAIN TO SOURCE VOLTAGE (V)

VGS = 4.5V

10

FIGURE 7. TRANSFER CHARACTERISTICS FIGURE 8. SATURATION CHARACTERISTICS

3.5

PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX

3.0

2.5

2.0

1.5

ON RESISTANCE

1.0

0.5

NORMALIZED DRAIN TO SOURCE

0.0

-80 -40 0 40 80 120 160 20 TJ, JUNCTION TEMPERATURE (oC)

VGS = 10V, ID = 11A

FIGURE 9. NORMALIZED DRAIN TO SOURCE ON

RESISTANCE vs JUNCTION TEMPERATURE

1.2

1.0

0.8

NORMALIZED GATE

THRESHOLD VOLTAGE

0.6

-80 -40 0 40 80 120 160 20 TJ, JUNCTION TEMPERATURE (oC)

VGS = VDS, ID = 250µA

FIGURE 10. NORMALIZED GA TE THRESHOLD VOL TAGE vs

JUNCTION TEMPERATURE

HUF75925P3, HUF75925D3ST

Typical Performance Curves

1.3 ID = 250µA

1.2

1.1

1.0

BREAKDOWN VOLTAGE

NORMALIZED DRAIN TO SOURCE

0.9

-80 -40 0 40 80 120 160 200 TJ, JUNCTION TEMPERATURE (oC)

(Continued)

FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN

VOLTAGE vs JUNCTION TEMPERATURE

10

VDD = 100V

8

3000

1000

C

OSS

100

C, CAPACITANCE (pF)

10

0.1 1 10 100 VDS, DRAIN TO SOURCE VOLTAGE (V)

≅ C

DS

+ C

GD

C

V

RSS

= 0V, f = 1MHz

GS

C

= C

ISS

= C

GD

GS

+ C

GD

200

FIGURE 12. CAPA C ITANCE vs DRAIN TO SOURCE VOLTAGE

, GATE TO SOURCE VOLTAGE (V)

GS

V

NOTE: Refer to Fairchild Application Notes AN7254 and AN7260.

FIGURE 13. GATE CHARGE WAVEFORMS FOR CONSTANT GATE CURRENT

Test Circuits and Wavefo rms

TO OBTAIN

VARY t

P

REQUIRED PEAK I

V

GS

AS

R

G

6

4

WAVEFORMS IN

2

0

0 5 10 15 20 25 30 35

, GATE CHARGE (nC)

Q

g

V

DS

L

+

V

DD

-

DUT

DESCENDING ORDER: ID = 11A

= 5A

I

D

BV

DSS

t

P

I

AS

V

DS

V

DD

0V

P

I

AS

0.01Ω

0

t

AV

t

FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 15. UNCLAMPED ENERGY WAVEFORMS

V

I

HUF75925P3, HUF75925D3ST

Test Circuits and Wavefo rms

V

DS

V

GS

I

g(REF)

FIGURE 16. GATE CHARGE TEST CIRCUIT FIGURE 17. GATE CHARGE WAVEFORMS

V

(Continued)

R

L

DUT

DS

R

L

V

DD

+

V

DD

-

V

GS

0

g(REF)

V

GS

= 2V

Q

g(TH)

Q

gs

Q

V

DS

g(10)

Q

gd

Q

g(TOT)

VGS = 10V

V

= 20

GS

0

t

ON

t

d(ON)

t

V

DS

90%

r

t

d(OFF)

t

OFF

t

f

90%

V

GS

+

V

DD

-

0

10%

DUT

R

GS

V

GS

V

GS

10%

0

50%

PULSE WIDTH

FIGURE 18. SWITCHING TIME TEST CIRCUIT FIGURE 19. SWITCHING TIME WAVEFORM

10%

90%

50%

HUF75925P3, HUF75925D3ST

PSPICE Electrical Model

.SUBCKT HUF75925 2 1 3 ; rev 19 October 2000

CA 12 8 1.6e-9 CB 15 14 1.75e-9 CIN 6 8 9.3e-8

DBODY 7 5 DBODYMOD DBREAK 5 11 D B REAK MOD DPLCAP 10 5 DPLCAPMOD

EBREAK 11 7 17 18 227 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 6 10 6 8 1 EVTHRES 6 21 19 8 1 EVTEMP 20 6 18 22 1

IT 8 17 1 LDRAIN 2 5 1e-9

LGATE 1 9 5.12e-9 LSOURCE 3 7 4.24e-9

GATE

MMED 16 6 8 8 MMEDMOD MSTRO 16 6 8 8 MSTROMOD MWEAK 16 21 8 8 MWEAKMOD

RBREAK 17 18 RBREAKMOD 1 RDRAIN 50 16 RDRAINMOD 1.98e-1 RGATE 9 20 1.61 RLDRAIN 2 5 10 RLGATE 1 9 51.2 RLSOURCE 3 7 42.4 RSLC1 5 51 RSLCMOD 1e-6 RSLC2 5 50 1e3 RSOURCE 8 7 RSOURCEMOD 1e-2 RVTHRES 22 8 RVTHRESMOD 1 RVTEMP 18 19 RVTE MPMOD 1

S1A 6 12 13 8 S1AMOD S1B 13 12 13 8 S1BMOD S2A 6 15 14 13 S2AMOD S2B 13 15 14 13 S2BMOD

VBAT 22 19 DC 1

7

RVTEMP 19

-

+

22

LDRAIN

RLDRAIN

DBODY

LSOURCE

RLSOURCE

VBAT

DRAIN

2

SOURCE

3

DPLCAP

10

RSLC2

-

6

ESG

8

EVTHRES

+

LGATE

1

RLGATE

9

RGATE

CA

EVTEMP

+

18 22

20

S1A

12

13

8

S1B

EGS EDS

+

6

-

S2A

14 13

S2B

13

+

6 8

-

5

RSLC1

51

+

5

ESLC

51

-

50 RDRAIN

16

21

-

19

8

MMED

MSTRO

CIN

15

CB

+

8

14

5 8

-

DBREAK

EBREAK

MWEAK

RSOURCE

RBREAK

17 18

IT

8

RVTHRES

11

+

17 18

-

ESLC 51 50 VALUE={(V (5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*19),2.5))} .MODEL DBODYMOD D (IS = 1e-12 N=1.02 RS = 7.75e-3 TRS1 = 2.5e-3 TRS2 = 2e-5 CJO = 8.5e-10 TT = 9.6e-6 M = 0.61 XTI=5.5)

.MODEL DBREAKMOD D (RS = 4. 2TRS1 = 1e- 3TRS2 = -8.9e-6) .MODEL DPLCAPMOD D (CJO = 1.15e- 9IS = 1e-30 N = 10 M = 0.86) .MODEL MMEDMOD NMOS (VTO = 3.25 KP = 5 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 1.61) .MODEL MSTROMOD NMOS (VTO = 3.65 KP = 28 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u) .MODEL MWEAKM OD NMOS (VTO = 2. 8 KP = 0.05 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 16.1 RS=.1) .MODEL RBREAKMOD RES (TC1 =1.3e- 3TC2 = 2e-6) .MODEL RDRAINMOD RES (TC1 = 1e-2 TC2 = 3.7e-5) .MODEL RSLCMOD RES (TC1 = 4e-3 TC2 = 1e-6) .MODEL RSOURCEMOD RES (TC1 = 1e-3 TC2 = 1e-6) .MODEL RVTHRESMOD RES (TC1 = -2e-3 TC2 = -1.3e-5) .MODEL RVTEMPMOD RES (TC1 = -3e- 3TC2 = 1.9e-6)

.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -7.5 VOFF= -.5) .MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VO N = -.5 VOFF= -7.5) .MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -0.1 VOFF= 0.2) .MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 0.2 VOFF= -0.1 )

.ENDS

NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.

HUF75925P3, HUF75925D3ST

SABER Electrical Model

REV 19 October 2000 template huf75925 n2,n1,n3

electrical n2,n1,n3 { var i iscl dp..model dbodym od = (isl = 1e-12, rs = 7.75e-3, xt i = 5.5, trs1 = 2.5e-3, trs2 = 2e-5, cjo = 8.5e-10, tt = 9.6e-6, m = 0.61) dp..model dbreakmod = (rs = 4.2, trs1 = 1e-3, trs2 = -8.9e-6) dp..model dplcapmod = (c jo = 1.15e-9, isl = 10e-30, nl=10, m = 0. 86) m..model mmedmod = (typ e=_n, vto = 3.25, kp = 5, isl = 1e-3 0, tox = 1) m..model mstrongmod = (type=_n, vto = 3.65, kp = 28, isl = 1e-30, tox = 1) m..model mweakmod = (type=_ n, vto = 2.8, kp = 0.05, isl = 1e-30, tox = 1, rs=0.1) sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -7.5, voff = -.5) sw_vcsp..model s1bmod = (ron =1e-5, roff = 0.1, von = -.5, voff = -7.5) sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -0.1, voff = 0.2) sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0.2, voff = -0.1)

c.ca n12 n8 = 1.6e-9 c.cb n15 n14 = 1.75e-9 c.cin n6 n8 = 9.3e-8

dp.dbody n7 n5 = model=dbodymod dp.dbreak n5 n11 = model=dbreakmod dp.dplcap n10 n5 = model=dplcapmod

i.it n8 n17 = 1 l.ldrain n2 n5 = 1e-9

l.lgate n1 n9 = 5.12e-9 l.lsource n3 n7 = 4.24e-9

GATE

LGATE

1

RLGATE

RGATE

9

m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u

res.rbreak n17 n18 = 1, tc1 = 1.3e-3, tc2 = 2e-6 res.rdrain n50 n16 = 1.98e-5, tc1 = 1e-2, tc2 =3.7e-5 res.rgate n9 n20 = 1.61 res.rldrain n2 n5 = 10 res.rlgate n1 n9 = 51.2 res.rlsource n3 n7 = 42.4 res.rslc1 n5 n51= 1e-6, tc1 = 4e-3, tc2 = -1e-6

CA

res.rslc2 n5 n50 = 1e3 res.rsource n8 n7 = 10e-3, tc1 = 1e-3, tc2 =1e-6 res.rvtemp n18 n19 = 1, tc1 = -2e-3, tc2 = -1.3e-5 res.rvthres n22 n 8 = 1, tc1 = -3e-3, tc2 = 1.9e-6

spe.ebreak n11 n7 n17 n18 = 227 spe.eds n14 n8 n5 n8 = 1 spe.egs n13 n8 n6 n8 = 1 spe.esg n6 n10 n6 n8 = 1 spe.evtemp n20 n6 n18 n22 = 1 spe.evthres n6 n21 n19 n8 = 1

sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod

v.vbat n22 n19 = dc =1

ESG

EVTEMP +

18 22

20

S1A

12

13

S1B

EGS EDS

DPLCAP

10

RSLC2

-

6 8

EVTHRES

+

6

-

S2A

14 13

8

S2B

13

+

6 8

-

5

RSLC1

51

ISCL

MMED

DBREAK

MWEAK

EBREAK

RSOURCE

17 18

IT

8

50 RDRAIN

16

21

-

19

8

MSTRO

CIN

15

CB

8

14

+

5 8

-

11

+

17 18

-

RBREAK

RVTHRES

7

RLSOURCE

RVTEMP 19

-

+

22

LDRAIN

RLDRAIN

DBODY

LSOURCE

VBAT

DRAIN

2

SOURCE

3

equations { i (n51->n50) +=iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51) )))*((abs(v(n5,n51)*1e6*19))** 2 .5)) } }

SPICE Thermal Model

REV 19 October 2000

HUF75925T

CTHERM1 th 6 8.0e-4 CTHERM2 6 5 2.6e-3 CTHERM3 5 4 3.5e-3 CTHERM4 4 3 5.2e-3 CTHERM5 3 2 7.0e-3 CTHERM6 2 tl 3.3e-2

RTHERM1 th 6 1.0e-3 RTHERM2 6 5 4.5e-3 RTHERM3 5 4 4.2e-2 RTHERM4 4 3 2.5e-1 RTHERM5 3 2 3.9e-1 RTHERM6 2 tl 5.0e-1

HUF75925P3, HUF75925D3ST

RTHERM1

RTHERM2

JUNCTION

th

CTHERM1

6

CTHERM2

5

SABER Thermal Model

SABER thermal model HUF75925T template thermal_model th tl

thermal_c th, tl { ctherm.ctherm1 th 6 = 8.0e-4 ctherm.ctherm2 6 5 = 2.6e-3 ctherm.ctherm3 5 4 = 3.5e-3 ctherm.ctherm4 4 3 = 5.2e-3 ctherm.ctherm5 3 2 = 7.0e-3 ctherm.ctherm6 2 tl = 3.3e-2

rtherm.rtherm1 th 6 = 1.0e-3 rtherm.rtherm2 6 5 = 4.5e-3 rtherm.rtherm3 5 4 = 4.2e-2 rtherm.rtherm4 4 3 = 2.5e-1 rtherm.rtherm5 3 2 = 3.9e-1 rtherm.rtherm6 2 tl = 5.0e-1 }

RTHERM3

RTHERM4

RTHERM5

RTHERM6

CTHERM3

4

CTHERM4

3

CTHERM5

2

CTHERM6

tl

CASE

TRADEMARKS

The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks.

ACEx™ Bottomless™ CoolFET™ CROSSVOLT™ DenseTrench™ DOME™ EcoSPARK™ E2CMOS EnSigna

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FACT™ FACT Quiet Series™

STAR*POWER is used under license

FAST FASTr™ FRFET™ GlobalOptoisolator™ GTO™ HiSeC™ ISOPLANAR™ LittleFET™ MicroFET™ MicroPak™ MICROWIRE™

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OPTOLOGIC™ OPTOPLANAR™ PACMAN™ POP™ Power247™ PowerTrench

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QFET™ QS™ QT Optoelectronics™ Quiet Series™ SILENT SWITCHER

SMART START™ STAR*POWER™ Stealth™ SuperSOT™-3 SuperSOT™-6 SuperSOT™-8 SyncFET™ TinyLogic™ TruTranslation™ UHC™

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UltraFET

VCX™

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DISCLAIMER

FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user.

PRODUCT STATUS DEFINITIONS Definition of Terms

Datasheet Identification Product Status Definition

Advance Information

Preliminary

No Identification Needed

Formative or In Design

First Production

Full Production

2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or

effectiveness.

This datasheet contains the design specifications for product development. Specifications may change in any manner without notice.

This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design.

This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design.

Obsolete

Not In Production

This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only.

Rev. H4