Datasheet HUF75631S3ST Datasheet (Fairchild)

查询HUF75631S3ST供应商

Data Sheet December 2001

33A, 100V, 0.040 Ohm, N-Channel, UltraFET® Power MOSFETs

Packaging

HUF75631P3, HUF75631S3ST

JEDEC TO-220AB JEDEC TO-263AB

DRAIN

(FLANGE)

DRAIN

(FLANGE)

HUF75631P3

SOURCE

DRAIN

GATE

SOURCE

HUF75631S3ST

Features

• Ultra Low On-Resistan ce

-r

• Simulation Models

- Temperature Compensated PSPICE® and SABER™ Electrical Models

- Spice and SABER Thermal Impedance Models

- www.fairchildsemi.com

DS(ON)

= 0.040Ω, V

GS

= 10V

• Peak Cu rrent vs Pulse Width Curve

• UIS Rating Curve

Symbol

Ordering Information

D

G

S

Absolute Maximum Ratings

Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

Drain to Gate Voltage (R

Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V

Drain Current

Continuous (T

Continuous (TC = 100oC, VGS = 10V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I

Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I

Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UIS Figures 6, 14, 15

Power Dissipation 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P

Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T

Maximum Temperature for Soldering

Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T

Package Body for 10s, See Techbrief TB334. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T

NOTE:

= 25oC to 150oC.

1. T

J

CAUTION: Stresses above those listed in “ Absolute M aximum Ratings” may cause perm anent damage to the device. This is a stress on ly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

C

= 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V

GS

= 25oC, VGS = 10V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I

TC = 25oC, Unless Otherwise Specified

PART NUMBER PACKAGE BRAND

HUF75631P3 TO-220AB 75631P HUF75631S3ST TO-263AB 75631S

NOTE: When ordering, use the entire part number, e.g., HUF75631S3ST.

HUF75631P3

HUF75631S3ST UNITS

DSS

DGR

GS

D D

DM

D

, T

J

STG

L

pkg

100 V 100 V ±20 V

33 23

Figure 4

120

0.80

-55 to 175

300 260

A A

W

W/oC

o

C

o

C

o

C

Product reliability information can be found at http://www.fairchildsemi.com/products/discrete/reliability/index.html

All Fairchild semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality systems certification.

For severe environments, see our Automotive HUFA series.

HUF75631P3, HUF75631S3ST

Electrical Specifications

TC = 25oC, Unless Otherwise Specified

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

OFF STATE SPECIFICATIONS

Drain to Source Breakdown Voltage BV Zero Gate Voltage Drain Current I

Gate to Source Leakage Current I

ON STATE SPECIFICATIONS

Gate to Source Threshold Voltage V Drain to Source On Resistance r

THERMAL SPECIFICATIONS

Thermal Resistance Junction to Case R Thermal Resistance Junction to

Ambient SWITCHING SPECIFICATIONS (V

GS

= 10V) Turn-On Time t Turn-On Delay Time t Rise Time t Turn-Off Delay Time t Fall Time t Turn-Off Time t

GATE CHARGE SPECIFICATIONS

DSSID

DSS

GSS

GS(TH)VGS

DS(ON)ID

θJC

R

θJA

ON

d(ON)

VDS = 95V, VGS = 0V - - 1 µA V

DS

VGS = ±20V - - ±100 nA

TO-220, TO-263 - - 1.25

VDD = 50V, ID = 33A V

GS

R

GS

(Figures 18, 19)

r

d(OFF)

f

OFF

= 250µA, VGS = 0V (Figure 11) 100 - - V

= 90V, VGS = 0V, TC = 150oC - - 250 µA

= VDS, ID = 250µA (Figure 10) 2 - 4 V

= 33A, VGS = 10V (Figure 9) - 0.033 0.040 Ω

o

C/W

--62oC/W

- - 100 ns

= 10V,

= 9.1Ω

-9.5-ns

-57-ns

-40-ns

- 55 - ns

- - 145 ns

Total Gate Charge Q Gate Charge at 10V Q Threshold Gate Charge Q

g(TOT)VGS

g(10)

g(TH)

Gate to Source Gate Charge Q Gate to Drain “Miller” Charge Q

CAPACITANCE SPECIFICATIONS

Input Capacitance C Output Capacitance C Reverse Transfer Capacitance C

ISS

OSS

RSS

Source to Drain Diode Specifications

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Source to Drain Diode Voltage V

Reverse Recovery Time t Reverse Recovered Charge Q

SD

RR

= 0V to 20V VDD = 50V,

= 33A,

I

VGS = 0V to 10V - 35 42 nC VGS = 0V to 2V - 2.4 2.9 nC

gs

gd

D

I

= 1.0mA

g(REF)

(Figures 13, 16, 17)

VDS = 25V, VGS = 0V,

-6679nC

-5.4-nC

-13-nC

- 1220 - pF f = 1MHz (Figure 12)

- 295 - pF

- 100 - pF

ISD = 33A - - 1.25 V I

= 17A - - 1.00 V

SD

rr

ISD = 33A, dISD/dt = 100A/µs - - 112 ns ISD = 33A, dISD/dt = 100A/µs - - 400 nC

Typical Performance Curves

5

HUF75631P3, HUF75631S3ST

1.2

1.0

0.8

0.6

0.4

0.2

POWER DISSIPATION MULTIPLIER

0

0 25 50 75 100 17

125

150

TC, CASE TEMPERATURE (oC)

FIGURE 1. NORMALIZED POWER DISSIP A TI ON vs CASE

TEMPERATURE

2

DUTY CYCLE - DESCENDING ORDER

0.5

1

0.2

0.1

0.05

0.02

0.01

0.1

, NORMALIZED

θJC

Z

THERMAL IMPEDANCE

SINGLE PULSE

0.01

-5

10

-4

10

-3

10

t, RECTANGULAR PULSE DURATION (s)

40

30

V

GS

20

, DRAIN CURRENT (A)

D

I

10

0

25

50 75 100 125 150

TC, CASE TEMPERATURE (oC)

FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs

CASE TEMPERATURE

P

DM

t

1

NOTES: DUTY FACTOR: D = t

PEAK TJ = PDM x Z

-2

10

-1

10

θJC

10

1/t2

0

x R

θJC

+ T

= 10V

t

2

17

C

1

10

FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE

600

100

, PEAK CURRENT (A)

DM

I

TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION

20

-5

10

VGS = 10V

-4

10

-3

10

-2

10

-1

10

t, PULSE WIDTH (s)

TC = 25oC FOR TEMPERATURES ABOVE 25

o

C DERATE PEAK

CURRENT AS FOLLOWS:

175 - T

I = I

25

0

10

C

150

10

FIGURE 4. PEAK CURRE NT CAPAB ILITY

1

0

1

6

4

0

HUF75631P3, HUF75631S3ST

Typical Performance Curves

300

100

10

OPERATION IN THIS AREA MAY BE

, DRAIN CURRENT (A)

LIMITED BY r

D

I

1

DS(ON)

10 30

V

, DRAIN TO SOURCE VOLTAGE (V)

DS

(Continued)

SINGLE PULSE TJ = MAX RATED

T

C

FIGURE 5. FORWARD BIAS SAFE OPERATING AREA

60

PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX

= 15V

V

DD

= 25oC

100

100µs

1ms

10ms

200

100

, AVALANCHE CURRENT (A)

AS

I

10

0.001 0.01 0.1

If R = 0 tAV = (L)(IAS)/(1.3*RATED BV

If R ≠ 0

= (L/R)ln[(IAS*R)/(1.3*RATED BV

t

AV

STARTING TJ = 150oC

tAV, TIME IN AVALANCHE (ms)

- VDD)

DSS

- VDD) +1]

DSS

STARTING TJ = 25oC

NOTE: Refer to Fairchild Application Notes AN9321 and AN9322.

FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING

CAPABILITY

60

VGS = 20V V

= 10V

GS

VGS = 7V V

= 6V

GS

40

20

DRAIN CURRENT (A)

D,

I

0

234

VGS, GATE TO SOURCE VOLTAGE (V)

TJ = 175oC

TJ = -55oC

TJ = 25oC

5

40

20

, DRAIN CURRENT (A)

D

I

0

01 2 3

VDS, DRAIN TO SOURCE VOLTAGE (V)

PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX

T

FIGURE 7. TRANSFER CHARACTERISTICS FIGURE 8. SATURATION CHARACTERISTICS

3.0

PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX

2.5

2.0

1.5

ON RESISTANCE

1.0

NORMALIZED DRAIN TO SOURCE

0.5

-80 -40 0 40 80 120 20 TJ, JUNCTION TEMPERATURE (oC)

VGS = 10V, ID = 33A

160

1.2

1.0

0.8

NORMALIZED GATE

THRESHOLD VOLTAGE

0.6

-80 -40 0 40 80 120 20 TJ, JUNCTION TEMPERATURE (oC)

VGS = 5V

= 25oC

C

VGS = VDS, ID = 250µA

160

FIGURE 9. NORMALIZED DRAIN TO SOURCE ON

RESISTANCE vs JUNCTION TEMPERATURE

FIGURE 10. NORMALIZED GA TE THRESHOLD VOLTAGE vs

JUNCTION TEMPERATURE

0

HUF75631P3, HUF75631S3ST

Typical Performance Curves

1.2 ID = 250µA

1.1

1.0

BREAKDOWN VOLTAGE

NORMALIZED DRAIN TO SOURCE

0.9

-80 -40 0 40 80 120 20 TJ, JUNCTION TEMPERATURE (oC)

(Continued)

160160

FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN

VOLTAGE vs JUNCTION TEMPERATURE

10

VDD = 50V

8

6

4000

1000

C

OSS

100

C, CAPACITANCE (pF)

20

0.1 1.0 10 10 VDS, DRAIN TO SOURCE VOLTAGE (V)

≅ C

DS

+ C

GD

C

V

C

RSS

= 0V, f = 1MHz

GS

= C

ISS

GS

= C

GD

+ C

GD

FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE

4

WAVEF ORMS IN

2

, GATE TO SOURCE VOLTAGE (V)

GS

V

0

01020304

, GATE CHARGE (nC)

Q

g

DESCENDING ORDER:

ID = 33A

= 17A

I

D

NOTE: Refer to Fairchild Application Notes AN7254 and AN7260.

FIGURE 13. GATE CHARGE WAVEFORMS FOR CONSTANT GATE CURRENT

V

I

HUF75631P3, HUF75631S3ST

Test Circuits and Waveforms

V

DS

BV

DSS

L

TO OBTAIN

VARY t

P

REQUIRED PEAK I

V

GS

AS

R

G

+

V

DD

-

DUT

0V

P

I

AS

0.01Ω

0

t

FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 15. UNCLAMPED ENERGY WAVEFORMS

V

I

g(REF)

DS

R

L

V

GS

+

V

DD

-

DUT

V

DD

V

GS

0

g(REF)

0

V

GS

= 2V

Q

g(TH)

Q

gs

t

P

I

AS

t

AV

Q

g(TOT)

V

DS

Q

g(10)

VGS = 10V

Q

gd

V

DS

V

DD

V

= 20

GS

FIGURE 16. GATE CHARGE TEST CIRCUIT FIGURE 17. GATE CHARGE WAVEFORMS

V

DS

R

L

V

GS

+

V

DD

-

V

DS

0

DUT

R

GS

V

GS

V

GS

10%

0

t

d(ON)

90%

t

ON

50%

t

10%

r

PULSE WIDTH

t

d(OFF)

90%

t

OFF

50%

t

f

90%

10%

FIGURE 18. SWITCHING TIME TEST CIRCUIT FIGURE 19. SWITCHING TIME WAVEFORM

HUF75631P3, HUF75631S3ST

PSPICE Electrical Model

.SUBCKT HUF75631 2 1 3 ; rev 19 July 1999

CA 12 8 1.95e-9 CB 15 14 1.90e-9 CIN 6 8 1.12e-9

DBODY 7 5 DBODYMOD DBREAK 5 11 D B REAK MOD DPLCAP 10 5 DPLCAPMOD

EBREAK 11 7 17 18 112.8 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 6 10 6 8 1 EVTHRES 6 21 19 8 1 EVTEMP 20 6 18 22 1

IT 8 17 1 LDRAIN 2 5 1.0e-9

LGATE 1 9 6.19e-9 LSOURCE 3 7 2.18e-9

MMED 16 6 8 8 MMEDMOD MSTRO 16 6 8 8 MSTROMOD MWEAK 16 21 8 8 MWEAKMOD

RBREAK 17 18 RBREAKMOD 1 RDRAIN 50 16 RDRAINMOD 2.00e-2 RGATE 9 20 1.77 RLDRAIN 2 5 10 RLGATE 1 9 26 RLSOURCE 3 7 11 RSLC1 5 51 RSLCMOD 1e-6 RSLC2 5 50 1e3 RSOURCE 8 7 RSOURCEMOD 6.5e-3 RVTHRES 22 8 RVTHRESMOD 1 RVTEMP 18 19 RVTE MPMOD 1

S1A 6 12 13 8 S1AMOD S1B 13 12 13 8 S1BMOD S2A 6 15 14 13 S2AMOD S2B 13 15 14 13 S2BMOD

VBAT 22 19 DC 1

GATE

LGATE

1

RLGATE

RGATE

9

CA

-

ESG

+

EVTEMP +

-

18 22

20

S1A

12

13

8

S1B

EGS EDS

13

10

6 8

+

RSLC2

6

S2A

14 13

S2B

6 8

-

DPLCAP

EVTHRES

+

19

8

CIN

15

CB

-

+

51

5 8

-

5

RSLC1

51

+

5

-

50

RDRAIN

21

MSTRO

14

ESLC

16

8

MMED

DBREAK

EBREAK

MWEAK

RSOURCE

RBREAK

17 18

IT

8

RVTHRES

LDRAIN

RLDRAIN

11

+

17 18

DBODY

DRAIN

2

-

LSOURCE

7

RLSOURCE

RVTEMP 19

SOURCE

3

-

VBAT

+

22

ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*71),3.5))} .MODEL DBODYMOD D (IS = 1.20e-12 RS = 4.2e-3 XTI = 5 TRS1 = 1.3e-3 TRS2 = 8.0e-6 CJO = 1.50e-9 TT = 7.47e-8 M = 0.63)

.MODEL DBREAKMOD D (RS = 4.2e- 1TRS1 = 8e- 4TRS2 = 3e-6) .MODEL DPLCAPMOD D (C JO = 1.45e- 9IS = 1e-3 0M = 0 .82) .MODEL MMEDMOD NMOS (VTO = 3.11 KP = 5 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 1.77) .MODEL MSTROMOD NMOS (VTO = 3.57 KP = 33.5 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u) .MODEL MWEAKM OD NMOS (VTO = 2 . 68 K P = 0.09 IS = 1e- 3 0 N = 10 TO X = 1 L = 1u W = 1u RG = 17.7 ) .MODEL RBREAKMOD RES (TC1 =1.05e- 3TC2 = -5e-7) .MODEL RDRAINMOD RES (TC1 = 9.40e-3 TC2 = 2.93e-5) .MODEL RSLCMOD RES (TC1 = 3.5e-3 TC2 = 2.0e-6) .MODEL RSOURCEMOD RES (TC1 = 1e-3 TC2 = 1e-6) .MODEL RVTHRESMOD RES (TC1 = -1.8e-3 TC2 = -8.6e-6) .MODEL RVTEMPMOD RES (TC1 = -3.0e- 3TC2 =1.5e-7)

.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -6.2 VOFF= -3.1) .MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -3.1 VOFF= -6.2) .MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -1.0 VOFF= 0.5) .MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 0.5 VOFF= -1.0)

.ENDS

NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.

HUF75631P3, HUF75631S3ST

SABER Electrical Model

REV 19 July 1999 template huf75631 n2,n1,n3

electrical n2,n1,n3 { var i iscl d..model dbodymod = (is = 1.20e-12, cjo = 1.50e-9, tt = 7.47e-8, xti = 5, m = 0.63) d..model dbreakmod = () d..model dplcapmod = (cjo = 1.45e-9, is = 1e-30, m = 0.82) m..model mmedmod = (type=_n, vto = 3.11, kp = 5, is = 1e-30, tox = 1) m..model mstrongmod = (type=_n, vto = 3.57, kp = 33.5, is = 1e-30, tox = 1) m..model mweakmod = (type=_n, vto = 2.68, kp = 0.09, is = 1e-30, tox = 1) sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -6.2, voff = -3.1) sw_vcsp..model s1bmod = (ron =1e-5, roff = 0.1, von = -3.1, voff = -6.2) sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -1.0, voff = 0.5) sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0.5, voff = -1.0)

c.ca n12 n8 = 1.95e-9 c.cb n15 n14 = 1.90e-9 c.cin n6 n8 = 1.12e-9

d.dbody n7 n71 = model=dbodymod d.dbreak n72 n11 = model=dbreakmod d.dplcap n10 n5 = model=dplcapmod

i.it n8 n17 = 1 l.ldrain n2 n5 = 1e-9

l.lgate n1 n9 = 6.19e-9 l.lsource n3 n7 = 2.18e-9

GATE

LGATE

1

RLGATE

m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u

res.rbreak n17 n18 = 1, tc1 = 1.05e-3, tc2 = -5.0e-7 res.rdbody n71 n5 = 4.2e-3, tc1 = 1.30e-3, tc2 = 8.0e-6 res.rdbreak n72 n5 = 4.2e-1, tc1 = 8.0e-4, tc2 = 3.0e-6 res.rdrain n50 n16 = 2.00e-2, tc1 = 9.40e-3, tc2 = 2.93e-5 res.rgate n9 n20 = 1.77 res.rldrain n2 n5 = 10 res.rlgate n1 n9 = 26 res.rlsource n3 n7 = 11 res.rslc1 n5 n51 = 1e-6, tc1 = 3.5e-3, tc2 = 2.0e-6 res.rslc2 n5 n50 = 1e3 res.rsource n8 n7 = 6.5e-3, tc1 = 1e-3, tc2 = 1e-6 res.rvtemp n18 n19 = 1, tc1 = -3.0e-3, tc2 = 1.5e-7 res.rvthres n22 n 8 = 1, tc1 = -1.8e-3, tc2 = -8.6e-6

RGATE

9

CA

-

ESG

+

EVTEMP

+

-

18 22

20

S1A

12

13

8

S1B

EGS EDS

13

10

6 8

+

-

DPLCAP

RSLC2

EVTHRES

6

S2A

14 13

S2B

6 8

5

RSLC1

51

ISCL

50 RDRAIN

+

19

21

-

8

MSTRO

CIN

15

CB

14

+

5 8

-

16

8

MMED

RDBREAK

72

DBREAK

11

MWEAK

EBREAK

RSOURCE

RBREAK

17 18

IT

8

RVTHRES

+

17 18

-

LDRAIN

RLDRAIN

RDBODY

71

DBODY

LSOURCE

7

RLSOURCE

RVTEMP 19

-

VBAT

+

22

DRAIN

2

SOURCE

3

spe.ebreak n11 n7 n17 n18 = 112.8 spe.eds n14 n8 n5 n8 = 1 spe.egs n13 n8 n6 n8 = 1 spe.esg n6 n10 n6 n8 = 1 spe.evtemp n20 n6 n18 n22 = 1 spe.evthres n6 n21 n19 n8 = 1

sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod

v.vbat n22 n19 = dc =1 equations {

i (n51->n50) +=iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/71))** 3.5)) } }

HUF75631P3, HUF75631S3ST

SPICE Thermal Model

REV 26 July 1999

HUF75631T

CTHERM1 th 6 2.60e-3 CTHERM2 6 5 8.85e-3 CTHERM3 5 4 7.60e-3 CTHERM4 4 3 7.65e-3 CTHERM5 3 2 1.22e-2 CTHERM6 2 tl 8.70e-2

RTHERM1 th 6 9.00e-3 RTHERM2 6 5 1.80e-2 RTHERM3 5 4 9.15e-2 RTHERM4 4 3 2.43e-1 RTHERM5 3 2 3.10e-1 RTHERM6 2 tl 3.21e-1

SABER Thermal Model

SABER thermal model HUF75631T template thermal_model th tl

thermal_c th, tl { ctherm.ctherm1 th 6 = 2.60e-3 ctherm.ctherm2 6 5 = 8.85e-3 ctherm.ctherm3 5 4 = 7.60e-3 ctherm.ctherm4 4 3 = 7.65e-3 ctherm.ctherm5 3 2 = 1.22e-2 ctherm.ctherm6 2 tl = 8.70e-2

rtherm.rtherm1 th 6 = 9.00e-3 rtherm.rtherm2 6 5 = 1.80e-2 rtherm.rtherm3 5 4 = 9.15e-2 rtherm.rtherm4 4 3 = 2.43e-1 rtherm.rtherm5 3 2 = 3.10e-1 rtherm.rtherm6 2 tl = 3.21e-1 }

RTHERM1

RTHERM2

RTHERM3

RTHERM4

RTHERM5

RTHERM6

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th

CTHERM1

6

CTHERM2

5

CTHERM3

4

CTHERM4

3

CTHERM5

2

CTHERM6

tl

CASE

TRADEMARKS

The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks.

ACEx™ Bottomless™ CoolFET™ CROSSVOLT™ DenseTrench™ DOME™ EcoSPARK™ E2CMOS EnSigna

TM

FACT™ FACT Quiet Series™

STAR*POWER is used under license

FAST FASTr™ FRFET™ GlobalOptoisolator™ GTO™ HiSeC™ ISOPLANAR™ LittleFET™ MicroFET™ MicroPak™ MICROWIRE™



OPTOLOGIC™ OPTOPLANAR™ PACMAN™ POP™ Power247™ PowerTrench

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QFET™ QS™ QT Optoelectronics™ Quiet Series™ SILENT SWITCHER

SMART START™ STAR*POWER™ Stealth™ SuperSOT™-3 SuperSOT™-6 SuperSOT™-8 SyncFET™ TinyLogic™ TruTranslation™ UHC™

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UltraFET

VCX™

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DISCLAIMER

FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user.

PRODUCT STATUS DEFINITIONS Definition of Terms

Datasheet Identification Product Status Definition

Advance Information

Preliminary

No Identification Needed

Formative or In Design

First Production

Full Production

2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or

effectiveness.

This datasheet contains the design specifications for product development. Specifications may change in any manner without notice.

This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design.

This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design.

Obsolete

Not In Production

This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only.

Rev. H4

Datasheet HUF75631S3ST Datasheet (Fairchild)

Specifications and Main Features

Frequently Asked Questions

User Manual