Datasheet HUF75345S3 Datasheet (Fairchild Semiconductor)

Page 1
©2001 Fairchild Semiconductor Corporati on HUF75345G3, HUF75345P3, HUF75345S3S Rev. B
HUF75345G3, HUF75345P3, HUF75345S3S
75A, 55V, 0.007 Ohm, N-Channel UltraFET Power MOSFETs
These N-Channel pow er MOSFETs are manufactured using the innovat ive Ul traFET® pr ocess. This
advanced process technology achieves the lowest possible on-resistance per silicon area, resulting in outsta ndi ng performance. This device i s c apa ble of withstanding hi gh ene r gy in the a valanche mode and the diode exhibits very low reverse recove ry time and stored charge. It was designed for use in applications where power efficiency is important, such as switching regulators, switching converters, motor drivers, relay drivers, low­voltage bus switches, and power management in portable and battery-operated products.
Formerly developmental type TA75345.
Features
• 75A, 55V
• Simulation Models
- Temperature Compensated PSPICE® and SABER™ Models
- Thermal Impedance SPICE and SABER Models Available on the WEB at: www.fairchildsemi.com
• Pea k Cu rrent vs Pulse Width Curve
• UIS Rating Curve
• Related Literature
- TB334, “Guidelines for Soldering Surface Mount Components to PC Boards”
Symbol
Packaging
Product reliability information can be found at http://www.fairchildsemi.com/products/discrete/reliability/index.html
For severe environments, see our Automotive HUFA series.
All Fairchild semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality systems certification.
Ordering Information
PART NUMBER PACKAGE BRAND
HUF75345G3 TO-247 75345G HUF75345P3 TO-220AB 75345P HUF75345S3S TO-263AB 75345S
NOTE: When ordering, use the entire part number. Add the suffix T to obtain the TO-263AB variant in tape and reel, e.g., HUF75345S3ST.
D
G
S
JEDEC STYLE TO-247 JEDEC TO-220AB
JEDEC TO-263AB
SOURCE
DRAIN
GATE
DRAIN (TAB)
DRAIN
SOURCE
GATE
DRAIN
(FLANGE)
GATE
SOURCE
DRAIN
(FLANGE)
Data Sheet December 2001
Page 2
©2001 Fairchild Semiconductor Corporati on HUF75345G3, HUF75345P3, HUF75345S3S Rev. B
Absolute Maximum Ratings
TC = 25oC, Unless Otherwise Specified
UNITS
Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
DSS
55 V
Drain to Gate Voltage (R
GS
= 20k) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
DGR
55 V
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
GS
±20 V
Drain Current
Continuous (Figure 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
D
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
DM
75
Figure 4
A
Pulsed Avalanche Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E
AS
Figure 6
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P
D
Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
325
2.17
W
W/oC
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
J
, T
STG
-55 to 175
o
C
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
L
Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
pkg
300 260
o
C
o
C
CAUTION: Stresses above those listed in “A bsolute Maximu m Rating s” may cause per manent d amage to t he device. This is a str ess onl y rating and operation o f the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. T
J
= 25oC to 150oC.
Electrical Specifications
TC = 25oC, Unless Otherwise Specified
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
OFF STATE SPECIFICATIONS
Drain to Source Breakdown Voltage BV
DSSID
= 250µA, VGS = 0V (Figure 11) 55 - - V
Zero Gate Voltage Drain Current I
DSS
VDS = 50V, VGS = 0V - - 1 µA V
DS
= 45V, VGS = 0V, TC = 150oC--250µA
Gate to Source Leakage Current I
GSS
VGS = ±20V - - ±100 nA
ON STATE SPECIFICATIONS
Gate to Source Threshold Voltage V
GS(TH)VGS
= VDS, ID = 250µA (Figure 10) 2 - 4 V
Drain to Source On Resistance r
DS(ON)ID
= 75A, VGS = 10V (Figure 9) - 0.006 0.007 W
THERMAL SPECIFICATIONS
Thermal Resistance Junction to Case R
θJC
(Figure 3) - - 0.46
o
C/W
Thermal Resistance Junction to Ambient R
θJA
TO-247 - - 30
o
C/W
TO-220, TO-263 - - 62
o
C/W
SWITCHING SPECIFICATIONS (V
GS
= 10V)
Turn-On Time t
ON
VDD = 30V, ID 75A, R
L
= 0.4Ω, VGS = 10V,
R
GS
= 2.5
--145ns
Turn-On Delay Time t
d(ON)
-20- ns
Rise Time t
r
-75- ns
Turn-Off Delay Time t
d(OFF)
-45- ns
Fall Time t
f
-30- ns
Turn-Off Time t
OFF
--115ns
GATE CHARGE SPECIFICATIONS
Total Gate Charge Q
g(TOT)VGS
= 0V to 20V VDD = 30V,
I
D
75A,
R
L
= 0.4
I
g(REF)
= 1.0mA
(Figure 13)
- 220 275 nC
Gate Charge at 10V Q
g(10)
VGS = 0V to 10V - 125 165 nC
Threshold Gate Charge Q
g(TH)
VGS = 0V to 2V - 6.8 10 nC
Gate to Source Gate Charge Q
gs
-14-nC
Gate to Drain “Miller” Charge Q
gd
-58-nC
HUF75345G3, HUF75345P3, HUF75345S3S
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©2001 Fairchild Semiconductor Corporati on HUF75345G3, HUF75345P3, HUF75345S3S Rev. B
CAPACITANCE SPECIFICATIONS
Input Capacitance C
ISS
VDS = 25V, VGS = 0V, f = 1MHz (Figure 12)
- 4000 - pF
Output Capacitance C
OSS
- 1450 - pF
Reverse Transfer Capacitance C
RSS
- 450 - pF
Electrical Specifications
TC = 25oC, Unless Otherwise Specified (Continued)
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Source to Drain Diode Specifications
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Source to Drain Diode Voltage V
SD
ISD = 75A - - 1.25 V
Reverse Recovery Time t
rr
ISD = 75A, dISD/dt = 100A/µs - - 110 ns
Reverse Recovered Charge Q
RR
ISD = 75A, dISD/dt = 100A/µs - - 225 nC
Typical Performance Curves
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE
TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
TC, CASE TEMPERATURE (oC)
POWER DISSIPA TION MULTIPLIER
0
0 25 50 75 100 150
0.2
0.4
0.6
0.8
1.0
1.2
125 17
5
I
D
, DRAIN CURRENT (A)
TC, CASE TEMPERATURE (oC)
20
40
60
80
50 75 100 125 150 17
5
0
25
t, RECTANGULAR PULSE DURATION (s)
SINGLE PULSE
NOTES: DUTY FACTOR: D = t
1/t2
PEAK TJ = PDM x Z
θJC
x R
θJC
+ T
C
P
DM
t
1
t
2
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
0.1
0.05
0.01
0.02
10
-4
10
-3
10
-2
10
-1
10
0
10
1
10
-5
0.1
1
2
0.01
Z
θJC
, NORMALIZED
THERMAL IMPEDANCE
HUF75345G3, HUF75345P3, HUF75345S3S
Page 4
©2001 Fairchild Semiconductor Corporati on HUF75345G3, HUF75345P3, HUF75345S3S Rev. B
FIGURE 4. PEAK CURRENT CAPABILITY
FIGURE 5. FORWARD BIAS SAFE OPERATING AREA
NOTE: Refer to Fairchild Application Notes AN9321 and AN9322.
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY
FIGURE 7. SATURATION CHARACTERISTICS FIGURE 8. TRANSFER CHARACTERISTICS
Typical Performance Curves
(Continued)
10
1
10
0
10
-1
10
-2
10
-3
10
-4
10
-5
50
100
2000
TC = 25oC
I = I
25
175 - T
C
150
FOR TEMPERATURES ABOVE 25
o
C DERATE PEAK
CURRENT AS FOLLOWS:
VGS = 10V
I
DM
, PEAK CURRENT (A)
t, PULSE WIDTH (s)
TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION
1000
VGS = 20V
10
100
1000
10 100
1
120
0
VDS, DRAIN TO SOURCE VOLTAGE (V)
I
D
, DRAIN CURRENT (A)
TJ = MAX RATED T
C
= 25oC
100µs
10ms
1ms
V
DSS(MAX)
= 55V
LIMITED BY r
DS(ON)
AREA MAY BE
OPERATION IN THIS
1 10 100
100
0.01
1000
10
I
AS
, AVALANCHE CURRENT (A)
tAV, TIME IN AVALANCHE (ms)
tAV = (L)(IAS)/(1.3*RATED BV
DSS
- VDD)
If R = 0
If R ≠ 0 t
AV
= (L/R)ln[(IAS*R)/(1.3*RATED BV
DSS
- VDD) +1]
STARTING TJ = 25oC
STARTING TJ = 150oC
0.1
0
30
60
0123
4
90
120
I
D
, DRAIN CURRENT (A)
VDS, DRAIN TO SOURCE VOLTAGE (V)
VGS = 6V
VGS = 10V
V
GS
= 20V
PULSE DURATION = 80µs T
C
= 25oC
VGS = 5V
150
VGS = 7V
DUTY CYCLE = 0.5% MAX
175oC
0 3.0 4.5 6.0 7.51.5
0
30
60
90
120
I
D
, DRAIN CURRENT (A)
VGS, GATE TO SOURCE VOLTAGE (V)
-55oC
25oC
V
DD
= 15V
150
PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX
HUF75345G3, HUF75345P3, HUF75345S3S
Page 5
©2001 Fairchild Semiconductor Corporati on HUF75345G3, HUF75345P3, HUF75345S3S Rev. B
FIGURE 9. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
FIGURE 10. NORMALIZED GATE T HRESHOLD V OLTA GE vs
JUNCTION TEMPERATURE
FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
NOTE: Refer to Fairchild Application Notes AN7254 and AN7260.
FIGURE 13. GATE CHARGE WA VEFORMS FOR CONSTANT GATE CURRENT
Typical Performance Curves
(Continued)
0.5
1.0
1.5
2.0
2.5
-80 -40 0 40 80 120 160
NORMALIZED DRAIN TO SOURCE
TJ, JUNCTION TEMPERATURE (oC)
ON RESISTANCE
PULSE DURATION = 80µs, VGS = 10V, ID = 75A
200
DUTY CYCLE = 0.5% MAX
-80 -40 0 40 80 120 160
0.4
0.6
0.8
1.0
1.2
NORMALIZED GATE
TJ, JUNCTION TEMPERATURE (oC)
THRESHOLD VOLTAGE
VGS = VDS, ID = 250µA
200
1.2
1.1
1.0
0.9
0.8
-80 -40 0 40 80 120 160 T
J
, JUNCTION TEMPERATURE (oC)
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
ID = 250µA
200
1.3
4000
2000
0
01020304050
C, CAPACITANCE (pF)
3000
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
1000
C
ISS
C
OSS
C
RSS
60
5000
6000
7000
V
GS
= 0V, f = 1MHz
C
ISS
= CGS + C
GD
C
RSS
= C
GD
C
OSS
CDS + C
GD
10
8
6
4
0
V
GS
, GATE TO SOURCE VOLTAGE (V)
VDD = 30V
2
75 100 1250
Q
g
, GATE CHARGE (nC)
25 50
ID = 75A I
D
= 55A
I
D
= 35A
I
D
= 20A
WAVEFORMS IN DESCENDING ORDER:
HUF75345G3, HUF75345P3, HUF75345S3S
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©2001 Fairchild Semiconductor Corporati on HUF75345G3, HUF75345P3, HUF75345S3S Rev. B
Test Circuits and Waveforms
FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 15. UNCLAMPED ENERGY WAVEFORMS
FIGURE 16. GATE CHARGE TEST CIRCUIT FIGURE 17. GATE CHARGE WAVEFORM
FIGURE 18. SWITCHING TIME TEST CIRCUIT FIGURE 19. RESISTIVE SWITCHING WAVEFORMS
t
P
V
GS
0.01
L
I
AS
+
-
V
DS
V
DD
R
G
DUT
VARY t
P
TO OBTAIN
REQUIRED PEAK I
AS
0V
V
DD
V
DS
BV
DSS
t
P
I
AS
t
AV
0
R
L
V
GS
+
-
V
DS
V
DD
DUT
I
G(REF)
V
DD
Q
g(TH)
V
GS
= 2V
Q
g(10)
VGS = 10V
Q
g(TOT)
V
GS
= 20
V
V
DS
V
GS
I
g(REF)
0
0
Q
gs
Q
gd
V
GS
R
L
R
GS
DUT
+
-
V
DD
V
DS
V
GS
t
ON
t
d(ON)
t
r
90%
10%
V
DS
90%
10%
t
f
t
d(OFF)
t
OFF
90%
50%
50%
10%
PULSE WIDTH
V
GS
0
0
HUF75345G3, HUF75345P3, HUF75345S3S
Page 7
©2001 Fairchild Semiconductor Corporati on HUF75345G3, HUF75345P3, HUF75345S3S Rev. B
PSPICE Electrical Model
.SUBCKT HUF75345 2 1 3 ; rev 3 Feb 99
CA 12 8 5.55e-9 CB 15 14 5.55e-9 CIN 6 8 3.45e-9
DBODY 7 5 DBODYMOD DBREAK 5 11 D B REAK MOD DPLCAP 10 5 DPLCAPMOD
EBREAK 11 7 17 18 56.7 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 6 10 6 8 1 EVTHRES 6 21 19 8 1 EVTEMP 20 6 18 22 1
IT 8 17 1 LDRAIN 2 5 1e-9
LGATE 1 9 2.6e-9 LSOURCE 3 7 1.1e-9 KGATE LSOURCE LGATE 0.0085
MMED 16 6 8 8 MMEDMOD MSTRO 16 6 8 8 MSTROMOD MWEAK 16 21 8 8 MWEAKMOD
RBREAK 17 18 RBREAKMOD 1 RDRAIN 50 16 RDRAINMOD 1e-4 RGATE 9 20 0.36 RLDRAIN 2 5 10 RLGATE 1 9 26 RLSOURCE 3 7 11 RSLC1 5 51 RSLCMOD 1e-6 RSLC2 5 50 1e3 RSOURCE 8 7 RSOURCEMOD 3.15e-3 RVTHRES 22 8 RVTHRESMOD 1 RVTEMP 18 19 RVTE MPMOD 1
S1A 6 12 13 8 S1AMOD S1B 13 12 13 8 S1BMOD S2A 6 15 14 13 S2AMOD S2B 13 15 14 13 S2BMOD
VBAT 22 19 DC 1 ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*500),3.5))} .MODEL DBODYMOD D (IS = 6e-12 RS = 1.4e-3 IKF = 20 XTI = 5 TRS1 = 2.75e-3 TRS2 = 5.0e-6 CJO = 5.5e-9 TT = 5.9e-8 M = 0.5 VJ = 0.75)
.MODEL DBREAKMOD D (RS = 2.8e-2 IKF = 3 0TRS1 = -4.0e- 3TRS2 = 1.0e-6) .MODEL DPLCAPMOD D (CJO = 6.75e- 9IS = 1e-30 M = 0.88 VJ = 1.45 FC = 0.5) .MODEL MMEDM OD NMOS (VTO = 2.93 KP = 13.75 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 0.36) .MODEL MSTROMOD NMOS (VT O = 3.23 KP = 96 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u Lambda = 0.06) .MODEL MWEAKMOD NMOS (VTO = 2.35 KP =0.02 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 3.6) .MODEL RBREAKMOD RES (TC1 = 8.0e- 4TC2 = 4.0e-6) .MODEL RDRAINMOD RES (TC1 = 1.5e-1 TC2 = 6.5e-4) .MODEL RSLCMOD RES (TC1 = 1.0e-4 TC2 = 1.05e-6) .MODEL RSOURCEMOD RES (TC1 = 1.0e-3 TC2 = 0) .MODEL RVTHRESMOD RES (TC1 = -1.5e-3 TC2 = -2.6e-5) .MODEL RVTEMPMOD RES (TC1 = -2.75e- 3TC2 = 1.45e-6)
.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -9.00 VOFF= -4.00) .MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -4.00 VOFF= -9.00) .MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 0.00 VOFF= 0.50) .MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 0.50 VOFF= 0.00)
.ENDS
NOTE: For further di scussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featu ring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
18 22
+
-
6 8
+
-
5
51
+
-
19
8
+
-
17 18
6 8
+
-
5 8
+
-
RBREAK
RVTEMP
VBAT
RVTHRES
IT
17 18
19
22
12
13
15
S1A
S1B
S2A
S2B
CA
CB
EGS EDS
14
8
13
8
14 13
MWEAK
EBREAK
DBODY
RSOURCE
SOURCE
11
7
3
LSOURCE
RLSOURCE
CIN
RDRAIN
EVTHRES
16
21
8
MMED
MSTRO
DRAIN
2
LDRAIN
RLDRAIN
DBREAK
DPLCAP
ESLC
RSLC1
10
5
51
50
RSLC2
1
GATE
RGATE
EVTEMP
9
ESG
LGATE
RLGATE
20
+
-
+
-
+
-
6
HUF75345G3, HUF75345P3, HUF75345S3S
Page 8
©2001 Fairchild Semiconductor Corporati on HUF75345G3, HUF75345P3, HUF75345S3S Rev. B
SABER Electrical Model
REV 3 February 1999 template huf75345 n2, n1, n3
electrical n2, n1, n3 { var i iscl d..model dbodymod = (is = 6e-12, xti = 5, cjo = 5.5e-9, tt = 5.9e-8, m=0.5, vj=0.75) d..model dbreakmod = () d..model dplcapmod = (cjo = 6.75e-9, is = 1e-3 0, m = 0.88, vj = 1.45,fc=0.5) m..model mmedmod = (type=_n, vto = 2.93, kp = 13.75, is = 1e-30, tox = 1) m..model mstrongmod = (type=_n, vto = 3.23, kp = 96, is=1e-30,tox=1, lambda = 0.06) m..model mweakmod = (type=_n, vto = 2.35, kp = 0.02, is = 1e-30, tox = 1) sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -9, voff = -4) sw_vcsp..model s1bmod = (ron = 1e-5, roff = 0.1, von = -4, voff = -9) sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = 0, voff = 0.5) sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0.5, voff = 0)
c.ca n12 n8 = 5.55e-9 c.cb n15 n14 = 5.55e-9 c.cin n6 n8 = 3.45e-9
d.dbody n7 n71 = model=dbodymod d.dbreak n72 n11 = model=dbreakmod d.dplcap n10 n5 = model=dplcapmod
i.it n8 n17 = 1 l.ldrain n2 n5 = 1e-9
l.lgate n1 n9 = 2.6e-9 l.lsource n3 n7 = 1.1e-9 k.k1 i(l.lgate) i(l.lsource) = l(l.lgate), l(l.lsource), 0.0085
m.mmed n16 n6 n8 n8 = model=mmedmod, l = 1u, w = 1u m.mstrong n16 n6 n8 n8 = model=mstrongmod, l = 1u, w = 1u m.mweak n16 n21 n8 n8 = model=mweakmod, l = 1u, w = 1u
res.rbreak n17 n18 = 1, tc1 = 8e-4, tc2 = 4e-6 res.rdbody n71 n5 = 1.4e-3, tc1 = 2.75e-3, tc2 = 5e-6 res.rdbreak n72 n5 = 2.8e-2, tc1 = -4e-3, tc2 = 1e-6 res.rdrain n50 n16 = 1e-4, tc1 = 1.5e-1, tc2 = 6.5e-4 res.rgate n9 n20 = 0.36 res.rldrain n2 n5 = 10 res.rlgate n1 n9 = 26 res.rlsource n3 n7 = 11 res.rslc1 n5 n51 = 1e-6, tc1 = 1e-4, tc2 = 1.05e-6 res.rslc2 n5 n50 = 1e3 res.rsource n8 n7 = 3.15e-3, tc1 = 1e-3, tc2 = 0 res.rvtemp n18 n19 = 1, tc1 = -2.75e-3, tc2 = 1.45e-6 res.rvthres n22 n 8 = 1, tc1 = -1.5e-3, tc2 = -2.6e-5
spe.ebreak n11 n7 n17 n18 = 56.7 spe.eds n14 n8 n5 n8 = 1 spe.egs n13 n8 n6 n8 = 1 spe.esg n6 n10 n6 n8 = 1 spe.evtemp n20 n6 n18 n22 = 1 spe.evthres n6 n21 n19 n8 = 1
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc = 1 equations {
i (n51->n50) + = iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v ( n5,n51))))*((abs(v(n5,n51)*1e6/500))** 3.5)) } }
18 22
+
-
6 8
+
-
19
8
+
-
17 18
6 8
+
-
5 8
+
-
RBREAK
RVTEMP
VBAT
RVTHRES
IT
17 18
19
22
12
13
15
S1A
S1B
S2A
S2B
CA
CB
EGS EDS
14
8
13
8
14 13
MWEAK
EBREAK
DBODY
RSOURCE
SOURCE
11
7
3
LSOURCE
RLSOURCE
CIN
RDRAIN
EVTHRES
16
21
8
MMED
MSTRO
DRAIN
2
LDRAIN
RLDRAIN
DBREAK
DPLCAP
ISCL
RSLC1
10
5
51
50
RSLC2
1
GATE
RGATE
EVTEMP
9
ESG
LGATE
RLGATE
20
+
-
+
-
+
-
6
RDBODY
RDBREAK
72
71
HUF75345G3, HUF75345P3, HUF75345S3S
Page 9
©2001 Fairchild Semiconductor Corporati on HUF75345G3, HUF75345P3, HUF75345S3S Rev. B
SPICE Thermal Model
REV 5 February 1999
HUF75345
CTHERM1 th 6 6.3e-3 CTHERM2 6 5 1.5e-2 CTHERM3 5 4 2.0e-2 CTHERM4 4 3 3.0e-2 CTHERM5 3 2 8.0e-2 CTHERM6 2 tl 1.5e-1
RTHERM1 th 6 5.0e-3 RTHERM2 6 5 1.8e-2 RTHERM3 5 4 5.0e-2 RTHERM4 4 3 8.5e-2 RTHERM5 3 2 1.0e-1 RTHERM6 2 tl 1.1e-1
SABER Thermal Model
SABER thermal model HUF75345 template thermal_model th tl
thermal_c th, tl { ctherm.ctherm1 th 6 = 6.3e-3 ctherm.ctherm2 6 5 = 1.5e-2 ctherm.ctherm3 5 4 = 2.0e-2 ctherm.ctherm4 4 3 = 3.0e-2 ctherm.ctherm5 3 2 = 8.0e-2 ctherm.ctherm6 2 tl = 1.5e-1
rtherm.rtherm1 th 6 = 5.0e-3 rtherm.rtherm2 6 5 = 1.8e-2 rtherm.rtherm3 5 4 = 5.0e-2 rtherm.rtherm4 4 3 = 8.5e-2 rtherm.rtherm5 3 2 = 1.0e-1 rtherm.rtherm6 2 tl = 1.1e-1 }
RTHERM4
RTHERM6
RTHERM5
RTHERM3
RTHERM2
RTHERM1
CTHERM4
CTHERM6
CTHERM5
CTHERM3
CTHERM2
CTHERM1
tl
2
3
4
5
6
th
JUNCTION
CASE
HUF75345G3, HUF75345P3, HUF75345S3S
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