Datasheet HT82K68A Datasheet (Holtek Semiconductor Inc)

Page 1
HT82K68A
Preliminary
Multimedia Keyboard Encoder Body

Features

Operating voltage: 2.2V~5.5V
·
34(42-pin)/32(40-pin) bidirectional I/O lines
·
One 8-bit programmable timer counter with
·
·
Watchdog Timer
·
3K´16 program ROM
·
160´8 data RAM
·

General Description

The HT82K68A is an 8-bit high performance peripheral interface IC, designed for multiple I/O products and multimedia applications. It supports interface to a low speed PC with
HALT function and wake-up feature reduce
·
power consumption Six-level subroutine nesting
·
Bit manipulation instructions
·
16-bit table read instructions
·
63 powerful instructions
·
All instructions in 1 or 2 machine cycles
·
40-pin DIP/42-pin DIP/DICE form package
·
multimedia keyboard or wireless keyboard in Windows 95, Windows 98 or Windows 2000 en vironment. A HALT feature is included to re duce power consumption.
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1 April 20, 2000
Page 2

Block Diagram

Program
ROM
Program
C ounter
Preliminary
STACK0
STACK1
STACK2
STACK3
STACK4
STACK5
In te rru p t
Circuit
IN T C
HT82K68A
SYS C LK/4
TM R
TM RC
8 bit
Instruction
R egister
Instruction
D ecoder
Tim ing
G enerator
OSC2 OSC1
RESET
VDD VSS
MP0 MP1
ALU
S h ifte r
ACC
MUX
M U X
DATA
Memory
STATUS
WDTS
WDT Prescaler
PORT E
PEC
PE
PDC
PORT D
PD
PCC
PORT C
PC
PBC
PORT B
PB
PAC
PORT A
PA
SYS C LK/4
WDT
PE0~PE4
PD0~PD 7
PC0~PC 7
PB0~PB7
PA0~PA7
M U X
RC OSC
2 April 20, 2000
Page 3

Pin Assignment

Preliminary
HT82K68A
PB5(R5)
PB4(R4)
PA3(C3)
PA2(C2)
PA1(C1)
PA0(C0)
PB3(R3)
PB2(R2)
PB1(R1)
PB0(R0)
PD 7(R 15)
PD 6(R 14)
PD 5(R 13)
PD 4(R 12)
VSS
PE2(SCR)
PE3(NUM )
PC0(D ATA)
PC1(C LK)
PC2
H T 82K 68A

Pin Description

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
4 0 D IP
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
PB6(R6)
PB7(R7)
PA4(C4)
PA5(C5)
PA6(C6)
PA7(C7)
OSC2
OSC1
VDD
RESET
PE4(CAP)
PD 3(R 11)
PD 2(R 10)
PD1(R 9)
PD0(R 8)
PC 7(R 17)
PC 6(R 16)
PC5
PC4
PC3
PB5(R5)
PB4(R4)
PA3(C3)
PA2(C2)
PA1(C1)
PA0(C0)
PB3(R3)
PB2(R2)
PB1(R1)
PB0(R0)
PD7(R 15)
PD6(R 14)
PD5(R 13)
PD4(R 12)
VSS
PE2(SCR)
PE3(NUM )
PC0(D ATA)
PC1(C LK)
PC2
PE0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
H T 82K 68A
4 2 D IP
PB6(R6)
PB7(R7)
PA4(C4)
PA5(C5)
PA6(C6)
PA7(C7)
OSC2
OSC1
VDD
RESET
PE4(CAP)
PD 3(R 11)
PD 2(R 10)
PD1(R 9)
PD0(R 8)
PC 7(R 17)
PC 6(R 16)
PC5
PC4
PC3
PE1
Pin Name I/O
PA0~PA7 I/O
PB0~PB7 I/O
PC0 I/O
PC1 I/O
Mask
Option
Wake-up
Pull-high
or None
Pull-high
or None
Wake-up
Pull-high
or None
Wake-up
Pull-high
or None
Description
Bidirectional 8-bit input/output port. Each bit can be configured as a wake-up input by mask option. Software* instructions determine the CMOS output or schmitt trigger input with or without pull-high resistor 12K.
Bidirectional 8-bit input/output port. Software* instructions deter mine the CMOS output or schmitt trigger input with or without pull-high resistor.
This pin is an I/O port. NMOS open drain output with pull-high re sistor and can be used as DATA or CLOCK line of PS2. This pin can be configured as a wake-up input by mask option.
This pin is an I/O port. NMOS open drain output with pull-high re sistor and can be used as DATA or CLOCK line of PS2. This pin can be configured as a wake-up input by mask option.
3 April 20, 2000
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Page 4
Preliminary
HT82K68A
Pin Name I/O
PC2~PC3 I/O
PC4~PC7 I/O
PD0~PD7 I/O
PE0~PE1 I/O
PE2 O
PE3 O
PE4 O
VDD
VSS
RESET
OSC1 OSC2
¾¾ ¾¾
I
IOCrystal or
Mask
Option
Wake-up
Pull-high
or None
Pull-high
or None
Pull-high
or None
Pull-high
or None
¾
RC
Description
Bidirectional 2-bit input/output port. Each bit can be configured as a wake-up input by mask option. Software* instructions determine the CMOS output or schmitt trigger input with or without pull-high resistor.
Bidirectional 4-bit input/output port. Software* instructions deter mine the CMOS output or schmitt trigger input with or without pull-high resistor.
Bidirectional 8-bit input/output port. Software* instructions deter mine the CMOS output or schmitt trigger input with or without pull-high resistor.
Bidirectional input/output port. Software* instruction determine the CMOS output or schmitt trigger input with or without pull-high resistor.
This pin is an NMOS output structure. The pad can function as LED (SCR) drivers for the keyboard. I
This pin is an NMOS output structure. The pad can function as LED (NUM) drivers for the keyboard. I
This pin is an NMOS output structure. The pad can function as LED (CAP) drivers for the keyboard. I
Positive power supply
Negative power supply, ground
Chip reset input. Active low. Built-in power-on reset circuit to reset the entire chip. Chip can also be externally reset via RESET
OSC1, OSC2 are connected to an RC network or a crystal for the in­ternal system clock. In the case of RC operation, OSC2 is the output terminal for the 1/4 system clock; A 110kW resistor is connected to OSC1 to generate a 2 MHZ frequency.
=14mA, @VOL=3.2V
OL
=14mA, @VOL=3.2V
OL
=14mA, @VOL=3.2V
OL
pin
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Note:
*: Software means the HT-IDE (Holtek Integrated Development Environment) can be con­figured by mask option.

Absolute Maximum Ratings

Supply Voltage .............................-0.3V to 5.5V
Input Voltage ................V
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maxi
mum Ratings² may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged expo sure to extreme conditions may affect device reliability.
3V to VDD+0.3V
SS-0.
Storage Temperature ................-50°Cto125°C
Operating Temperature .............-25°Cto70°C
4 April 20, 2000
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Page 5
Preliminary
HT82K68A

D.C. Characteristics

Symbol Parameter
V
DD
I
DD1
I
DD2
I
STB1
I
STB2
V
IL
V
IH
V
IL1
V
IH1
I
OL
I
OH
I
LED
t
POR
R
PH
R
PH1
Df/f Df/f1
Operating Voltage
Operating Current (Crystal OSC)
Operating Current (RC OSC)
Standby Current (WDT enabled)
Standby Current (WDT Disabled)
Input Low Voltage for I/O Ports
Input High Voltage for I/O Ports
Input Low Voltage (RESET
)
Input High Voltage (RESET
)
I/O Port Sink Current 5V
I/O Port Source Current 5V
LED Sink Current (SCR, NUM, CAP)
Power-on Reset Time 5V
Internal Pull-high Resistance of PA, PB, PC, PD, PE Port
Internal Pull-high Resistance of DATA, CLK
Frequency Variation 5V Crystal
Frequency Variation 5V RC
Test Conditions
V
DD
Conditions
¾¾
3V
No load, f
5V
3V
No load, f
5V
3V
No load, system HALT
5V
3V
No load, system HALT
5V
3V
5V
3V
5V
3V
5V
3V
5V
V
= 0.5V
OL
V
= 4.5V
OH
=3.2V
V
5V
OL
SYS
SYS
¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾
= 2MHz
= 2MHz
¾
5V
5V
¾
¾
Ta=25°C
Min. Typ. Max. Unit
2.2
¾ ¾ ¾ ¾ ¾¾ ¾¾ ¾¾ ¾¾
0
0
2.1
3.5
0
0
2.4
4.0
712
-2.5 -4.5 ¾
5.5 V
¾
0.7 1.5 mA
25mA
0.5 1 mA
25mA
8
mA
15
mA
3
mA
6
mA
0.9 V
¾
1.5 V
¾ ¾ ¾ ¾ ¾ ¾ ¾
3V
5V
0.7 V
1.3 V
3V
5V
mA
¾
mA
10 14 18 mA
120 150 180 ms
51220
2 4.7 8
¾¾±1 ¾¾±10
kW
kW
%
%
5 April 20, 2000
Page 6
Preliminary
HT82K68A

A.C. Characteristics

Symbol Parameter
f
SYS1
f
SYS2
t
WDTOSC
t
WDT1
t
WDT2
t
RES
t
SST
t
INT
Note: t
System Clock (Crystal OSC)
System Clock (RC OSC)
Watchdog Oscillator
Watchdog Time-out Period (RC)
Watchdog Time-out Period (System Clock)
External Reset Low Pulse Width
System Start-up Timer Period
Interrupt Pulse Width
= 1/f
SYS
SYS
Ta=25°C
Test Conditions
V
DD
3V
5V
3V
5V
3V
5V
3V
5V 9 17 35 ms
¾
Conditions
¾¾2¾ ¾¾2¾ ¾¾ ¾¾ ¾ ¾
Without WDT prescaler
Without WDT prescaler
¾¾
Power-up or
¾
wake-up from HALT
¾¾
Min. Typ. Max. Unit
MHz
MHz
2 12 MHz
2 20 MHz
45 90 180
35 65 130
12 23 45 ms
1024
¾
¾
1
¾¾ms
1024
1
¾¾ms
¾
¾
t
t
ms ms
SYS
SYS
6 April 20, 2000
Page 7
Preliminary

Functional Description

Execution flow
The HT82K68A system clock is derived from ei ther a crystal or an RC oscillator. The system clock is internally divided into four non-overlapping clocks. One instruction cycle consists of four system clock cycles.
Instruction fetching and execution are pipelined in such a way that a fetch takes one instruction cycle while decoding and execution takes the next instruction cycle. However, the pipelining scheme causes each instruction to effectively execute within one cycle. If an in struction changes the program counter, two cy cles are required to complete the instruction.
Program counter - PC
The 12-bit program counter (PC) controls the sequence in which the instructions stored in the program ROM are executed and its contents specify a maximum of 4096 addresses.
After accessing a program memory word to fetch an instruction code, the contents of the program counter are incremented by one. The program counter then points to the memory word containing the next instruction code.
When executing a jump instruction, conditional skip execution, loading PCL register, subrou­tine call, initial reset, internal interrupt, exter-
HT82K68A
nal interrupt or return from subroutine, the PC manipulates the program transfer by loading
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the address corresponding to each instruction.
The conditional skip is activated by instruction. Once the condition is met, the next instruction, fetched during the current instruction execu tion, is discarded and a dummy cycle replaces it to get the proper instruction. Otherwise pro ceed with the next instruction.
The lower byte of the program counter (PCL) is a readable and writeable register (06H).Moving data into the PCL performs a short jump. The
­destination will bewithin 256locations.
­Once a control transfer takes place, an addi
tional dummy cycle is required.
Program memory - ROM
The program memory is used to store the pro gram instructions which are to be executed. It also contains data, table, and interrupt entries, and is organized with 3072 ´ 16 bits, addressed by the program counter and table pointer.
Certain locations in the program memory are reserved for special usage:
·
Location 000 This area is reserved for the initialization
program. After chip reset, the program al­ways begins execution at location 000H.
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-
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S ystem C lock
OSC2 (RC only)
(N M O S open drain output)
PC
T1 T2 T3 T4 T1 T2 T3 T4 T1 T2 T3 T4
PC
F e tc h IN S T (P C )
Execute IN S T (P C -1)
PC+1 PC+2
F e tc h IN S T (P C + 1 )
Execute IN ST (P C )
F e tc h IN S T (P C + 2 )
Execute IN S T (P C +1)
Execution flow
7 April 20, 2000
Page 8
Preliminary
·
Location 008H This area is reserved for the timer counter in
terrupt service program. If timer interrupt re sults from a timer counter overflow, and if the interrupt is enabled and the stack is not full, the program begins execution at location 008H.
·
Table location Any location in the ROM space can be used as
look-up tables. The instructions TABRDC [m] (the current page, 1 page=256 words) and TABRDL [m] (the last page) transfer the con tents of the lower-order byte to the specified data memory, and the higher-order byte to TBLH (08H). Only the destination of the lower-order byte in the table is well-defined, the other bits of the table word are trans ferred to the lower portion of TBLH, the re maining 1 bit is read as 0. The Table Higher-order byte register (TBLH) is read only. The TBLH is read only and cannot be re stored. If the main routine and the ISR (Inter rupt Service Routine) both employ the table read instruction, the contents of the TBLH in the main routine are likely to be changed by the table read instruction used in the ISR. Er­rors can occur. In other words, using the table read instruction in the main routine and the ISR simultaneously should be avoided. How-
HT82K68A
000H
-
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008H
n00H
nFFH
BFFH
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ever, if the table read instruction has to be ap plied in both the main routine and the ISR, the interrupt is supposed to be disabled prior
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to the table read instruction. It will not be en abled until the TBLH has been backed up. The table pointer (TBLP) is a read/write regis ter (07H), which indicates the table location. Before accessing the table, the location must be placed in TBLP. All table related instructions need 2 cycles to complete the operation. These areas may function as normal program memory depending upon the requirements.
D evice initialization program
Tim er/event counter interrupt subroutine
Look-up table (256 w ords)
Look-up table (256 w ords)
16 bits
N ote: n ranges from 0 to B
Program memory
Program ROM
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Mode
Program Counter
*11 *10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0
Initial reset 0 0 0 0 00000000
Timer counter overflow 0 0 0 0 00001000
Skip PC+2
Loading PCL
*11 *10 *9 *8
@7 @6 @5 @4 @3 @2 @1 @0
Jump, call branch #11 #10 #9 #8 #7 #6 #5 #4 #3 #2 #1 #0
Return from subroutine S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0
Note: *11~*0: Program counter bits
#11~#0: Instruction code bits
S11~S0: Stack register bits @7~@0: PCL bits
8 April 20, 2000
Page 9
Preliminary
Stack register - STACK
This is a special part of the memory which is used to save the contents of the program coun ter (PC) only. The stack is organized into six lev els and is neither part of the data nor part of the program space, and is neither readable nor writeable. The activated level is indexed by the stack pointer (SP) and is neither readable nor writeable. At a subroutine call or interrupt ac knowledgement, the contents of the program counter are pushed onto the stack. At the end of a subroutine or an interrupt routine, signaled by a return instruction (RET or RETI), the pro gram counter is restored to its previous value from the stack. After a chip reset, the SP will point to the top of the stack.
If the stack is full and a non-masked interrupt takes place, the interrupt request flag will be re corded but the acknowledgement will be inhib ited. When the stack pointer is decremented (by RET or RETI), the interrupt will be serviced. This feature prevents stack overflow allowing the pro grammer to use the structure more easily. In a similar case, if the stack is full and a ²CALL² is subsequently executed, stack overflow occurs and the first entry will be lost (only the most recent four return addresses are stored).
HT82K68A
Indirect Addressing R egister 0
00H
01H
Indirect Addressing R egister 1
-
-
-
-
-
-
-
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0C H
0D H
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1C H
1D H
1EH
1FH
20H
MP0
MP1
ACC
PCL
TBLP
TBLH
WDTS
STATUS
IN T C
TM R
TM R C
PA
PAC
PB
PBC
PC
PCC
PD
PDC
PE
PEC
Special P urpose
DATA MEM ORY
: U nused.
R ead as ²00
²
Data memory - RAM
The data memory is designed with 184 ´ 8 bits. It is divided into two functional groups: special function registers and general purpose data memory (160´8). Most of them are read/write,
60H
G eneral P urpose
DATA MEM ORY
(160 B ytes)
FFH
RAM mapping
but some are read only.
The special function registers include the Indi­rect Addressing register 0 (00H), the Memory Pointer register 0 (MP0;01H), the Indirect Ad dressing register 1 (02H), the Memory Pointer register 1 (MP1;03H), the Accumulator
Instruction(s)
*11 *10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0
(ACC;05H), the Program Counter Lower-byte register (PCL;06H), the Table Pointer
­(TBLP;07H), the Table Higher-order byte regis
ter (TBLH;08H), the Watchdog Timer option Set ting register (WDTS;09H), the Status register
Table Location
TABRDC [m] P11 P10 P9 P8 @7 @6 @5 @4 @3 @2 @1 @0
TABRDL [m] 1 0 1 1 @7 @6 @5 @4 @3 @2 @1 @0
Note: *11~*0: Table location bits
P11~P8: Current program counter bits
@7~@0: Table location bits
9 April 20, 2000
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Page 10
Preliminary
HT82K68A
(STATUS;0AH), the Interrupt Control register (INTC;0BH), the timer counter register (TMR;0DH), the timer counter control register (TMRC;0EH), the I/O registers (PA;12H, PB;14H, PC;16H, PD;18H, PE;1AH) and the I/O control registers (PAC;13H, PBC;15H, PCC;17H, PDC;19H, PEC;1BH). The remaining space be fore the 60H is reserved for future expanded us age and reading these locations will get the result 00H. The general purpose data memory, ad dressed from 60H to FFH, is used for data and control information under instruction com mand.
All data memory areas can handle arithmetic, logic, increment, decrement and rotate opera tions directly. Except for some dedicated bits, each bit in the data memory can be set and re set by the SET [m].i and CLR [m].i instructions, respectively. They are also indirectly accessible through Memory pointer registers (MP0;01H, MP1;03H).
Indirect addressing register
Location 00H and 02H are indirect addressing registers that are not physically implemented. Any read/write operation of [00H] and [02H] can access the data memory pointed to by MP0 (01H) and MP1 (03H) respectively. Reading lo­cation 00H or 02H indirectly will return the re­sult 00H. Writing indirectly results in no operation.
The function of data movement between two in­direct addressing registers is not supported. The memory pointer registers, MP0 and MP1, are 8-bit registers which can be used to access the data memory by combining corresponding indirect addressing registers.
Accumulator
The accumulator is closely related to the ALU operations. It is also mapped to location 05H of the data memory and is capable of carrying out immediate data operations. The data move ment between two data memory locations must pass through the accumulator.
Arithmetic and logic unit - ALU
This circuit performs 8-bit arithmetic and logic operation. The ALU provides the following func tions:
·
Arithmetic operations (ADD, ADC, SUB,
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SBC, DAA)
·
Logic operations (AND, OR, XOR, CPL)
·
Rotation (RL, RR, RLC, RRC)
·
Increment and Decrement (INC, DEC)
·
Branch decision (SZ, SNZ, SIZ, SDZ ....)
The ALU not only saves the results of a data op eration but also changes the status register.
Status register - Status
The 8-bit status register (0AH) contains the zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag (OV), power down flag (PD) and watch dog time-out flag (TO). The status register not only records the status information but also controls the operation sequence.
With the exception of the TO and PD flags, bits in the status register can be altered by instruc tions like most other registers. Any data writ ten into the status register will not change the TO or PD flags. It should be noted that opera­tions related to the status register may give dif­ferent results from those intended. The TO and PD flags can only be changed by system power up, Watchdog Timer overflow, executing the HALT instruction and clearing the Watchdog Timer.
The Z, OV, AC and C flags generally reflect the status of the latest operations.
In addition, on entering an interrupt sequence or executing a subroutine call, the status regis ter will not be automatically pushed onto the stack. If the contents of status are important and if the subroutine can corrupt the status register, precaution must be taken to save it properly.
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10 April 20, 2000
Page 11
Preliminary
HT82K68A
Interrupt
The HT82K68A provides an internal timer counter interrupt. The interrupt control regis ter (INTC;0BH) contains the interrupt control bits to set not only the enable/disable status but also the interrupt request flags.
Once an interrupt subroutine is serviced, all other interrupts will be blocked (by clearing the EMI bit). This scheme may prevent any further interrupt nesting. Other interrupt requests may occur during this interval but only the interrupt request flag is recorded. If a certain interrupt re quires servicing within the service routine, the EMI bit and the corresponding bit of the INTC may be set to allow interrupt nesting. If the stack is full, the interrupt request will not be ac knowledged, even if the related interrupt is en abled, until the SP is decremented. If immediate service is desired, the stack must be prevented from becoming full.
All these kinds of interrupt have the wake-up capability. As an interrupt is serviced, a control transfer occurs by pushing the program counter onto the stack followed by a branch to a subrou tine at the specified location in the program
memory. Only the program counter is pushed onto the stack. If the contents of the register and Status register (STATUS) are altered by the in
­terrupt service program which corrupt the de
sired control sequence, the contents should be saved in advance.
The internal timer counter interrupt is initialized by setting the timer counter interrupt request flag (T0F; bit 5 of INTC), which is normally caused by a timer counter overflow. When the in terrupt is enabled, and the stack is not full and the T0F bit is set, a subroutine call to location
­08H will occur. The related interrupt request flag
(T0F) will be reset and the EMI bit cleared to dis able further interrupts.
During the execution of an interrupt subroutine,
­other interrupt acknowledgements are held un
­til the RETI instruction is executed or the EMI bit and the related interrupt control bit are set to 1 (if the stack is not full). To return from the in terrupt subroutine, a RET or RETI instruction may be invoked. RETI will set the EMI bit to en able an interrupt service, but RET will not.
Interrupts occurring in the interval between
­the rising edges of two consecutive T2 pulses,
-
-
-
-
-
-
-
Labels Bits Function
C is set if the operation results in a carry during an addition operation or if a bor-
C0
AC 1
Z2
OV 3
PD 4
TO 5
¾ ¾
row does not take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through carry instruction.
AC is set if the operation results in a carry out of the low nibbles in addition or if no borrow from the high nibble into the low nibble in subtraction; otherwise AC is cleared.
Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is cleared.
OV is set if the operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise OV is cleared.
PD is cleared when either a system power-up or executing the CLR WDT in struction. PD is set by executing the HALT instruction.
TO is cleared by a system power-up or executing the CLR WDT or HALT in struction. TO is set by a WDT time-out.
6 Undefined, read as "0"
7 Undefined, read as "0"
Status register
11 April 20, 2000
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Page 12
Preliminary
HT82K68A
will be serviced on the latter of the two T2 pulses, if the corresponding interrupts are en abled. In the case of simultaneous requests, the following table shows the priority that is ap plied. These can be masked by resetting the EMI bit.
No. Interrupt Source Vector
a Timer counter overflow 08H
The timer counter interrupt request flag (T0F), enable timer counter bit (ET0I), and enable master interrupt bit (EMI) constitute an inter rupt control register (INTC) which is located at 0BH in the data memory. EMI, ET0I, are used to control the enabling/disabling of interrupts. These bits prevent the requested interrupt from being serviced. Once the interrupt request flags (T0F) are set, they will remain in the INTC register until the interrupts are serviced or cleared by a software instruction.
It is suggested that a program does not use the ²CALL subroutine² within the interrupt sub routine. Because interrupts often occur in an un predictable manner or need to be serviced immediately in some applications, if only one stack is left and enabling the interrupt is not well
controlled, once the ²CALL subroutine² operates in
-
the interrupt subroutine it will damage the original control sequence.
-
Oscillator configuration
There are two oscillator circuits in HT82K68A.
V
DD
OSC1
-
f
OSC2
Crystal Oscillator RC Oscillator
(NMOS Open Drain Output)
/4
SYS
System oscillator
Both are designed for system clocks; the RC os cillator and the Crystal oscillator, which are de termined by mask options. No matter what
-
oscillator type is selected, the signal provides
-
the system clock. The HALT mode stops the system oscillator and resists the external signal to conserve power.
OSC1
OSC2
-
-
Register Bit No. Label Function
Controls the master (global) interrupt (1= enabled; 0= disabled)
Undefined, read as "0"; programming must be "0"
Controls the timer counter interrupt (1= enabled; 0= disabled)
Undefined, read as "0"
Undefined, read as "0"; programming must be "0"
Internal timer counter request flag (1= active; 0= inactive)
Undefined, read as "0"
Unused bit, read as "0"
INTC
(0BH)
0 EMI
1
¾
2 ET0I
3
4
¾ ¾
5 T0F
6
7
¾ ¾
INTC register
12 April 20, 2000
Page 13
Preliminary
HT82K68A
If an RC oscillator is used, an external resistor between OSC1 and VDD is needed and the re sistance must range from 51kW to 1MW. The system clock, divided by 4, is available on OSC2, which can be used to synchronize exter nal logic. The RC oscillator provides the most cost effective solution. However, the frequency of the oscillation may vary with VDD, tempera ture and the chip itself due to process varia tions. It is, therefore, not suitable for timing sensitive operations where accurate oscillator frequency is desired.
If the Crystal oscillator is used, a crystal across OSC1 and OSC2 is needed to provide the feed back and phase shift needed for oscillator, no other external components are needed. Instead of a crystal, the resonator can also be connected between OSC1 and OSC2 to get a frequency ref erence, but two external capacitors in OSC1 and OSC2 are required.
The WDT oscillator is a free running on-chip RC oscillator, and no external components are required. Even if the system enters the power down mode, the system clock is stopped, but the WDT oscillator still works for a period of ap proximately 78 ms. The WDT oscillator can be disabled by mask option to conserve power.
Watchdog Timer - WDT
The WDT clock source is implemented by a ded­icated RC oscillator (WDT oscillator) or instruc­tion clock (system clock divided by 4), decided by mask options. This timer is designed to pre­vent a software malfunction or sequence jump­ing to an unknown location with unpredictable results. The Watchdog Timer can be disabled by mask option. If the Watchdog Timer is disabled, all the executions related to the WDT results in no operation.
Once the internal WDT oscillator (RC oscillator normally with a period of 78ms) is selected, it is first divided by 256 (8-stages) to get the nomi nal time-out period of approximately 20 ms. This time-out period may vary with tempera ture, VDD and process variations. By invoking the WDT prescaler, longer time-out periods can be realized. Writing data to WS2, WS1, WS0 (bit 2,1,0 of the WDTS) can give different
time-out periods. If WS2, WS1, WS0 are all equal to 1, the division ratio is up to 1:128, and
­the maximum time-out period is 2.6 seconds.
If the WDT oscillator is disabled, the WDT clock
­may still come from the instruction clock and
operate in the same manner except that in the HALT state the WDT may stop counting and
­lose its protecting purpose. In this situation the
­WDT logic can be restarted by external logic.
The high nibble and bit 3 of the WDTS are re served for user defined flags, which can be used to indicate some specified status.
If the device operates in a noisy environment,
­using the on-chip RC oscillator (WDT OSC) is
strongly recommended, since the HALT will stop the system clock.
-
-
-
-
WS2 WS1 WS0 Division Ratio
000 1:1
001 1:2
010 1:4
011 1:8
1 0 0 1:16
1 0 1 1:32
1 1 0 1:64
1 1 1 1:128
WDTS register
The WDT overflow under normal operation will initialize ²chip reset² and set the status bit TO. An overflow in the HALT mode, initializes a ²warm reset² only when the PC and SP are reset to zero. To clear the contents of the WDT (including the WDT prescaler ), three methods are adopted; ex ternal reset (a low level to RESET struction(s), or a HALT instruction. There are two types of software instructions; CLR WDT and CLR WDT1/CLR WDT2. Of these two types of in struction, only one can be active depending on the mask option -²CLR WDT times selection option². If the ²CLR WDT² is selected (ie. CLR WDT times equal one), any execution of the CLR WDT in struction will clear the WDT. In case ²CLR WDT1² and ²CLR WDT2² are chosen (ie. CLRWDT times equal two), these two instructions must be exe
), software in
-
-
-
-
-
-
13 April 20, 2000
Page 14
Preliminary
HT82K68A
cuted to clear the WDT; otherwise, the WDT may reset the chip because of the time-out.
Power down operation - HALT
The HALT mode is initialized by the HALT in struction and results in the following...
·
The system oscillator will turn off but the WDT oscillator keeps running (if the WDT os cillator is selected).
·
The contents of the on chip RAM and regis ters remain unchanged.
·
WDT and WDT prescaler will be cleared and recount again (if the WDT clock has come from the WDT oscillator).
·
All I/O ports maintain their original status.
·
The PD flag is set and the TO flag is cleared.
The system can leave the HALT mode by means of an external reset, an external falling edge signal on port A and port C [0:3] or a WDT over flow. An external reset causes a device initializa tion and the WDT overflow performs a ²warm reset². Examining the TO and PD flags, the rea son for chip reset can be determined. The PD flag is cleared when system power-up or executing the CLR WDT instruction and is set when the HALT instruction is executed. The TO flag is set if the WDT time-out occurs, and causes a wake-up that only resets the PC and SP, the others keep their original status.
The port A or port C [0:3] wake-up can be con­sidered as a continuation of normal execution. Each bit in port A can be independently se­lected to wake up the device by mask option. Awakening from an I/O port stimulus, the pro­gram will resume execution of the next instruc tion.
Once a wake-up event occurs, and the system clock comes from a crystal, it takes 1024 t (system clock period) to resume normal opera tion. In other words, the HT82K68A will insert a dummy period after the wake-up. If the sys
­tem clock comes from an RC oscillator, it contin
ues operating immediately. If the wake-up results in next instruction execution, this will
-
execute immediately after the dummy period is completed.
­To minimize power consumption, all I/O pins
should be carefully managed before entering the HALT status.
Reset
There are three ways in which a reset can occur:
·
RESET reset during normal operation
·
RESET reset during HALT
-
-
-
VDD
RESET
SST Tim e-out
C hip R eset
t
Reset timing chart
·
WDT time-out reset during normal operation
The WDT time-out during HALT is different from other chip reset conditions, since it can perform a warm reset that just resets the PC and SP, leaving the other circuits to remain in their original state. Some registers remain un­changed during other reset conditions. Most
­registers are reset to the ²initial condition²
SYS
-
-
-
SST
S ystem clock/4
WDT OSC
Mask Option Select
8-bit C ounter
Watchdog Timer
W D T P resca le r
7-bit C ounter
8 -to -1 M U X
W DT Tim e-out
14 April 20, 2000
WS0~WS2
Page 15
Preliminary
V
DD
RESET
Reset circuit
when the reset conditions are met. By examin ing the PD and TO flags, the program can dis tinguish between different ²chip resets².
TO PD RESET Conditions
0 0 RESET
uu
RESET operation
0 1 RESET
1u
WDT time-out during normal operation
1 1 WDT wake-up HALT
Note: ²u² means ²unchanged²
To guarantee that the system oscillator has started and stabilized, the SST (System Start-up Timer) provides an extra-delay of 1024 system clock pulses when the system powers up or when it awakes from the HALT state.
HALT
WDT
WDT
Tim e-out
Reset
RESET
SST
OSC1
10-stage
R ipple C ounter
Power-on Detection
Reset configuration
reset during power-up
reset during normal
wake-up HALT
W arm R eset
Cold Reset
HT82K68A
When a system power-up occurs, the SST delay is added during the reset period. But when the reset comes from the RESET is disabled. Any wake-up from HALT will en able the SST delay.
The functional unit chip reset status is shown below.
PC 000H
Prescaler Clear
Clear. After master re
WDT
-
-
set, WDT begins count ing
Timer counter Off
Input/output ports Input mode
SP
Points to the top of the stack
Timer counter
A timer counter (TMR) is implemented in the HT82K68A. The timer counter contains an 8-bit programmable count-up counter and the clock may come from the system clock divided by 4.
Using the internal instruction clock, there is only one reference time-base.
There are two registers related to the timer counter; TMR ([0DH]), TMRC ([0EH]). Two physical registers are mapped to TMR location; writing TMR makes the starting value be placed in the timer counter preload register and reading TMR gets the contents of the timer counter. The TMRC is a timer counter control register, which defines some options.
In the timer mode, once the timer counter starts counting, it will count from the current contents in the timer counter to FFH. Once overflow occurs, the counter is reloaded from the timer counter preload register and gener ates the interrupt request flag (TF; bit 5 of INTC) at the same time.
pin, the SST delay
-
-
-
-
15 April 20, 2000
Page 16
Preliminary
HT82K68A
To enable the counting operation, the timer ON bit (TON; bit 4 of TMRC) should be set to 1. In the case of timer counter OFF condition, writing data to the timer counter preload reg ister will also reload that data to the timer counter. But if the timer counter is turned on, data written to it will only be kept in the timer counter preload register. The timer coun ter will still operate until overflow occurs. When the timer counter (reading TMR) is read, the clock will be blocked to avoid errors. As clock blocking may results in a counting error, this must be taken into consideration by the program
Input/output ports
There are 32 bidirectional input/output lines in the HT82K68A, labeled from PA to PE, which
­are mapped to the data memory of [12H], [14H],
[16H], [18H] and [1AH] respectively. All these I/O ports can be used for input and output opera tions. For input operation, these ports are
­non-latching, that is, the inputs must be ready
at the T2 rising edge of instruction MOV A,[m] (m=12H, 14H, 16H, 18H or 1AH). For output op eration, all data is latched and remains un changed until the output latch is rewritten.
-
mer.
Label Bits Function
¾
TON 4
¾
TM0 TM1
0~3 Unused bits, read as "0"
To enable/disable timer counting (0= disabled; 1= enabled)
5 Unused bits, read as "0"
6 7
10= Timer mode (internal clock)
TMRC register
-
-
-
S ystem C lock/4
TM 1 TM 0 TO N
TM 1 TM 0
Pulse W idth M easurem ent M ode C ontrol
Data Bus
Tim er C ounter
Preload R egister
Tim er
C ounter
R eload
O verflow to Interrupt
Timer counter
16 April 20, 2000
Page 17
Preliminary
The state of the registers is summarized in the following table:
Register
TMR xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu
TMRC 00-0 1--- 00-0 1--- 00-0 1--- 00-0 1--- uu-u u---
PC 000H 000H 000H 000H
MP0 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu
MP1 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu
ACC xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu
TBLP xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu
TBLH -xxx xxxx -uuu uuuu -uuu uuuu -uuu uuuu -uuu uuuu
STATUS --00 xxxx --1u uuuu --uu uuuu --01 uuuu --11 uuuu
INTC -000 0000 -000 0000 -000 0000 -000 0000 -uuu uuuu
WDTS 0000 0111 0000 0111 0000 0111 0000 0111 uuuu uuuu
PA 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu
PAC 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu
PB 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu
PBC 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu
PC 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu
PCC 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu
PD 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu
PDC 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu
PE ---1 1111 ---1 1111 ---1 1111 ---1 1111 ---u uuuu
PEC ---1 1111 ---1 1111 ---1 1111 ---1 1111 ---u uuuu
Reset
(power on)
WDT time-out
(normal
operation)
RESET
operation)
reset
(normal
RESET
(HALT)
reset
HT82K68A
WDT
time-out
(HALT)
000H*
Note:
²*² means warm reset ²u² means unchanged ²x² means unknown
17 April 20, 2000
Page 18
Preliminary
HT82K68A
Each I/O line has its own control register (PAC, PBC, PCC, PDC, PEC) to control the input/out put configuration. With this control register, CMOS output or schmitt trigger input with or without pull-high resistor (mask option) struc tures can be reconfigured dynamically (i.e., on-the-fly) under software control. To function as an input, the corresponding latch of the control register must write ²1². The pull-high resistance will exhibit automatically if the pull-high option is selected. The input source(s) also depend(s) on the control register. If the control register bit is ²1², input will read the pad state. If the control register bit is ²0², the contents of the latches will move to the internal bus. The latter is possible in ²read-modify-write² instruction. For output func tion, CMOS is the only configuration. These con trol registers are mapped to locations 13H, 15H, 17H, 19H and 1BH.
Data Bus
W rite C ontrol R egister
C hip R eset
R ead C ontrol R egister
W rite I/O
D
CK
D
CK
Q
Q
S
Q
Q
S
After a chip reset, these input/output lines stay at high levels or floating (mask option). Each
­bit of these input/output latches can be set or cleared by the SET [m].i or CLR [m].i (m=12H, 14H, 16H, 18H or 1AH) instruction.
-
Some instructions first input data and then fol low the output operations. For example, the SET [m].i, CLR [m].i, CPL [m] and CPLA [m] instructions read the entire port states into the CPU, execute the defined operations (bit-operation), and then write the results back to the latches or the accumulator.
Each line of port A and port C [0:3] has the capa bility to wake-up the device.
-
-
V
DD
W eak
V
DD
Pull-up
M a sk O p tion
PA0~PA7 PB0~PB7 PC0~PC 7 PD0~PD 7 PE0~PE4
-
-
R ead I/O
System W ake-up (P A & P C 0~P C 3 only)
M U X
M a sk O p tion
Input/output ports
18 April 20, 2000
Page 19
Preliminary
Mask option
The following shows five kinds of mask option in the HT82K68A. All the mask options must be de fined to ensure proper system function.
No. Mask Option
OSC type selection. This option is to decide if an RC or Crystal oscillator is chosen as
1
2
3
4
5
6
system clock. If the Crystal oscillator is selected, the XST (Crystal Start-up Timer) default is activated, otherwise the XST is disabled.
WDT source selection. There are three types of selection: on-chip RC oscillator, in struction clock or disable the WDT.
CLRWDT times selection. This option defines the way to clear the WDT by instruc tion. ²One time² means that the CLR WDT instruction can clear the WDT. ²Two times² means only if both of the CLR WDT1 and CLR WDT2 instructions have been executed, only then will the WDT be cleared.
Wake-up selection. This option defines the wake-up function activity. External I/O pins (PA and PC [0:3] only) all have the capability to wake-up the chip from a HALT.
Pull-high selection. This option is to decide whether the pull-high resistance is visi ble or not in the input mode of the I/O ports. Each bit of an I/O port can be independ ently selected.
Special power on reset. This option defines the function will reset the chip to prevent incorrect status. If the special power on reset is enabled, the chip must not enter the HALT mode.
HT82K68A
-
-
-
-
-
19 April 20, 2000
Page 20

Application Circuits

Preliminary
HT82K68A
R C o s c illa to r fo r m u ltip le I/O a p p lic a tio n s
V
DD
F.B.
(N M O S O pen D rain O utput)
f
/4
SYS
V
DD
VDD
0.1
m10m
V
DD
OSC1
OSC2
V
DD
RESET RESET
CAP
NUM
SCR
CLK
CLK
DATA
DATA
HT82K68A
PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PC6 PC7
C0 C1 C2 C3 C4 C5 C6 C7 R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17
C r y s ta l o s c illa to r o r c e r a m ic r e s o n a to r fo r m u ltip le I/O a p p lic a t io n s
V
DD
F.B.
Reserve for
R esonator
V
DD
0.1
V
CLK
DATA
VDD
m10m
OSC1
OSC2
DD
CAP
NUM
SCR
CLK
DATA
HT82K68A
PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB3 PB4 PB5 PB6
PB7 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PC6 PC7
C0 C1 C2 C3 C4 C5 C6 C7 R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17
20 April 20, 2000
Page 21
Preliminary
HT82K68A

Instruction Set Summary

Mnemonic Description Flag Affected
Arithmetic
ADD A,[m] ADDM A,[m] ADD A,x ADC A,[m] ADCM A,[m] SUB A,x SUB A,[m] SUBM A,[m] SBC A,[m] SBCM A,[m]
DAA [m]
Logic Operation
AND A,[m] OR A,[m] XOR A,[m] ANDM A,[m] ORM A,[m] XORM A,[m] AND A,x OR A,x XOR A,x CPL [m] CPLA [m]
Increment & Decrement
INCA [m] INC [m] DECA [m] DEC [m]
Rotate
RRA [m] RR [m] RRCA [m] RRC [m] RLA [m] RL [m] RLCA [m] RLC [m]
Add data memory to ACC Add ACC to data memory Add immediate data to ACC Add data memory to ACC with carry Add ACC to register with carry Subtract immediate data from ACC Subtract data memory from ACC Subtract data memory from ACC with result in data memory Subtract data memory from ACC with carry Subtract data memory from ACC with carry with result in data memory Decimal adjust ACC for addition with result in data memory
AND data memory to ACC OR data memory to ACC Exclusive-OR data memory to ACC AND ACC to data memory OR ACC to data memory Exclusive-OR ACC to data memory AND immediate data to ACC OR immediate data to ACC Exclusive-OR immediate data to ACC Complement data memory Complement data memory with result in ACC
Increment data memory with result in ACC Increment data memory Decrement data memory with result in ACC Decrement data memory
Rotate data memory right with result in ACC Rotate data memory right Rotate data memory right through carry with result in ACC Rotate data memory right through carry Rotate data memory left with result in ACC Rotate data memory left Rotate data memory left through carry with result in ACC Rotate data memory left through carry
Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV
None
None None
C
Z Z Z Z Z Z Z Z Z Z Z
Z Z Z Z
C C
C C
21 April 20, 2000
Page 22
Preliminary
Mnemonic Description Flag Affected
Data Move
MOV A,[m] MOV [m],A MOV A,x
Bit Operation
CLR [m].i SET [m].i
Branch
JMP addr SZ [m] SZA [m] SZ [m].i SNZ [m].i SIZ [m] SDZ [m] SIZA [m] SDZA [m] CALL addr RET RET A,x RETI
Table Read
TABRDC [m] TABRDL [m]
Miscellaneous
NOP CLR [m] SET [m] CLR WDT CLR WDT1 CLR WDT2 SWAP [m] SWAPA [m] HALT
Move data memory to ACC Move ACC to data memory Move immediate data to ACC
Clear bit of data memory Set bit of data memory
Jump unconditional Skip if data memory is zero Skip if data memory is zero with data movement to ACC Skip if bit i of data memory is zero Skip if bit i of data memory is not zero Skip if increment data memory is zero Skip if decrement data memory is zero Skip if increment data memory is zero with result in ACC Skip if decrement data memory is zero with result in ACC Subroutine call Return from subroutine Return from subroutine and load immediate data to ACC Return from interrupt
Read ROM code (current page) to data memory and TBLH Read ROM code (last page) to data memory and TBLH
No operation Clear data memory Set data memory Clear Watchdog Timer Pre-clear Watchdog Timer Pre-clear Watchdog Timer Swap nibbles of data memory Swap nibbles of data memory with result in ACC Enter power down mode
HT82K68A
None None None
None None
None None None None None None None None None None None None None
None None
None None None
TO,PD TO*,PD* TO*,PD*
None None
TO,PD
Note: x: 8-bit immediate data m: 7-bit data memory address
A: Accumulator i: 0~7 number of bits
addr: 12 bits program memory address
-: Flag(s) is not affected *: Flag(s) may be affected by the execution status
Ö: 0~7 number of bits
22 April 20, 2000
Page 23
Preliminary
HT82K68A

Instruction Definition

ADC A,[m] Add data memory and carry to the accumulator
Description The contents of the specified data memory, accumulator and the carry flag
are added simultaneously, leaving the result in the accumulator.
Operation
Affected flag(s)
ADCM A,[m] Add the accumulator and carry to data memory
Description The contents of the specified data memory, accumulator and the carry flag
Operation
Affected flag(s)
ADD A,[m] Add data memory to the accumulator
Description The contents of the specified data memory and the accumulator are added.
Operation
Affected flag(s)
ACC ¬ ACC+[m]+C
TC2 TC1 TO PD OV Z AC C
¾¾¾¾ÖÖÖÖ
are added simultaneously, leaving the result in the specified data memory. [m] ¬ ACC+[m]+C
TC2 TC1 TO PD OV Z AC C
¾¾¾¾ÖÖÖÖ
The result is stored in the accumulator. ACC ¬ ACC+[m]
TC2 TC1 TO PD OV Z AC C
¾¾¾¾ÖÖÖÖ
ADD A,x Add immediate data to the accumulator
Description The contents of the accumulator and the specified data are added, leaving
the result in the accumulator.
Operation
Affected flag(s)
ACC ¬ ACC+x
TC2 TC1 TO PD OV Z AC C
¾¾¾¾ÖÖÖÖ
23 April 20, 2000
Page 24
Preliminary
ADDM A,[m] Add the accumulator to the data memory
Description The contents of the specified data memory and the accumulator are added.
The result is stored in the data memory.
Operation
Affected flag(s)
AND A,[m] Logical AND accumulator with data memory
Description Data in the accumulator and the specified data memory perform a bitwise
Operation
Affected flag(s)
AND A,x Logical AND immediate data to the accumulator
Description Data in the accumulator and the specified data perform a bitwise logi
Operation
Affected flag(s)
[m] ¬ ACC+[m]
TC2 TC1 TO PD OV Z AC C
¾¾¾¾ÖÖÖÖ
logical_AND operation. The result is stored in the accumulator. ACC ¬ ACC ²AND² [m]
TC2 TC1 TO PD OV Z AC C
¾¾¾¾¾Ö¾¾
cal_AND operation. The result is stored in the accumulator. ACC ¬ ACC ²AND² x
TC2 TC1 TO PD OV Z AC C
¾¾¾¾¾Ö¾¾
HT82K68A
-
ANDM A,[m] Logical AND data memory with the accumulator
Description Data in the specified data memory and the accumulator perform a bitwise
logical_AND operation. The result is stored in the data memory.
Operation
Affected flag(s)
[m] ¬ ACC ²AND² [m]
TC2 TC1 TO PD OV Z AC C
¾¾¾¾¾Ö¾¾
24 April 20, 2000
Page 25
Preliminary
CALL addr Subroutine call
Description The instruction unconditionally calls a subroutine located at the indicated
address. The program counter increments once to obtain the address of the next instruction, and pushes this onto the stack. The indicated address is then loaded. Program execution continues with the instruction at this ad dress.
Operation
Affected flag(s)
CLR [m] Clear data memory
Description The contents of the specified data memory are cleared to zero.
Operation
Affected flag(s)
CLR [m].i Clear bit of data memory
Description The bit i of the specified data memory is cleared to zero.
Operation
Affected flag(s)
Stack ¬ PC+1 PC ¬ addr
TC2 TC1 TO PD OV Z AC C
¾¾¾¾¾¾¾¾
[m] ¬ 00H
TC2 TC1 TO PD OV Z AC C
¾¾¾¾¾¾¾¾
[m].i ¬ 0
TC2 TC1 TO PD OV Z AC C
¾¾¾¾¾¾¾¾
HT82K68A
-
CLR WDT Clear Watchdog Timer
Description The WDT and the WDT Prescaler are cleared (re-counting from zero). The
power down bit (PD) and time-out bit (TO) are cleared.
Operation
Affected flag(s)
WDT and WDT Prescaler ¬ 00H PD and TO ¬ 0
TC2 TC1 TO PD OV Z AC C
¾¾
00
25 April 20, 2000
¾¾¾¾
Page 26
Preliminary
CLR WDT1 Preclear Watchdog Timer
Description The TD, PD flags, WDT and the WDT Prescaler has cleared (re-counting
from zero), if the other preclear WDT instruction has been executed. Only ex ecution of this instruction without the other preclear instruction sets the in dicated flag which implies that this instruction has been executed and the TO and PD flags remain unchanged.
Operation
Affected flag(s)
CLR WDT2 Preclear Watchdog Timer
Description The TO, PD flags, WDT and the WDT Prescaler are cleared (re-counting
Operation
Affected flag(s)
WDT and WDT Prescaler ¬ 00H* PD and TO ¬ 0*
TC2 TC1 TO PD OV Z AC C
¾¾
from zero), if the other preclear WDT instruction has been executed. Only ex ecution of this instruction without the other preclear instruction sets the in dicated flag which implies that this instruction has been executed and the TO and PD flags remain unchanged.
WDT and WDT Prescaler ¬ 00H* PD and TO ¬ 0*
TC2 TC1 TO PD OV Z AC C
¾¾
0* 0*
0* 0*
¾¾¾¾
¾¾¾¾
HT82K68A
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-
-
-
CPL [m] Complement data memory
Description
Operation
Affected flag(s)
Each bit of the specified data memory is logically complemented (1¢s comple­ment). Bits which previously contained a 1 are changed to 0 and vice-versa.
[m] ¬ [m
TC2 TC1 TO PD OV Z AC C
]
¾¾¾¾¾Ö¾¾
26 April 20, 2000
Page 27
Preliminary
CPLA [m] Complement data memory and place result in the accumulator
Description
Operation
Affected flag(s)
DAA [m] Decimal-Adjust accumulator for addition
Description The accumulator value is adjusted to the BCD (Binary Code Decimal) code.
Operation If ACC.3~ACC.0 >9 or AC=1
Affected flag(s)
Each bit of the specified data memory is logically complemented (1¢s comple ment). Bits which previously contained a 1 are changed to 0 and vice-versa. The complemented result is stored in the accumulator and the contents of the data memory remain unchanged.
ACC ¬ [m
TC2 TC1 TO PD OV Z AC C
¾¾¾¾¾Ö¾¾
The accumulator is divided into two nibbles. Each nibble is adjusted to the BCD code and an internal carry (AC1) will be done if the low nibble of the ac cumulator is greater than 9. The BCD adjustment is done by adding 6 to the original value if the original value is greater than 9 or a carry (AC or C) is set; otherwise the original value remains unchanged. The result is stored in the data memory and only the carry flag (C) may be affected.
then [m].3~[m].0 ¬ (ACC.3~ACC.0)+6, AC1=AC else [m].3~[m].0) ¬ (ACC.3~ACC.0), AC1=0 and If ACC.7~ACC.4+AC1 >9 or C=1 then [m].7~[m].4 ¬ ACC.7~ACC.4+6+AC1,C=1 else [m].7~[m].4 ¬ ACC.7~ACC.4+AC1,C=C
TC2 TC1 TO PD OV Z AC C
¾¾¾¾¾¾¾ Ö
]
HT82K68A
-
-
DEC [m] Decrement data memory
Description Data in the specified data memory is decremented by1.
Operation
Affected flag(s)
[m] ¬ [m] 1
TC2 TC1 TO PD OV Z AC C
¾¾¾¾¾Ö¾¾
27 April 20, 2000
Page 28
Preliminary
DECA [m] Decrement data memory and place result in the accumulator
Description Data in the specified data memory is decremented by 1, leaving the result in
the accumulator. The contents of the data memory remain unchanged.
Operation
Affected flag(s)
HALT Enter power down mode
Description This instruction stops program execution and turns off the system clock. The
Operation
Affected flag(s)
ACC ¬ [m] 1
TC2 TC1 TO PD OV Z AC C
¾¾¾¾¾Ö¾¾
contents of the RAM and registers are retained. The WDT and prescaler are cleared. The power down bit (PD) is set and the WDT time-out bit (TO) is cleared.
PC ¬ PC+1 PD ¬ 1 TO ¬ 0
TC2 TC1 TO PD OV Z AC C
¾¾
01
¾¾¾¾
HT82K68A
INC [m] Increment data memory
Description Data in the specified data memory is incremented by 1.
Operation
Affected flag(s)
INCA [m] Increment data memory and place result in the accumulator
Description Data in the specified data memory is incremented by 1, leaving the result in
Operation
Affected flag(s)
[m] ¬ [m]+1
TC2 TC1 TO PD OV Z AC C
¾¾¾¾¾Ö¾¾
the accumulator. The contents of the data memory remain unchanged. ACC ¬ [m]+1
TC2 TC1 TO PD OV Z AC C
¾¾¾¾¾Ö¾¾
28 April 20, 2000
Page 29
Preliminary
JMP addr Directly jump
Description The contents of the program counter are replaced with the directly-specified
address unconditionally, and control is passed to this destination.
Operation
Affected flag(s)
MOV A,[m] Move data memory to the accumulator
Description The contents of the specified data memory are copied to the accumulator.
Operation
Affected flag(s)
MOV A,x Move immediate data to the accumulator
Description The 8-bit data specified by the code is loaded into the accumulator.
Operation
Affected flag(s)
PC ¬ addr
TC2 TC1 TO PD OV Z AC C
¾¾¾¾¾¾¾¾
ACC ¬ [m]
TC2 TC1 TO PD OV Z AC C
¾¾¾¾¾¾¾¾
ACC ¬ x
TC2 TC1 TO PD OV Z AC C
¾¾¾¾¾¾¾¾
HT82K68A
MOV [m],A Move the accumulator to data memory
Description The contents of the accumulator are copied to the specified data memory (one
of the data memories).
Operation
Affected flag(s)
NOP No operation
Description No operation is performed. Execution continues with the next instruction.
Operation
Affected flag(s)
[m] ¬ ACC
TC2 TC1 TO PD OV Z AC C
¾¾¾¾¾¾¾¾
PC ¬ PC+1
TC2 TC1 TO PD OV Z AC C
¾¾¾¾¾¾¾¾
29 April 20, 2000
Page 30
Preliminary
OR A,[m] Logical OR accumulator with data memory
Description Data in the accumulator and the specified data memory (one of the data
memories) perform a bitwise logical_OR operation. The result is stored in the accumulator.
Operation
Affected flag(s)
OR A,x Logical OR immediate data to the accumulator
Description Data in the accumulator and the specified data perform a bitwise logical_OR
Operation
Affected flag(s)
ORM A,[m] Logical OR data memory with the accumulator
Description Data in the data memory (one of the data memories) and the accumulator
Operation
Affected flag(s)
ACC ¬ ACC ²OR² [m]
TC2 TC1 TO PD OV Z AC C
¾¾¾¾¾Ö¾¾
operation. The result is stored in the accumulator. ACC ¬ ACC ²OR² x
TC2 TC1 TO PD OV Z AC C
¾¾¾¾¾Ö¾¾
perform a bitwise logical_OR operation. The result is stored in the data memory.
[m] ¬ ACC ²OR² [m]
TC2 TC1 TO PD OV Z AC C
¾¾¾¾¾Ö¾¾
HT82K68A
RET Return from subroutine
Description The program counter is restored from the stack. This is a two-cycle instruc-
tion.
Operation
Affected flag(s)
PC ¬ Stack
TC2 TC1 TO PD OV Z AC C
¾¾¾¾¾¾¾¾
30 April 20, 2000
Page 31
Preliminary
RET A,x Return and place immediate data in the accumulator
Description The program counter is restored from the stack and the accumulator loaded
with the specified 8-bit immediate data.
Operation
Affected flag(s)
RETI Return from interrupt
Description The program counter is restored from the stack, and interrupts are enabled
Operation
Affected flag(s)
RL [m] Rotate data memory left
Description The contents of the specified data memory are rotated 1 bit left with bit 7 ro
Operation
Affected flag(s)
PC ¬ Stack ACC ¬ x
TC2 TC1 TO PD OV Z AC C
¾¾¾¾¾¾¾¾
by setting the EMI bit. EMI is the enable master (global) interrupt bit (bit 0; register INTC).
PC ¬ Stack EMI ¬ 1
TC2 TC1 TO PD OV Z AC C
¾¾¾¾¾¾¾¾
tated into bit 0. [m].(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
[m].0 ¬ [m].7
TC2 TC1 TO PD OV Z AC C
¾¾¾¾¾¾¾¾
HT82K68A
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RLA [m] Rotate data memory left and place result in the accumulator
Description Data in the specified data memory is rotated 1 bit left with bit 7 rotated into
bit 0, leaving the rotated result in the accumulator. The contents of the data memory remain unchanged.
Operation
Affected flag(s)
ACC.(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6) ACC.0 ¬ [m].7
TC2 TC1 TO PD OV Z AC C
¾¾¾¾¾¾¾¾
31 April 20, 2000
Page 32
Preliminary
RLC [m] Rotate data memory left through carry
Description The contents of the specified data memory and the carry flag are rotated 1 bit
left. Bit 7 replaces the carry bit; the original carry flag is rotated into the bit 0 position.
Operation
Affected flag(s)
RLCA [m] Rotate left through carry and place result in the accumulator
Description Data in the specified data memory and the carry flag are rotated 1 bit left.
Operation
Affected flag(s)
[m].(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6) [m].0 ¬ C C ¬ [m].7
TC2 TC1 TO PD OV Z AC C
¾¾¾¾¾¾¾ Ö
Bit 7 replaces the carry bit and the original carry flag is rotated into bit 0 po sition. The rotated result is stored in the accumulator but the contents of the data memory remain unchanged.
ACC.(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6) ACC.0 ¬ C C ¬ [m].7
TC2 TC1 TO PD OV Z AC C
¾¾¾¾¾¾¾ Ö
HT82K68A
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RR [m] Rotate data memory right
Description The contents of the specified data memory are rotated 1 bit right with bit 0
rotated to bit 7.
Operation
Affected flag(s)
[m].i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m].7 ¬ [m].0
TC2 TC1 TO PD OV Z AC C
¾¾¾¾¾¾¾¾
32 April 20, 2000
Page 33
Preliminary
RRA [m] Rotate right-place result in the accumulator
Description Data in the specified data memory is rotated 1 bit right with bit 0 rotated
into bit 7, leaving the rotated result in the accumulator. The contents of the data memory remain unchanged.
Operation
Affected flag(s)
RRC [m] Rotate data memory right through carry
Description The contents of the specified data memory and the carry flag are together ro
Operation
Affected flag(s)
ACC.(i) ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6) ACC.7 ¬ [m].0
TC2 TC1 TO PD OV Z AC C
¾¾¾¾¾¾¾¾
tated 1 bit right. Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position.
[m].i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m].7 ¬ C C ¬ [m].0
TC2 TC1 TO PD OV Z AC C
¾¾¾¾¾¾¾ Ö
HT82K68A
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RRCA [m] Rotate right through carry - place result in the accumulator
Description Data of the specified data memory and the carry flag are rotated 1 bit right.
Bit 0 replaces the carry bit and the original carry flag is rotated into the bit 7 position. The rotated result is stored in the accumulator. The contents of the data memory remain unchanged.
Operation
Affected flag(s)
ACC.i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6) ACC.7 ¬ C C ¬ [m].0
TC2 TC1 TO PD OV Z AC C
¾¾¾¾¾¾¾ Ö
33 April 20, 2000
Page 34
Preliminary
SBC A,[m] Subtract data memory and carry from the accumulator
Description Thecontents of thespecified data memory andthe complement ofthecarry flag
aresubtractedfromtheaccumulator,leaving the result in theaccumulator.
Operation
Affected flag(s)
SBCM A,[m] Subtract data memory and carry from the accumulator
Description The contents of the specified data memory and the complement of the carry
Operation
Affected flag(s)
SDZ [m] Skip if decrement data memory is 0
Description The contents of the specified data memory are decremented by 1. If the result
Operation
Affected flag(s)
ACC ¬ ACC+[m
TC2 TC1 TO PD OV Z AC C
¾¾¾¾ÖÖÖÖ
flag are subtracted from the accumulator, leaving the result in the data memory.
[m] ¬ ACC+[m
TC2 TC1 TO PD OV Z AC C
¾¾¾¾ÖÖÖÖ
is 0, the next instruction is skipped. If the result is 0, the following instruc tion, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (two cycles). Otherwise proceed with the next instruction (one cycle).
Skip if ([m]-1)=0, [m] ¬ ([m]-1)
TC2 TC1 TO PD OV Z AC C
¾¾¾¾¾¾¾¾
]+C
]+C
HT82K68A
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SDZA [m] Decrement data memory and place result in ACC, skip if 0
Description The contents of the specified data memory are decremented by 1. If the result
is 0, the next instruction is skipped. The result is stored in the accumulator but the data memory remains unchanged. If the result is 0, the following in struction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Affected flag(s)
Skip if ([m]-1)=0, ACC ¬ ([m]-1)
TC2 TC1 TO PD OV Z AC C
¾¾¾¾¾¾¾¾
34 April 20, 2000
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Page 35
Preliminary
SET [m] Set data memory
Description Each bit of the specified data memory is set to 1.
Operation
Affected flag(s)
SET [m].i Set bit of data memory
Description
Operation
Affected flag(s)
SIZ [m] Skip if increment data memory is zero
Description The contents of the specified data memory are incremented by 1. If the result
Operation
Affected flag(s)
[m] ¬ FFH
TC2 TC1 TO PD OV Z AC C
¾¾¾¾¾¾¾¾
Bit ²i² of the specified data memory is set to 1. [m].i ¬ 1
TC2 TC1 TO PD OV Z AC C
¾¾¾¾¾¾¾¾
is 0, the following instruction, fetched during the current instruction execu tion, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Skip if ([m]+1)=0, [m] ¬ ([m]+1)
TC2 TC1 TO PD OV Z AC C
¾¾¾¾¾¾¾¾
HT82K68A
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SIZA [m] Increment data memory and place result in ACC, skip if 0
Description The contents of the specified data memory are incremented by 1. If the result
is zero, the next instruction is skipped and the result is stored in the accumu­lator. The data memory remains unchanged. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Other wise proceed with the next instruction (1 cycle).
Operation
Affected flag(s)
Skip if ([m]+1)=0, ACC ¬ ([m]+1)
TC2 TC1 TO PD OV Z AC C
¾¾¾¾¾¾¾¾
35 April 20, 2000
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Page 36
Preliminary
HT82K68A
SNZ [m].i
Description
Operation
Affected flag(s)
SUB A,[m] Subtract data memory from the accumulator
Description The specified data memory is subtracted from the contents of the accumula
Operation
Affected flag(s)
SUBM A,[m] Subtract data memory from the accumulator
Description The specified data memory is subtracted from the contents of the accumula-
Operation
Affected flag(s)
Skip if bit ²i² of the data memory is not 0 If bit ²i² of the specified data memory is not zero, the next instruction is
skipped. If bit ²i² of the data memory is not 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Skip if [m].i¹0
TC2 TC1 TO PD OV Z AC C
¾¾¾¾¾¾¾¾
tor, leaving the result in the accumulator. ACC ¬ ACC+[m
TC2 TC1 TO PD OV Z AC C
¾¾¾¾ÖÖÖÖ
tor, leaving the result in the data memory. [m] ¬ ACC+[m
TC2 TC1 TO PD OV Z AC C
¾¾¾¾ÖÖÖÖ
]+1
]+1
-
SUB A,x Subtract immediate data from the accumulator
Description The immediate data specified by the code is subtracted from the contents of
the accumulator, leaving the result in the accumulator.
Operation
Affected flag(s)
ACC ¬ ACC+x
TC2 TC1 TO PD OV Z AC C
¾¾¾¾ÖÖÖÖ
+1
36 April 20, 2000
Page 37
Preliminary
SWAP [m] Swap nibbles within the data memory
Description The low-order and high-order nibbles of the specified data memory (one of
the data memories) are interchanged.
Operation
Affected flag(s)
SWAPA [m] Swap data memory-place result in the accumulator
Description The low-order and high-order nibbles of the specified data memory are inter
Operation
Affected flag(s)
SZ [m] Skip if data memory is 0
Description If the contents of the specified data memory are 0, the following instruction,
Operation Skip if [m]=0
Affected flag(s)
[m].3~[m].0 « [m].7~[m].4
TC2 TC1 TO PD OV Z AC C
¾¾¾¾¾¾¾¾
changed, writing the result to the accumulator. The contents of the data memory remain unchanged.
ACC.3~ACC.0 ¬ [m].7~[m].4 ACC.7~ACC.4 ¬ [m].3~[m].0
TC2 TC1 TO PD OV Z AC C
¾¾¾¾¾¾¾¾
fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (2 cycle).
TC2 TC1 TO PD OV Z AC C
¾¾¾¾¾¾¾¾
HT82K68A
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SZA [m] Move data memory to ACC, skip if 0
Description The contents of the specified data memory are copied to the accumulator. If
the contents is 0, the following instruction, fetched during the current in struction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Affected flag(s)
Skip if [m]=0, ACC ¬ [m]
TC2 TC1 TO PD OV Z AC C
¾¾¾¾¾¾¾¾
37 April 20, 2000
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Page 38
Preliminary
HT82K68A
SZ [m].i
Description
Operation Skip if [m].i=0
Affected flag(s)
TABRDC [m] Move the ROM code (current page) to TBLH and data memory
Description The low byte of ROM code (current page) addressed by the table pointer
Operation
Affected flag(s)
TABRDL [m] Move the ROM code (last page) to TBLH and data memory
Description The low byte of ROM code (last page) addressed by the table pointer (TBLP)
Operation
Affected flag(s)
Skip if bit ²i² of the data memory is zero If bit ²i² of the specified data memory is 0, the following instruction, fetched
during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
TC2 TC1 TO PD OV Z AC C
¾¾¾¾¾¾¾¾
(TBLP) is moved to the specified data memory and the high byte transferred to TBLH directly.
[m] ¬ ROM code (low byte) TBLH ¬ ROM code (high byte)
TC2 TC1 TO PD OV Z AC C
¾¾¾¾¾¾¾¾
is moved to the data memory and the high byte transferred to TBLH directly. [m] ¬ ROM code (low byte)
TBLH ¬ ROM code (high byte)
TC2 TC1 TO PD OV Z AC C
¾¾¾¾¾¾¾¾
XOR A,[m] Logical XOR accumulator with data memory
Description Data in the accumulator and the indicated data memory perform a bitwise
logical Exclusive_OR operation and the result is stored in the accumulator.
Operation
Affected flag(s)
ACC ¬ ACC ²XOR² [m]
TC2 TC1 TO PD OV Z AC C
¾¾¾¾¾Ö¾¾
38 April 20, 2000
Page 39
Preliminary
XORM A,[m] Logical XOR data memory with the accumulator
Description Data in the indicated data memory and the accumulator perform a bitwise
logical Exclusive_OR operation. The result is stored in the data memory. The 0 flag is affected.
Operation
Affected flag(s)
XOR A,x Logical XOR immediate data to the accumulator
Description Data in the the accumulator and the specified data perform a bitwise logical
Operation
Affected flag(s)
[m] ¬ ACC ²XOR² [m]
TC2 TC1 TO PD OV Z AC C
¾¾¾¾¾Ö¾¾
Exclusive_OR operation. The result is stored in the accumulator. The 0 flag is affected.
ACC ¬ ACC ²XOR² x
TC2 TC1 TO PD OV Z AC C
¾¾¾¾¾Ö¾¾
HT82K68A
39 April 20, 2000
Page 40
Preliminary
HT82K68A
Holtek Semiconductor Inc. (Headquarters)
No.3 Creation Rd. II, Science-based Industrial Park, Hsinchu, Taiwan, R.O.C. Tel: 886-3-563-1999 Fax: 886-3-563-1189
Holtek Semiconductor Inc. (Taipei Office)
5F, No.576, Sec.7 Chung Hsiao E. Rd., Taipei, Taiwan, R.O.C. Tel: 886-2-2782-9635 Fax: 886-2-2782-9636 Fax: 886-2-2782-7128 (International sales hotline)
Holtek Semiconductor (Hong Kong) Ltd.
RM.711, Tower 2, Cheung Sha Wan Plaza, 833 Cheung Sha Wan Rd., Kowloon, Hong Kong Tel: 852-2-745-8288 Fax: 852-2-742-8657
Copyright Ó 2000 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may pres ent a risk to human life due to malfunction or otherwise. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw.
40 April 20, 2000
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