Datasheet HSP43881 Datasheet (Intersil Corporation)

HSP43881

Data Sheet May 1999

Digital Filter

The HSP43881 is a video speed Digital Filter (DF) designed
to efficiently implement vectoroperations such as FIR digital
filters. It is comprised of eight filter cells cascaded internally
and a shift and add output stage, all in a single integrated
circuit. Each filter cell contains a 8 x 8-bit multiplier, three
decimation registers and a 26-bit accumulator. The output
stage contains an additional 26-bit accumulator which can
add the contents of any filter cell accumulator to the output
stage accumulatorshifted right by 8 bits. The HSP43881 has
a maximum sample rate of 30MHz. The effective multiply
accumulate (mac) rate is 240MHz.

The HSP43881 DF can be configured to process expanded
coefficient and word sizes. Multiple DFs can be cascaded for
larger filter lengths without degrading the sample rate or a
single DF can process larger filter lengths at less than
30MHz with multiple passes. The architecture permits
processing filter lengths of over 1000 taps with the
guarantee of no overflows. In practice, most filter coefficients
are less than 1.0, making even larger filter lengths possible.
The DF provides for 8-bit unsigned or two’s complement
arithmetic, independently selectable for coefficients and
signal data.

Each DF filter cell contains three resampling or decimation
registers which permit output sample rate reduction at rates

1

of

/2, 1/3 or 1/4 the input sample rate. These registers also
provide the capability to perform 2-D operations such as
matrix multiplication and N x N spatial
correlations/convolutions for image processing applications.

File Number

2758.4

Features

• Eight Filter Cells

• 0MHz to 30MHz Sample Rate

• 8-Bit Coefficients and Signal Data

• 26-Bit Accumulator Per Stage

• Filter Lengths Over 1000 Taps

• Expandable Coefficient Size, Data Size and Filter Length

• Decimation by 2, 3 or 4

Applications

• 1-D and 2-D FIR Filters

• Radar/Sonar

• Adaptive Filters

• Echo Cancellation

• Complex Multiply-Add

• Sample Rate Converters

Ordering Information

PART

NUMBER

HSP43881JC-20 0 to 70 84 Ld PLCC N84.1.15
HSP43881JC-25 0 to 70 84 Ld PLCC N84.1.15
HSP43881JC-30 0 to 70 84 Ld PLCC N84.1.15
HSP43881GC-20 0 to 70 85 Ld PGA G85.A
HSP43881GC-25 0 to 70 85 Ld PGA G85.A
HSP43881GC-30 0 to 70 85 Ld PGA G85.A

TEMP. RANGE

(oC) PACKAGE PKG. NO.

Block Diagram

VCCV

DIENB
CIENB

DCMO - 1

ERASE

CIN0 - 7

RESET

ADR0 - 2

RESET

SHADD

SENBL

SENBH

TCCI

CLK

CLK

5

DF
FILTER
CELL 0

5

5

3

ADR0, ADR1, ADR2

2

SS

DIN0 - DIN7 TCS

8

8

88

26

2

8

DF
FILTER
CELL 1

8

26

1

8

DF
FILTER
CELL 2

8

26

SUM0 - 25

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

8

DF
FILTER
CELL 3

OUTPUT

STAGE

8

26

MUX

26

26

8

DF
FILTER
CELL 4

http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999

8

26

8

DF
FILTER
CELL 5

8

26

8

DF
FILTER
CELL 6

8

26

8

DF
FILTER
CELL 7

26

8

TCCO
COUT0 - 7

COENB

Pinouts

HSP43881

85 PIN GRID ARRAY (PGA)

TOP VIEW, PINS DOWN

2173 4 5 6 8 9 10 11

V

A

B

C

D

E

F

G

H

J

K

COENB

V

SS

COUT7 ERASE DIN1 DIN2

V

CC

COUT5 COUT6

COUT3 COUT4

COUT1

V

COUT0 SHADD

SS

V

SS

ADR2 DCM0 CLK

ADR1

V

SUM25

CC

SENBH

SUM24

L

RESET

CC

DIN7

TCCO TCS

ALIGN

PIN

DIENB

COUT2

VCCSUM19

V

SS

DIN6 DIN3 DIN0 TCCI

CIENB

CIN7 CIN6 CIN4

DIN5 DIN4 CIN5 CIN3

CIN1

SUM0

SUM1

SUM16SUM17SUM20

SUM15 SUM12 SUM10 SUM8 SUM6

V

SS

SUM14SUM18SUM21SUM22SUM23DCM1

SUM13

V

CC

V

SS

HSP43881

TOP VIEW, PINS UP

1234567891011

V

V

CC

SS

V

CIN2

CIN0

SENBL

V

CCVSS

CC

SUM3 SUM2

SUM5 SUM4ADR0

V

SUM7

SS

SUM9SUM11

L

DCM1 SUM23 SUM22 SUM21 SUM18 SUM14 SUM13 SUM11 SUM9

K

SENBH SUM24 SUM19 SUM15 SUM12 SUM10 SUM8 SUM6

J

V

CC

H

ADR1

G

ADR2 DCM0 CLK

F

V

SS

E

COUT1

D

COUT3 COUT4

C

COUT5 COUT6

B

V

CC

A

V

SS

V

SSVCC

SUM25

ADR0

COUT0 SHADD

COUT2

V

SS

ALIGN

PIN

COENB V

CC

SUM20 SUM17 SUM16 SUM7

DIENB

ERASECOUT7 DIN8COUT8

RESET

V

CC

V

SS

DIN5 DIN4

DIN2DIN1

V

SUM1 SUM3 SUM2

SUM0

CIN1 CIN0

CIENB

DIN0DIN3DIN6DIN7

CIN8

SS

SUM5 SUM4

V

CIN2

CIN5 CIN3

V

V

CCVSS

SENBL

V

CIN4CIN6CIN7

CCVSS

SS

CC

2

HSP43881

Pinouts

(Continued)

SUM23
SUM22

V

CC

SUM21
SUM20
SUM19
SUM18

V

SS

SUM17
SUM16

V

CC

SUM15
SUM14
SUM13
SUM12

V

SS

SUM11
SUM10

SUM9
SUM8
SUM7

84 LEAD PLCC PACKAGE

BOTTOM VIEW

SS

SUM24

DCM1

V

111098765432184838281807978777675

12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32

33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53

SUM25

SENBH

CC

V

ADDR0

ADDR1

SS

DCM0

ADDR2

CLK

V

SHADD

COUT0

COUT1

SS

V

COUT2

COUT3

COUT4

COUT5

V

CC

COUT6

74

COUT7

73
72

V

SS

TCCO

71

COENB

70

V

69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54

CC

ERASE
RESET
DIENB
TCS
DIN7
DIN6
DIN5
DIN4
DIN3
DIN2
DIN1
DIN0
CIENB
TCCI
V

CC

SUM6

SS

V

SUM5

SUM4

CC

V

SUM3

SUM2

SUM1

SUM0

SS

V

NOTE: An overbar on a signal name represents an active LOW signal.

3

CIN0

SENBL

CIN1

CC

V

CIN2

CIN3

CIN4

CIN5

SS

V

CIN7

CIN6

HSP43881

Pin Description

PIN

SYMBOL

V

CC

V

SS

CLK G3 I The CLK input provides the DF system sample clock. The maximum clock frequency is 30MHz.

DIN0-7 A58, B67, C67 I These eight inputs are the data sample input bus. Eight bit data samples are synchronously loaded

TCS B5 I The TCS input determines the number system interpretation of the data input samples on pins

DIENB C5 I A low on this enables the data sample input bus (DIN0-7) to all the filter cells. A rising edge of the

CIN0-7 B9-11,

TCCI A9 I TheTCCI input determines the number system interpretation of the coefficient inputs on pins CIN07

CIENB B8 I A low on this input enable the C register of every filter cell and the D registers (decimation) of every

COUT0-7 B2, C1-2,

TCCO B3 O The TCCO three-state output determines the number system representation of the coefficients out-

COENB A2 I A low on the COENB input enables the COUT0-7 and the TCCO output. A high on this input places

NUMBER TYPE DESCRIPTION

A3, A10, B1,

D11, F10, J1,

K4, L7

A1, A11, E2,

F1, E11, H11,

K3, K6, L9

C10-11, D10,

E9-10

D1-2, E1, E3,

F2

+5V Power Supply Input.

Power Supply Ground Input.

through these pins to the X register of each filter cell simultaneously. The DIENB signal enables
loading, which is synchronous on the rising edge of the clock signal.

DIN0-7 as follows:

TCS = Low → Unsigned Arithmetic.

TCS = High → Two's Complement Arithmetic.
The TCS signal is synchronously loaded into the X register in the same way as the DIN0-7
inputs.

CLK signal occurring while DIENB is low will load the X register of every filter cell with the 8-bit value
present on DIN0-7. A high on this input forces all the bits of the data sample input bus to zero; a
rising CLK edge when DIENB is high will load the X register of every filter cell with all zeros. This
signal is latched inside the DF,delaying its effect by one clock internal to the DF. Therefore, it must
be low during the clock cycle immediately preceding presentation of the desired data on the
DIN0-7 inputs. Detailed operation is shown in later timing diagrams.

I These eight inputs are used to input the 8-bit coefficients. The coefficients are synchronously load-

ed into the C register of filter CELL 0 if a rising edge of CLK occurs while CIENB is low. The CIENB
signal is delayed by one clock as discussed below.

as follows:

TCCI = LOW E Unsigned Arithmetic.

TCCI = HIGH E Two's Complement Arithmetic.
The TCCI signal is synchronously loaded into the C register in the same way as the CIN0-7 inputs.

filter cell according to the state of the DCM0-1 inputs. A rising edge of the CLKsignaloccurring while
CIENB is low will load the C register and appropriate D registers with the coefficient data present at
their inputs. This provides the mechanism for shifting the coefficients from cell to cell through the
device. A high on this input freezes the contents of the C register and the D registers ignoring the
CLK signal. This signal is latched and delayed by one clock internal to the DF. Therefore, it must be
lowduring the clock cycle immediately preceding presentation of the desired coefficient of the CIN0­7 inputs. Detailed operation is shown in the Timing Diagrams Section.

O These eight three-state outputs are used to output the 8-bit coefficients from filter cell 7. These out-

puts are enabled by the COENB signal low. These outputs may be tied to the CIN0-7 inputs of the
same DF to recirculate the coefficients, or they may be tied to the CIN0-7 inputs of another DF to
cascade DFs for longer filter lengths.

put on COUTO-7. It tracks the TCCI signal to this same DF. It should be tied to the TCCI input of the
next DF in a cascade of DFs for increased filter lengths. This signal is enabled by COENB low.

all these outputs in their high impedance state.

4

HSP43881

Pin Description

SYMBOL

DCM0-1 G2, L1 These two inputs determine the use of the internal decimation registers as follows:

SUM0-25 J2, J5-8, J10,

SENBH K1 I A low on this input enables result bits SUM16-25. A high on this input places these bits in their high

SENBL E11 I A low on this input enables result bits SUM0-15. A high on this input places these bits in their high

ADR0-2 G1, H1-2 I These inputs select the one cell whose accumulator will be read through the output bus (SUM0-25)

SHADD F3 I The SHADD input controls the activation of the shift-and-add operation in the output stage. This

RESET A4 I A low on this input synchronously clears all the internal registers, except the cell accumulators. It

ERASE B4 I A low on this input synchronously clears the cell accumulator selected by the ADR0-1 signals. If

ALIGN PIN C3 Used for aligning chip in socket or printed circuit board. Must be left as a no connect in circuit.

(Continued)

PIN

NUMBER TYPE DESCRIPTION

DCM1 DCM0 Decimation Function

0 0 Decimation Registers not used.
0 1 One Decimation Register is used.
1 0 Two Decimation Registers are used.

1 1 Three Decimation Registers are used.
The coefficients pass from cell to cell at a rate determined by the number of decimation registers
used. When no decimation registers are used, coefficients move from cell to cell on each clock.
When one decimation register is used, coefficients move from cell to cell on every other clock, etc.
These signals are latched and delayed by one clock internal to the DF.

O These 26 three-state outputs are used to output the results of the internal filter cell computations.

K2, K5-11,

L-26, L8,

L10-11

Individual filter cell results or the result of the shift and add output stage can be output. If an individ­ual filter cell result is to be output, the ADR0-2 signals select the filter cell result. The SHADD signal
determines whether the selected filter cell result or the output stage adder result is output. The sig­nalsSENBHand SENBL enablethemostsignificantandleastsignificantbitsof the SUM0-25 result,
respectively. Both SENBH and SENBL may be enabled simultaneously if the system has a 26-bit or
larger bus. However, individual enables are provided to facilitate use with a 16-bit bus.

impedance state.

impedance state.

or added to the output stage accumulator. They also determine which accumulator will be cleared
when ERASE is low. For selection of which accumulator to read through the output bus (SUM0-25)
or which to add to the output stage accumulator, these inputs are latched in the DF and delayed by
one clock internal to the device. If the ADR0-2 lines remain at the same address for more than one
clock, the output at SUM0-25 will not change to reflect any subsequent accumulator updates in the
addressed cell. Only the result available during the first clock, when ADR0-1 selects the cell, will be
output. This does not hinder normal operation since the ADR0-1 lines are changed sequentially.
This feature facilitates the interface with slow memories where the output is required to be fixed for
more than one clock.

signal is latched in the DF and delayed by one clock internal to the device. A detailed explanation is
given in the DF Output Stage Section.

can be used with ERASE to also clear all the accumulators simultaneously.This signal is latched in
the DF and delayed by one clock internal to the DF.

RESET is also low simultaneously, all cell accumulators are cleared.

Functional Description

The Digital Filter Processor (DF) is composed of eight filter cells
cascaded together and an output stage for combining or
selectingfilte5r cell outputs(See Block Diagram). Each filter cell
contains a multiplier accumulator and sever al registers (Figure

1). Each 8-bit coefficient is multiplied by an 8-bit data sample,
with the result added to the 26-bit accumulator contents. The
coefficient output of each cell is cascaded to the coefficient
input of the next cell to its right.

DF Filter Cell

An 8-bit coefficient (CIN0-7) enters each cell through the C
register on the left and exits the cell on the right as signals

5

COUT0-7. With no decimation, the coefficient moves directly
from the C register to the output, and is valid on the clock
following its entrance. When decimation is selected the
coefficient exit is delayed by 1, 2 or 3 clocks by passing through
one or more decimation registers (D1, D2 or D3).

The combination of D registers through which the coefficient
passes is determined by the state of DCM0 and DCM1. The
output signals (COUT0-7) are connected to the CIN0-7 inputs
of the next cell to its right. The COENB input signal enables the
COUT0-7 outputs of the right most cell to the COUT-07 pins of
the device.

The C and D registers are enabled for loading by CIENB .
Loading is synchronous with CLK when CIENB is low.Note that

HSP43881

CIENB is latched internally. It enab les the register for loading
after the next CLK follo wing the onset of CIENB low. Actual
loading occurs on the second CLK following the onset of
CIENB low . Theref ore , CIENB must be lo w during the clock
cycle immediately preceding presentation of the coefficient on
the CIN0-7 inputs. In most basic FIR operations, CIENB will be
low throughout the process, so this latching and delay
sequence is only important during the initialization phase.
When CIENB is high, the coefficients are frozen.

These registers are cleared synchronously under control of
RESET, which is latched and delayed exactly like CIENB . The
output of the C register (C0-8) is one input to 8 x 8 multiplier.

The other input to the 8 x 8 multiplier comes from the output of
the X register. This register is loaded with a data sample from
the device input signals DIN0-7 discussed above . The X
register is enabled for loading by DIENB . Loading is
synchronous with CLK when DIENB is low.Note that DIENB is
latched internally . It enables the register for loading after the
next CLK follo wing the onset of DIENB low. Actual loading
occurs on the second CLK following the onset of DIENB low;
therefore, DIENB must be low during the clock cycle
immediately preceding presentation of the data sample on the
DIN0-7 inputs. In most basic FIR operations, DIENB will be low
throughout the process, so this latching and delay sequence is
only important during the initialization phase. When DIENB is
high, the X register is loaded with all zeros.

The multiplier is pipelined and is modeled as a multiplier core
followedby two pipeline registers,MREG0 and MREG1 (Figure

1). The multiplier output is sign extended and input as one
operand of the 26-bit adder. The other adder operand is the
output of the 26-bit accumulator. The adder output is loaded
synchronously into both the accumulator and the TREG.

The TREG loading is disabled by the cell select signal,
CELLn, where n is the cell number. The cell select is decoded
from the ADR0-2 signals to generate the TREG load enable.
The cell select is inverted and applied as the load enable to
the TREG. Operation is such that the TREG is loaded
whenever the cell is not selected. Theref ore, TREG is loaded
every clock except the clock following cell selection. The
purpose of the TREG is to hold the result of a sum of products
calculation during the clock when the accumulator is cleared
to prepare for the next sum of products calculation. This
allows continuous accumulation without wasting clocks .

decoded from ADR0-2 and the

ERASE signal enable clearing

of the accumulator on the next CLK.
The

ERASE and RESET signals clear the DF internal

registers and states as follows:

ERASE RESET CLEARING EFFECT

1 1 No clearing occurs, internal state remains

same.

10RESET only active, all registers except accu-

mulators are cleared, including the internal
pipeline registers.

01ERASE only active, the accumulator whose

address is given by the ADR0-2 inputs is
cleared.

0 0 BothRESETandERASE active, all accumula-

tors, as well as all other registers are cleared.

The DF Output Stage

The output stage consists of a 26-bit adder, 26-bit register,
feedback multiplexer from the register to the adder, an output
multiplexer and a 26-bit three-state driv er stage (Figure 2).

The 26-bit output adder can add any filter cell accumulator
result to the 18 most significant bits of the output buffer. This
result is stored back in the output buffer. This operation takes
place in one clock period. The eight LSBs of the output buffer
are lost. The filter cell accumulator is selected by the ADR0-2
inputs.

The 18 MSBs of the output buffer actually pass through the
zero mux on their wayto the output adder input. The zero mux
is controlled by the SHADD input signal and selects either the
output buffer 18 MSBs or all zeros for the adder input. A low
on the SHADD input selects zero. A high on the SHADD input
selects the output buffer MSBs, thus , activating the shift and
add operation. The SHADD signal is latched and delayed b y
one clock internally.

The accumulator is loaded with the adder output every clock
unless it is cleared. It is cleared synchronously in two ways.
When

RESET and ERASE are both low, the accum ulator is
cleared along with all other registers on the device. Since
ERASE and RESET are latched and delayed one clock
internally , clearing occurs on the second CLK f ollo wing the
onset of both

ERASE and RESET low.

The second accumulator clearing mechanism clears a single
accumulator in a selected cell. The cell select signal, CELLn,

6

DCM1.D
DCM0.D

RESET.D

CIENB.D

TCCI

CIN0-7

HSP43881

THREE-STATE BUFFERS

1

MUX

ON CELL 7 ONLY

TCCO

LD CLR

C REG

7

C.TCCI

0-7

C0-7

LD CLR

D1 REG

1

MUX

LD CLR

D2 REG

LD CLR
D3 REG

RESET.D
DIENB.D

TCS

DIN0-7

DCM1
DCM0

RESET

DIENB
CIENB

ADR0

ADR1

ADR2

ERASE

CLK

B

LD CLR

X REG

7

CLK

LATCHES

DCM1.D
DCM0.D
RESET.D
DIENB.D
CIENB.D
ADR0.D
ADR1.D
ADR2.D
ERASE.D

CLK

0

C0-8

X0-8

RESET.D

ACC.D0-25

D.TCCI

D0-7

CLK

MULTIPLIER

X

CORE

P0-17

MREG0

CLR

MREG1

CLR

0

C

0-17 SIGN EXTENSION

COUT0-7

COENB

CLK

18-25

CLK

ADR0

ADR1

ADR2

DECODER

ADDER

ACC0-25

CELL 0
CELL 1

CELL 7

ERASE.D

CELLn

CELLn

CLK

D Q

ACC

CLR

T REG

LD

AOUT0-25

CLK

FIGURE 1. FILTER CELL

7

HSP43881

01 67

SHADD

18 MSBs SHIFTED

8 BITS TO RIGHT

RESET.D

CLR

Q

D

CLK

(BITS 0 - 17)

SHADD.D

ADR0.D-ADR2.D

SIGN EXT

18-25

18 (LSBs)
0-17

ZERO

MUX

01

18

0

RESET.D

CLR

DQ

8-25

SENBL

SENBH

3

CLK

26

0-18

18

8

2

THREE-STATE

26 26 26

CELL RESULT

MUX

26

+

26

OUTPUT
BUFFER

26

26

01

OUTPUT

MUX

26

BUFFER

RESET.D

FIGURE 2. DF OUTPUT STAGE

The 26 least significant bits (LSBs) from either a cell
accumulator or the output buffer are output on the SUM0-25
bus. The output mux determines whether the cell
accumulator selected by ADR0-2 or the output buffer is
output to the bus. This mux is controlled by the SHADD input
signal. Control is based on the state of the SHADD during
two successive clocks; in other words, the output mux
selection contains memory. If SHADD is low during a clock
cycle and was low during the previous clock, the output mux
selects the contents of the filter cell accumulator addressed
by ADR0-2. Otherwise the output mux selects the contents
of the output buffer.

If the ADR0-2 lines remain at the same address for more
than one clock, the output at SUM0-25 will not change to
reflect any subsequent accumulator updates in the
addressed cell. Only the result availableduring the first clock
when ADR0-2 selects the cell will be output. This does not
hinder normal FIR operation since the ADR0-2 lines are
changed sequentially. This feature facilitates the interface
with slow memories where the output is required to be fixed
for more than one clock.

CLK

26

SUM0-25

The SUM0-25 output bus is controlled by the SENBH and
SENBL signals. A low on SENBL enables bits SUM0-15. A
low on SENBH enables bits SUM16-25. Thus, all 26 bits can
be output simultaneously if the external system has a 26-bit
or larger bus. If the external system bus is only 16 bits, the
bits can be enabled in two groups of 16 and 10 bits (sign
extended).

DF Arithmetic

Both data samples and coefficients can be represented as
either unsigned or two's complement numbers. The TCS and
TCCI inputs determine the type of arithmetic representation.
Internally all values are represented by a 9-bit two's
complement number. The value of the additional ninth bit
depends on the arithmetic representation selected. For two's
complement arithmetic, the sign is extended into the ninth
bit. For unsigned arithmetic, bit-9 is 0.

The multiplier output is 18 bits and the accumulator is 26
bits. The accumulator width determines the maximum
possible number of terms in the sum of products without

8

HSP43881

overflow. The maximum number of terms depends also on
the number system and the distribution of the coefficient and
data values. Then maximum numbers of terms in the sum
products are:

MAX #

NUMBER SYSTEM

Two Unsigned Vectors 1032
Two Two's Complement:

• Two Positive Vectors

• Negative Vectors

• One Positive and One Negative Vector

One Unsigned and One Two's Complement
Vector:

• Positive Two's Complement Vector

• Negative Two's Complement Vector

X15...X9, X8, X7...X1, X

C0...C6, C7, C0...C6, C

OF TERMS

2080
2047

2064

1036
1028

TABLE 1. 30MHz, 8-TAP FIR FILTER SEQUENCE

0

7

For practical FIR filters, the coefficients are never all near
maximum value, so even larger vectors are possible in
practice.

Basic FIR Operation

A simple, 30MHz 8-tap filter example serves to illustrate
more clearly the operation of the DF. The sequence table
(Table 1) shows the results of the multiply accumulate in
each cell after each clock. The coefficient sequence, Cn,
enters the DF on the left and moves from left to right through
the cells. The data sample sequence, Xn, enters the DF from
the top, with each cell receiving the same sample
simultaneously. Each cell accumulates the sum of products
for one output point. Eight sums of products are calculated
simultaneously, but staggered in time so that a new output is
available every system clock.

HSP43881

Y15...Y

14,

...Y8, Y

7

CLK CELL 0 CELL 1 CELL 2 CELL 3 CELL 4 CELL 5 CELL 6 CELL 7 SUM/CLR

0C
1+C
2+C
3+C
4+C
5+C
6+C
7+C
8C

9+C
10 +C5 x X
11 +C4 x X
12 +C3 x X
13 +C2 x X
14 +C1 x X
15 +C0 x X

7

6
5
4
3
2
1
0

7

6

x X

x X
x X
x X
x X
x X
x X
x X

x X

x X

0

1
2
3
4
5
6
7

8

9
10
11
12
13
14
15

000 -

C7 x X
+C6 x X
+C5 x X
+C4 x X

C3 x X
+C2 x X
+C1 x X
+C0 x X

C7 x X

+C6 x X
+C5 x X
+C4 x X
+C3 x X
+C2 x X
+C1 x X

1

2
3
4

5

6
7

8
9
10
11
12
13
14
15

00 -

C7 x X
+C6 x X
+C5 x X
+C4 x X
+C3 x X
+C2 x X
+C1 x X
+C0 x X
C7 x X

+C6 x X
+C5 x X
+C4 x X
+C3 x X
+C2 x X

2

3
4
5
6
7
8
9

10

11
12
13
14
15

0-

C7 x X
+C6 x X
+C5 x X
+C4 x X
+C3 x X
+C2 x X
+C1 x X

+C0 x X

C7 x X

+C6 x X
+C5 x X
+C4 x X
+C3 x X

11

3

10

12
13
14
15

C7 x X

4
5
6
7
8
9

+C6 x X
+C5 x X
+C4 x X
+C3 x X

+C2 x X
+C1 x X
+C0 x X

C7 x X
+C6 x X
+C5 x X
+C4 x X

12

4

10
11

13
14
15

C7 x X

5
6
7
8
9

+C6 x X
+C5 x X
+C4 x X

+C3 x X
+C2 x X
+C1 x X
+C0 x X

C7 x X
+C6 x X
+C5 x X

13

5

10
11
12

14
15

C7 x X

6
7
8
9

+C6 x X
+C5 x X

+C4 x X
+C3 x X
+C2 x X
+C1 x X
+C0 x X
+C7 x X
+C6 x X

6

10
11
12
13
14
15

C7 x X

7
8
9

+C6 x X

+C5 x X
+C4 x X
+C3 x X
+C2 x X
+C1 x X
+C0 x X

C7 x X

7

8

9
10
11
12
13
14

15

-

-

-

­Cell 0 (Y7)
Cell 1 (Y8)
Cell 2 (Y9)

Cell 3 (Y10)
Cell 4 (Y11)
Cell 5 (Y12)
Cell 6 (Y13)
Cell 7 (Y14)
Cell 0 (Y15)

9

SAMPLE

DATA IN

(X

30MHz

CLOCK

HSP43881

)

n

3-BIT

COUNTER
Y

2Y1Y0

+5V

8

DIN0-7

DIENB

TCS

CLK

SYSTEM

RESET

ERASE

A2 A1 A0

D0-D7

8 x 8 COEFF.

RAM/ROM

TCCI

8

CIN0-7

FIGURE 3. 30MHZ, 8 TAP FIR FILTER APPLICATION SCHEMATIC

Detailed operation of the DF to perform a basic 8-tap, 8-bit
coefficient, 8-bit data, 30MHz FIR filter is best understood by
observing the schematic (Figure 3) and timing diagram
(Figure 4). The internal pipeline length of the DF is four (4)
clock cycles, corresponding to the register levels CREG (or
XREG), MREG0, MREG1, and TREG (Figures 1 and 2).
Therefore, the delay from presentation of data and
coefficients at the DIN0-7 and CIN0-7 inputs to a sum
appearing at the SUM0-25 output is:

k + Td

SS

SENBLSENBHSHADDV

SUM0-25

TCCO

COUT0-7

COENBV

SUM

26

OUT

)

(Y

n

NC

8

NC

ADR0ADR1ADR2

CC

HSP43881

ERASERESETDCM0DCM1CIENB

Extended FIR Filter Length

Filter lengths greater that eight taps can be created by either
cascading together multiple DF devices or “reusing” a single
device. Using multiple devices, an FIR filter of over 1000­taps can be constructed to operate at a 30MHz sample rate.
Using a single device clocked at 30MHz, a FIR filter of over
1000 taps can be constructed to operate at less than a
30MHz sample rate. Combinations of these two techniques
are also possible.

Where:
k = filter length
Td = 4, the internal pipeline delay of DF
After the pipeline has filled, a new output sample is available

every clock. The delay to last sample output from last
sample input is Td.

The output sums, Yn, shown in the Timing Diagram are
derived from the sum of products equation:

Y(n) = C(0) x X(n) + C(1) x X(n1) + C(2) x X(n -2) + C(3)
x X(n -3) + C(4) x X(n -4) + C(5) x X(n -5) + C(6) x X(n -6)
+ C(7) x X(n -7)

10

CLK

RESET

ERASE

DIN0-7
DIENB

HSP43881

01234567 98 1011121314151617181920

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

0

2

1

4

3

6

5

8

7

10

9

12

11

14

13

16

15

X

18

17

CIN0-7

CIENB

ADR0-2

SUM0-24

SHADD

SENBL

SENBH

DCM0-1

C7C6C5C4C3C2C1C0C7C6C5C4C3C2C1C0C7C6C

Y

7Y8Y9Y10Y11Y12Y13Y14

0

7

Y

N

CKX

∑

×

NK–

=

K0=

5

076543210

FIGURE 4. 30MHz, 8-TAP FIR FILTER TIMING

11

12

SAMPLE

DATA IN

(X

30MHz

CLOCK

)

n

CDQ

Q

+5V

+5V

SYSTEM

RESET

CLK

4-BIT

COUNTER

RESET

Y0
Y1

Y2
Y3

8x16 COEFF.

RAM/ROM

A0

D0-D7

A1
A2
A3

SUM0-24

COUT0-7

COENBV

SS

SENBLSENBHSHADDV

TCCO

25

8

8

DIN0-7

DIENB

TCS

CLK

TCCI

CIN0-7

ADR2ADR0ADR1

CC

8

DIN0-7

DIENB

TCS

CLK

TCCI

8

CIN0-7

HSP43881

DF0

ERASERESETDCM0DCM1CIENB

FIGURE 5. 30MHz, 16-TAP FIR FILTER CASCADE APPLICATION SCHEMATIC

ADR2ADR0ADR1

CC

HSP43881

DF1

SENBLSENBHSHADDV

SUM0-24

25

HSP43881

TCCO

COUT0-7

ERASERESETDCM0DCM1CIENB

SS

COENBV

NC

8

NC

SUM
OUT
(Y

)

n

HSP43881

Cascade Configuration

To design a filter length L>8, L/8 DFs are cascaded by
connecting the COUT0-7 outputs of the (i)th DF to the CIN0­7 inputs of the (i+1)th DF. The DIN0-7 inputs and SUM0-25
outputs of all the DFs are also tied together. A specific
example of two cascaded DFs illustrates the technique
(Figure 5). Timing (Figure 6) is similar to the simple 8-tap
FIR, except the
enabled independently for the two DFs in order to clear the
correct accumulators and enable the SUM0-25 output
signals at the proper times.

ERASE and SENBL/SENBH signals must be

Single DF Configuration

Using a single DF, a filter of length L>8 can be constructed
by processing in L/8 passes as illustrated in the following
table (Table 2) for a 16-tap FIR. Each pass is composed of
Tp = 7 + L cycles and computes eight output samples. In
pass i, the sample with indices i*8 to i*8 +(L1) enter the
DIN0-7 inputs. The coefficients C
inputs, followed by seven zeros. As these zeros are entered,
the result samples are output and the accumulators reset.
Initial filing of the pipeline is not shown in this sequence
table. Filter outputs can be put through a FIFO to even out
the sample rate.

-C

enter the CIN0-7

0

L-1

Extended Coefficient and Data Sample
Word Size

The sample and coefficient word size can be extended by
utilizing several DFs in parallel to get the maximum sample
rate or a single DF with resulting lower sample rates. The
technique is to compute partial products of 8 x 8 and
combine these partial products by shifting and adding to
obtain the final result. The shifting and adding can be
accomplished with external adders (at full speed) or with the
DF's shift and add mechanism contained in its output stage
(at reduced speed).

Decimation/Resampling

The HSP43881 DF provides a mechanism for decimating by
factors of 2, 3, or 4. From the DF filter cell block diagram
(Figure 1), note the three D registers and two multiplexers in
the coefficient path through the cell. These allow the
coefficients to be delayed by 1, 2, or 3 clocks through the
cell. The sequence table (Table 3) for a decimate by two filter
illustrates the technique (internal cell pipelining ignored for
simplicity).

Detailed timing for a 30MHz input sample rate, 15MHz
output sample rate (i.e., decimate by two), 16-tap FIR filter,
including pipelining, is shown in Figure 7. This filter requires
only a single HSP43881 DF.

13

DF0

CLK

RESET

ERASE

543210

22 23 242120191817161514131211109876

25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

14

DF1

ERASE

DIN0-7

DIENB

CIN0-7

CIENB

ADR0-2

DF0 SUM0-25

DF1 SUM0-25

SHADD

SENBL/H

DF0

SENBL/H

DF1

X

0X1X2X3X4X5X6X7X8X9X10X11X12X13X14X15X16X17X18X19X20X21X22X23X24X25X26X27X28X29X30X31X32X33X34X35X36X37

C15C14C13C12C11C10C9C8C7C6C5C4C3C2C1C0C15C14C13C12C11C10C9C8C7C6C5C4C3C2C1C0C15C14C13C12C11C

76

32

10

76

54

32

10

Y

Y

Y

Y

15

Y

Y

18

17

16

Y

Y

19

22

21

20

Y

Y

Y

25

24

23

54

Y

Y

Y

Y

27

26

Y

29

28

210

Y32Y

31

30

10

HSP43881

3

Y

33

DCM0-1

0

15

Y

N

CKX

∑

×

NK–

=

K0=

FIGURE 6. 16-TAP 30MHz FIR FILTER TIMING USING TWO CASCADED HSP43881s

HSP43881

TABLE 2. 16-TAP FIR FILTER SEQUENCE USING A SINGLE DF

Data

Sequence

Coefficient

Sequence

C

Input

CLK CELL 0 CELL 1 CELL 2 CELL 3 CELL 4 CELL 5 CELL 6 CELL 7 SUM/CLR

6C
7+C
8+C13x X

9+C
10 +C11 x X
11 +C10 x X
12 +C9 x X
13 +C8 x X
14 +C7 x X
15 +C6 x X
16 +C5 x X
17 +C4 x X
18 +C3 x X
19 +C2 x X
20 +C1 x X
21 +C0 x X

15

14

12

x X

x X

x X

0

1
2
3
4

5
6
7
8
9

10
11
12
13
14
15

22 0 +C2 x X
23 0 0 +C1 x X

24 0 0 0 +C0 x X
250000 C
26000
27000
28000

X30...X9, X8, X22...X1, X

Input

...C14, C

0

0...0, C0...C

15,

14, C15

0

HSP43881

...0, Y30 ...Y

23,

0...0, Y

22,

...Y

15,

0...0

000 -

C15 x X

+C0 x X

1

16

00 -

C15 x X

C0 x X

2

17

0-

C15 x X
+C14 x X
+C13 x X
+C12 x X
+C11 x X
+C10 x X

+C9 x X
+C8 x X
+C7 x X
+C6 x X
+C5 x X
+C4 x X
+C3 x X

0
0
0

10
11
12
13
14
15
16

17
18

3

C15 x X

4
5
6
7
8

9

4

C15 x X

5

C15 x X

6

C15 x X

7

C14 x X

8

C13 x X

9

C12 x X

10

C11 x X

11

C10 x X

12

C9 x X

13

C8 x X

14

C7 x X

15

C6 x X

16

C5 x X

17

C4 x X

18

C0 x X

19

0C
00 C

C0 x X

20

C0 x X

21

000C

3
2
1
0

x X
x X
x X
x X

19
20
21
22

-

-

-

-

-

-

-

-

-

-

-

­CELL 0 (Y15)
CELL 1 (Y16)

CELL 2 (Y17)
CELL 3 (Y18)
CELL 4 (Y19)
CELL 5 (Y20)
CELL 6 (Y21)
CELL 7 (Y22)

15

HSP43881

TABLE 2. 16-TAP FIR FILTER SEQUENCE USING A SINGLE DF (Continued)

Data

Sequence

Coefficient

Sequence

C

Input

CLK CELL 0 CELL 1 CELL 2 CELL 3 CELL 4 CELL 5 CELL 6 CELL 7 SUM/CLR

29 C15 x X
30 +C14 x X
31 +C13 x X
32 +C12 x X
33 +C11 x X
34 +C10 x X
35 +C9 x X
36 +C8 x X
37 +C7 x X
38 +C6 x X
39 +C5 x X
40 +C4 x X
41 +C3 x X
42 +C2 x X
43 +C1 x X
44 +C0 x X

80 0 0

9
10
11
12
13

14
15
16
17
18
19
20
21
22
23

45 0 C6 x X
46 0 0 C5 x X

47000 C
48000 C

X30...X9, X8, X22...X1, X

Input

...C14, C

0

C15 x X

0...0, C0...C

15,

9

+C15 x X

C0 x X

24

0

C0 x X

10

25

0

14, C15

HSP43881

...0, Y30 ...Y

23,

0...0, Y

22,

...Y

15,

0...0

0000 -

0

0000 -

00000 -

0000 -

C0 x X

26

C15 x X

x X

0

12

27

000 -

C15 x X

13

00 -

C15 x X

14

0-

C15 x X

15

C14 x X

16

C13 x X

17

C12 x X

18

C11 x X

19

C10 x X

20

C9 x X

21

C8 x X

22

C7 x X

x X

4

C3 x X

23
24

25
26

27

CELL 0 (Y23)
CELL 1 (Y24)

CELL 2 (Y25)
CELL 3 (Y26)

CELL 4 (Y27)

-

-

-

-

-

-

-

-

16

HSP43881

TABLE 3. 16-TAP DECIMATE BY TWO FIR FILTER SEQUENCE; 30MHz IN, 15MHz OUT

Data

Sequence

Coefficient

Sequence

Input

...C

, C0, ...C

15

CLK CELL 0 CELL 1 CELL 2 CELL 3 CELL 4 CELL 5 CELL 6 CELL 7 SUM/CLR

6C15 x X
7+C14 x X
8+C13 x X

9+C12 x X
10 +C11 x X
11 +C10 x X
12 +C9 x X
13 +C8 x X
14 +C7 x X
15 +C6 x X
16 +C5 x X
17 +C4 x X
18 +C3 x X
19 +C2 x X
20 +C1 x X
21 +C0 x X
22 C15 x X
23 +C14 x X
24 +C13 x X
25 +C12 x X
26 +C11 x X
27 +C10 x X
28 +C9 x X
29 +C8 x X
30 +C7 x X
31 +C6 x X
32 +C5 x X
33 +C4 x X
34 +C3 x X
35 +C2 x X
36 +C1 x X
37 +C0 x X

0

1
2
3
4

5
6
7
8
9

10
11
12
13
14
15

16

17
18
19
20
21

22
23
24
25
26
27
28
29
30
31

0000000­0000000-

C15 x X

2

000000 ­000000 -

C15 x X

+C14 x X

31

+C14 x X

Input

4

31

...X2, X1, X

13, C14

, C

15

0

HSP43881

...Y19, -, ...Y

17,

-, Y

15

00000 ­00000 -

C15 x X

6

0000 ­0000 -

C15 x X

8

000 ­000 -

C15 x X

10

00 ­00 -

C15 x X

12

0­0-

C15 x X

14

+C14 x X

31

+C14 x X

31

+C14 x X

31

+C14 x X

31

+C14 x X
+C13 x X
+C12 x X
+C11 x X
+C10 x X

+C9 x X
+C8 x X
+C7 x X
+C6 x X
+C5 x X
+C4 x X
+C3 x X
+C2 x X
+C1 x X
+C0 x X
C15 x X

+C14 x X

15
16
17
18

19
20
21
22
23
24
25
26
27
28
29
30

31

CELL 0 (Y15)

CELL 1 (Y17)

CELL 2 (Y19)

CELL 3 (Y21)

CELL 4 (Y23)

CELL 5 (Y25)

CELL 6 (Y27)

CELL 7 (Y29)

CELL 8 (Y31)

-

-

-

-

-

-

-

-

-

17

CLK

RESET

ERASE

543210

22 23 242120191817161514131211109876

25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

18

DIN0-7

DIENB

CIN0-7

CIENB

ADR0-2

SUM0-25

SHADD

SENBL

SENBH

DCM0-1

X

0X1X2X3X4X5X6X7X8X9X10X11X12X13X14X15X16X17X18X19X20X21X22X23X24X25X26X27X28X29X30X31X32X33X34X35X36X37

C15C14C13C12C11C10C9C8C7C6C5C4C3C2C1C0C15C14C13C12C11C10C9C8C7C6C5C4C3C2C1C0C15C14C13C12C11C

10

23456701

Y

Y

Y

Y

Y

Y

Y

Y

15

1

19

17

23

21

27

25

FIGURE 7. 16-TAP DECIMATE-BY-TWO FIR FILTER TIMING; 30MHz, 15MHz OUT

10

Y

Y

33

31

29

HSP43881

HSP43881

Absolute Maximum Ratings Thermal Information

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.0V

Input, Output Voltage. . . . . . . . . . . . . . . . . . . GND -0.5 to VCC 0.5V

ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Class 1

Operating Conditions

Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V ±5%

Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 70oC

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationofthe
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

1. θJA is measured with the component mounted on an evaluation PC board in free air.

DC Electrical Specifications

PARAMETER SYMBOL NOTES TEST CONDITIONS MIN MAX UNITS

Power Supply Current I

Standby Power Supply Current I
Input Leakage Current I
Output Leakage Current I
Logical One Input Voltage V
Logical Zero Input Voltage V
Logical One Output Voltage V
Logical Zero Output Voltage V
Clock Input High V
Clock Input Low V
Input Capacitance PLCC

PGA

Output CapacitancePLCC

PGA

NOTES:

2. Operating supply current is proportional to frequency. Typical rating is 7mA/MHz.

3. Controlled via design or process parameters and not directly tested. Characterized upon initial design and after major process and/or design
changes.

4. Output load per test load circuit and CL = 40pF.

CCOP

CCSB

O
IH

OH

OL
IHC
ILC

C

IN

C

OUT

I

IL

Notes 2, 4 VCC = Max

Note 4 VCC = Max - 500 µA

Note 3 CLK Frequency 1MHz

Thermal Resistance (Typical, Note 1) θJA (oC/W) θJC (oC/W)

PLCC Package . . . . . . . . . . . . . . . . . . 34 N/A

PGA Package . . . . . . . . . . . . . . . . . . . 36 7

Maximum Junction Temperature

PLCC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150oC

PGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175oC

Maximum Storage Temperature Range. . . . . . . . . . .-65oC to 150oC

Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC

(PLCC - Lead Tips Only)

Die Characteristics

Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17,763 Gates

- 140 mA

CLK Frequency 20MHz

VCC = Max, Input = 0V or V
VCC = Max, Input = 0V or V
VCC = Max 2.0 - V
VCC = Min - 0.8 V
IOH = 400µA, VCC = Min 2.6 - V
IOL = 2mA, VCC = Min - 0.4 V
VCC = Max 3.0 - V
VCC = Min - 0.8 V

All measurements referenced to
GND
TA = 25oC

CC
CC

-10 10 µA

-10 10 µA

-1015pF

-1015pF

pF

pF

19

HSP43881

AC Electrical Specifications V

PARAMETER

TEST CONDITIONS SYMBOL NOTES

Clock Period t
Clock Low t
Clock High t
Input Setup t
Input Hold t
CLK to Coefficient Output Delay t
Output Enable Delay t
Output Disable Delay t
CLK to SUM Output Delay t
Output Rise t
Output Fall t

= 5V ±5%, TA = 0oC to + 70oC

CC

CP
CL
CH

IS

IH
ODC
OED
ODD
ODS

OR

OF

Note 5 - 20 - 15 - 15 ns

Note 5 - 6 -6-6 ns
Note 5 - 6 -6-6 ns

-20 (20MHz) -25 (25.6MHz) -30 (30MHz)

MIN MAX MIN MAX MIN MAX UNITS

50 -39-33- ns
20 -16-13- ns
20 -16-13- ns
16 -14-13- ns

0 -0-0- ns

- 24-20-18 ns

- 20-15-15 ns

- 27-25-21 ns

NOTE:

5. Controlled by design or process parameters and not directly tested. Characterized upon initial design and after major process and/or design
changes.

Test Load Circuit

NOTES:

6. Includes stray and jig capacitance.

7. Switch S1 Open for I

CCSB

and I

(NOTE 6) C

Tests.

CCOP

DUT

S

1

L

I

OH

EQUIVALENT CIRCUIT

1.5V I

±

OL

20

Waveforms

HSP43881

2.0V

t

IS

t

IH

CLK

t

CP

t

CH

2.0V

t

CL

2.0V2.0V

CLK

3.0V

INPUT†

0.0V

† Input includes: DIN0-7, CIN0-7, DIENB, CIENB, ERASE,

RESET,DCM0-1, ADRO-2, TCS, TCCI, SHADD

CLK

SUM0-25

COUT0-7

TCCO

FIGURE 8. CLOCK AC PARAMETERS

2.0V

t

ODC,tODS

1.5V

FIGURE 9. INPUT SETUP AND HOLD

2.0V

0.8V

t

OR

t

OF

† SUM-25, COUTO-7, TCCO are assumed not to be in high-

impedance state.

FIGURE 10. SUM0-25, COUT0-7, TCCO OUTPUT DELAYS FIGURE 11. OUTPUT RISE AND FALL TIMES

SENBL

SENBH

COENB

SUM0-25

COUT0-7

TCCO

1.5V

HIGH

IMPEDANCE

t

OED

1.7V

1.3V

t

ODD

1.5V

IMPEDANCE

HIGH

INPUT

3.0V

0.0V

1.5V

NOTE: AC Testing: Inputs are driven at 3.0V for Logic and “1” and

0.0V for Logic “0”. Input and output timing measurements are made
at 1.5 for both a Logic “1” and “0”. CLK is driven at 4.0 and 0V and

DEVICE
UNDER

TEST

measured at 2.0V.

FIGURE 12. OUTPUT ENABLE, DISABLE TIMING

FIGURE 13. AC TESTING INPUT, OUTPUT WAVEFORM

1.5V1.5V

1.5V

4.0V

0.0V

OUTPUT

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Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with­out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
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