Datasheet HSP43168 Datasheet (Intersil Corporation)

HSP43168

Data Sheet November 1999

Dual FIR Filter

The HSP43168 Dual FIR Filter consists of two independent
8-tap FIR filters. Each filter supports decimation from 1 to 16
and provides on-board storage for 32 sets of coefficients.
The Block Diagram shows two FIR cells each fed by a
separate coefficient bank and one of two separate inputs.
The outputs of the FIR cells are either summed or
multiplexed by the MUX/Adder. The compute power in the
FIR Cells can be configured to provide quadrature filtering,
complex filtering, 2-D convolution, 1-D/2-D correlations, and
interpolating/decimating filters.

The FIR cells take advantage of symmetry in FIR
coefficients by pre-adding data samples prior to
multiplication. This allows an 8-tap FIR to be implemented
using only 4 multipliers per filter cell. These cells can be
configured as either a single 16-tap FIR filter or dual 8-tap
FIR filters. Asymmetric filtering is also supported.

Decimation ofupto 16 is providedto boost theeffective number
of filter taps from 2 to 16 times. Further, the Decimation
Registers provide the delay necessary for fractional data
conversion and 2-D filtering with kernels to 16 x16.

The flexibility of the Dual is further enhanced by 32 sets of
user programmable coefficients. Coefficient selection may
be changed asynchronously from clock to clock. The ability
to toggle between coefficient sets further simplifies
applications such as polyphase or adaptive filtering.

The HSP43168 is a low power fully static design
implemented in an advanced CMOS process. The
configuration of the device is controlled through a standard
microprocessor interface.

File Number 2808.8

Features

• Two Independent 8-Tap FIR Filters Configurable as a
Single 16-Tap FIR

• 10-Bit Data and Coefficients

• On-Board Storage for 32 Programmable Coefficient Sets

• Up To: 256 FIR Taps, 16 x 16 2-D Kernels, or 10 x 19-Bit
Data and Coefficients

• Programmable Decimation to 16

• Programmable Rounding on Output

• Standard Microprocessor Interface

Applications

• Quadrature, Complex Filtering

• Image Processing

• Polyphase Filtering

• Adaptive Filtering

Ordering Information

TEMP.

PART NUMBER

HSP43168VC-33 0 to 70 100 Ld MQFP Q100.14x20
HSP43168VC-40 0 to 70 100 Ld MQFP Q100.14x20
HSP43168VC-45 0 to 70 100 Ld MQFP Q100.14x20
HSP43168JC-33 0 to 70 84 Ld PLCC N84.1.15
HSP43168JC-40 0 to 70 84 Ld PLCC N84.1.15
HSP43168JC-45 0 to 70 84 Ld PLCC N84.1.15
HSP43168JI-40 -40 to 85 84 Ld PLCC N84.1.15
HSP43168GC-45 0 to 70 84 Ld CPGA G84.A

RANGE (oC) PACKAGE PKG. NO.

Block Diagram

INA0 - 9

INB0 - 9/
OUT0 - 8

OEL

OEH

10

10

CIN0 - 9

A0 - 8

WR

CSEL0 - 4

1

MUX

10

9

COEFFICIENT

BANK A

FIR CELL A

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

MUX

MUX/

ADDER

919

1-888-INTERSIL or 407-727-9207

COEFFICIENT

BANK B

FIR CELL B

CONTROL/

CONFIGURATION

OUT9 - 27

| Copyright © Intersil Corporation 1999

Pinouts

84 LEAD CPGA

11 10 9 8 7 6 5 4 3 2 1

GND

A

B

C

D

E

F

G

WR

RVRS

SHFTEN

MUX0 MUX1

FWRD

TXFR

V

ACCEN

CC

GND CLK

OEH

OUT27 OUT22 OUT26

OUT24 OUT23 OUT25

BOTTOM VIEW

A4A1

A0

A5

HSP43168

BOTTOM VIEW

A7 CSEL1 CSEL3 CSEL4

A8

V

CC

CSEL0

CSEL2 CIN9

CIN2 CIN1

INA8 INA9

INA7 INA5

A2A3

A6

CIN8

CIN5

CIN7

CIN6 CIN4

GND

CIN3

CIN0

V

INA6

HSP43168

PIN
'A1'
ID

L

A

B

C

D

E

CC

F

G

GND OUT15 OUT14 OUT12

K

OUT18

J

OUT19

H

OUT21

G

OUT24 OUT23 OUT25

F

OUT27 OUT22 OUT26

OEH

E

84 LEAD CPGA

11 10 9 8 7 6 5 4 3 2 1

V

OUT16

CC

OUT17

OUT20

TOP VIEW

OUT10 OUT11

V

INB0

CC

OUT9

OEL

HSP43168

INB5

INB7

INA7

INA8

INB6

INB8

INA0

INA3

INA5

INA9

INB4

INB1

GND

INB2OUT13

INB3 INA2

TOP VIEW

CIN2

GND

CLK

CIN1

INB9

INA1

INA4

INA6

V

CIN0

L

K

J

H

G

F

CC

E

OUT21 OUT20

H

J

OUT19 OUT17

V

OUT18

K

L

CC

GND OUT15 OUT14 OUT12 OUT10 OUT11 INB1 INB4 INB5 INB6

11 10 9 8 7 6 5 4 3 2 1

OUT9

V

INB3 INA2

OEL

CC

CSEL 3

CSEL 4

CIN 9

CIN 8

109 8 7 6 5 4 3 2 1 848382818079

11

CIN 7

12

CIN 6

13

CIN 5

14

CIN 4

15

GND

16

CIN 3

17

CIN 2

18

CIN 1

19

CIN 0

20

INA 9

21

INA 8

22

INA 7

23

INA 6

24

INA 5

25

V

26

CC

27

INA 4

28

INA 3

29

INA 2

30

INA 1

31

INA 0

32

INB 9

33 34 35 36 37 38 39 40 41

INA3 INA4

INA0

INB8

CSEL 1

CSEL 0

CSEL 2

H

D

C

J

INA1INB7GNDINB2OUT13 INB0OUT16

INB9

B

K

A

L

84 LEAD PLCC

TOP VIEW

CC

A 6

A 7

A 5

A 8

V

42 43 44 45 46 47 48 49

CIN9

CSEL3

GND

CIN6

CIN7

CSEL4

V

ACCEN

CC

A5

TXFR

FWRD

SHFTEN

MUX0 MUX1

RVRS WR

11 10 9 8 7 6 5 4 3 2 1

A 4

A 3

A 2

A 1

A 0

GND

GND

WR

A0

A1

MUX 1

MUX 0

A6

A2A3

A7 CSEL1

A4

CSEL0

V

CC

A8

CSEL2

767778 75

74

RVRS

73

FWD

72

SHFTEN

71

TXFR

70

ACCEN
V

69

CC

68

CLK

67

GND

66

OEH

65

OUT 27

64

OUT 26

63

OUT 25

62

OUT 24

61

OUT 23

60

OUT 22

59

OUT 21
OUT 20

58

OUT 19

57

OUT 18

56

OUT 17

55

V

54

CC

50 51 52 53

CIN3

CIN4

CIN5

CIN8

D

C

B

A
PIN

'A1'
ID

INB 8

INB 7

INB 6

INB 5

GND

INB 4

INB 3

INB 2

INB 1

INB 0

OEL

OUT 9

OUT 10

OUT 12

OUT 11

OUT 13

OUT 14

OUT 15

GND

OUT 16

CC

V

2

Pinouts (Continued)

HSP43168

100 LEAD MQFP

TOP VIEW

CIN8

NC

CIN7

NC
CIN6
CIN5
CIN4
GND
GND
CIN3
CIN2
CIN1
CIN0
INA9
INA8
INA7
INA6
INA5

V

CC

V

CC

INA4
INA3
INA2
INA1
INA0

NC

NC
INB9
INB8
INB7

CCVCC

CIN9

CSEL4

99 98 97 96 95 94 93 91 89 87 85 84 83 818286889092100

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

CSEL2

CSEL3

CSEL1

CSEL0

V

A8

A7

A6

A5

A4

A3

A2

A1

A0

GND

GND

80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

WR

MUX1
MUX0
RVRS
NC
FWRD
SHIFTEN
TXFR
ACCEN
V

CC

V

CC

CLK
GND
GND
OEH
OUT27
OUT26
OUT25
OUT24
OUT23
OUT22
OUT21
OUT20
OUT19
OUT18
OUT17
NC
V

CC

V

CC

GND
GND

32 33 34 35 36 37 38 40 42 44 46 47 48 50494543413931

INB6

INB5

GND

GND

INB4

INB3

INB2

INB1

INB0

OEL

OUT9

OUT10

VCCV

CC

OUT11

OUT12

OUT13

OUT14

OUT15

OUT16

3

HSP43168

Pin Description

SYMBOL TYPE DESCRIPTION

V

CC

GND Ground.

CIN0-9 I Control/Coefficient Data Bus. Processor interface for loading control data and coefficients. CIN0 is the LSB.

A0-8 I Control/Coefficient Address Bus. Processor interface for addressing Control and Coefficient Registers. A0 is the

WR I Control/Coefficient Write Clock. Data is latched into the Control and Coefficient Registers on the rising edge of

CSEL0-4 I Coefficient Select. Thisinput determines which of the 32 coefficient sets areto be used by FIR A and B. Thisinput

INA0-9 I Input to FIR A. INA0 is the LSB.
INB0-9 I/O Bidirectional Input for FIR B. INB0 is the LSB and is input only. When used as output, INB1-9 are the LSBs of the

OUT9-27 O 19MSBs of Output Bus. Data format is either unsigned or two's complement depending on configuration. OUT27

SHFTEN I ShiftEnable.This active lowinput enables clockingof data intothe part andshifting of datathrough the Decimation

FWRD I Forward ALU Input Enable. When active low, data from the forward decimation path is input to the ALUs through

RVRS I Reverse ALU Input Enable. When active low, data from the reverse decimation path is input to the ALUs through

VCC: +5V power supply pin.

LSB.

WR.

is registered and CSEL0 is the LSB.

output bus, and INB9 is the MSB of these bits.

is the MSB.

Registers.

the “a” input. When high, the “a” inputs to the ALUs are zeroed.

the “b” input. When high, the “b” inputs to the ALUs are zeroed.

TXFR I Data Transfer Control. This active low input switches the LIFO being read into the reverse decimation path with

the LIFO being written from the forward decimation path (see Figure 1).

MUX0-1 I Adder/Mux Control. This input controls data flow through the output Adder/Mux. Table 5 lists the various

configurations.

CLK I Clock. All inputs except those associated with the processor interface (CIN0-9, A0-8, WR) and the output enables

(OEL, OEH) are registered by the rising edge of CLK.

OEL I Output Enable Low. This three-state control enables the LSBs of the output bus to INB1-9 when OEL is low.

OEH I Output Enable High. This three-state control enables OUT9-27 when OEH is low.

ACCEN I Accumulate Enable. This active high input allows accumulation in the FIR Cell Accumulator. A low on this input

latches the FIR Accumulator contents into the Output Holding Registers while zeroing the feedback pass in the
Accumulator.

4

TXFR

FIR A REVERSE PATH

FIR A FORWARD PATH

SHFTEN

5

INB1-9/
OUT0-8

INA0-9

INB0

FWRD

RVRS

†FIR B INPUT

SOURCE

10

9

DELAY 3

DELAY 3

M

DELAY 3

U
X

DELAY 3

DELAY 3

10

10

AB

ALU

11

REG

DELAY

1-16 ††

DELAY
1-16

††

AB

REG

1

DELAY 4

0

DELAY 3

DECIMATION REGISTERS

DELAY

1-16 ††

DELAY

1-16

††

ALU

†DATA REVERSAL ENABLE

M
U
X

†FIR A ODD/EVEN # TAPS

DELAY
1-16 ††

DELAY
1-16

††

AB

ALU

REG

AB

ALU

REG

DATA FEEDBACK

CIRCUITRY

LIFO A

M

LIFO B

U
X

DELAY
1-16 ††

DELAY
1-16 ††

†ODD/EVEN

SYMMETRY

†MODE SELECT

†ODD/EVEN SYMMETRY
†MODE SELECT

D

M

E

U

M

U

X

X

M
U
X

AB

ALU

REG

DECIMATION REGISTERS

DELAY

1-16

††

DELAY

††

1-16

AB

ALU

REG

DELAY 4

DELAY 3

DELAY
1-16

DELAY
1-16

1

0

††

††

M
U
X

AB

ALU

REG

†FIR B

ODD/EVEN # TAPS

DELAY

1-16

††

DELAY

††

1-16

AB

ALU

REG

DATA FEEDBACK

CIRCUITRY

LIFO A

M

LIFO B

U
X

DELAY

1-16

†DATA REVERSAL ENABLE

FIR B REVERSE PATH
FIR B FORWARD PATH

†ODD/EVEN

SYMMETRY

D
E
M
U
X

†ODD/EVEN

NUMBER OF
TAPS

M
U
X

HSP43168

11

CSEL0-4

REG

COEF

X

BANK

COEF

X

BANK

5

DELAY 4

10

21

REG

REG

COEF

X

BANK

REG

COEF

X

BANK

REG

COEF

X

BANK

3210

REG

COEF

X

BANK

REG

COEF

X

BANK

210

REG

COEF

X

BANK

3

CLK

ACCEN

MUX0-1

CIN0-9

A0-8

WR

OEL

OEH

FIR A

ACCUMULATOR

0

M

R

U
X

DELAY 5

2

DELAY 6

10

9

CONTROL

ADDER

E
G

22

OUTPUT
HOLDING

REG

REGISTER

†MODE SELECT
†ODD EVEN SYMMETRY
†FIR A ODD/EVEN # TAPS
†FIR B ODD/EVEN # TAPS
†FIR B INPUT SOURCE
†DATA REVERSAL ENABLE
†ROUND ENABLE
†DECIMATION FACT OR

FIR CELL A FIR CELL B

MUX/

ADDER

28

DELAY 2

9

†ROUND ENABLE

19

FIR B

ACCUMULATOR

0

M

R

U
X

ADDER

E
G

OUTPUT
HOLDING

REG

REGISTER

OUT9-27

†Processor control words

††Decimation factor

FIGURE 1. DUAL FIR FILTER

HSP43168

Functional Description

As shown in Figure 1, the HSP43168 consists of two
4-multiplier FIR filter cells which process 10-bit data and
coefficients. The FIR cells can operate as two independent
8-tap FIR filters or two 4-tap asymmetric filters at maximum
I/O rates. A single filter mode is provided which allows the
FIR cells to operate as one 16-tap FIR filter or one 8-tap
asymmetric filter. On board coefficient storage for up to 32
sets of 8 coefficients is provided. The coefficient sets are
user selectable and are programmed through a
microprocessor interface.Programmable decimation to 16 is
also provided. By utilizing Decimation Registers together
with the coefficient sets, polyphase filters are realizable
which allow the user to trade data rate for filter taps. The
MUX/Adder can be configured to either add or multiplex the
outputs of the filter cells depending upon whether the cells
are operating in single or dual filter mode. In addition, a
shifter in the MUX/Adder is provided for implementation of
filters with 10-bit data and 20-bit coefficients or vice versa.

The Dual FIR Filter has a “pipeline” delay of 8 CLK periods,
once normal filtering operations begin. Five typical filtering
operation examples are provided in the Applications
Examples Section as a guide to configuration and control of
the Dual FIR Filter.

During normal filter operations, the location and duration of
the

TXFR signal assertions are determined by the filter
configuration and operation mode. Once set, these signal
parameters must be maintained during normal operation to
ensure proper data alignment in the part. Once the part is
reset, donot change
again.

NOTE: The fixed or periodic relationship between the
TXFR signal and CLK must be maintained for valid filter
operation. This relationship can only change when CLK
is halted and new configuration control words are
loaded into the device.

TXFR unlessyou load the configuration

Preparing the Dual FIR for Operation

Two configuration steps are requiredto prepare the Dual FIR
Filter for normal operation: 1) loading the Configuration
Control Registers, and 2) loading the FIR Filter Coefficients.

Configuration Control Registers are loaded by placing the
control register address on address lines A0-8, placing the
configuration data on the configuration input lines CIN0-9,
and asserting the
assertion). This action creates a rising edge on the
which clocks the address and configuration data into the part.
The details of the “Load Configuration” process areoutlined in
the Microprocessor Interface Section.

FIR Coefficients are loaded by placing the address of the
Coefficient Data Bank on the address lines A0-8, placing
the FIR 10-bit coefficient values on the configuration input
lines CIN0-9 and then asserting the
release of the assertion). This action creates a rising edge
on the

WR line, which clocks the FIR Coefficient Band
address and FIR Coefficient data into the part. The details
of the “Load FIR Coefficient” process are outlined in the
FIR Filter Cells Section, Coefficient Bank Subsection.

Both the Configuration Load and FIR Coefficient Load can
be done as a sequence of asynchronous write commands
to the Dual FIR Filter. Once these actions are complete, the
part is ready for normal filter operation. The CLK,
FWRD, RVRS, ACCEN, and SHFTEN signals must be
asserted in a manner determined by the application.
MUX0-1 must meet the setup and hold times with respect
to clock for proper filter operation. Details of the MUX1-0
control can be found in the Output MUX/Adder Section.
Details of the ACCEN control can be found in the Fir Cell
Accumulator Section. Bit locations for the various filter
control/configuration signals can be found in the
Input/Output Formats Section.

WR line (followed by a release of the

WR line,

WR line (followed by a

TXFR,

Microprocessor Interface

The Dual FIRhas a 20 pin write only microprocessor interface
for loading data into the Control Block and Coefficient Banks.
The interface consists of a 10-bit data bus (CIN0-9), a 9-bit
address bus (A0-8), and a write input (
into the on-boardregisters on a rising edge. The configuration
control and coefficient data loading is asynchronous to CLK.

WR) to latch the data

Control Block

The Dual FIR is configured by writing to the registers within
the Control Block. Figure 2 shows the timing diagram for
writing to the ConfigurationControl Registers. These Control
Registers are memory mapped to Address 000H (H =
Hexadecimal) and 001H on A0-8. The Filter Coefficient
Registers are mapped to 1XXH (X = value described in the
“Coefficient Banks” chapter of the ALU Section).

RESET

WR

A8-0

C9-0

FIGURE 2. LATCHING C9-0 VALUESINTOADDRESS A8-0

The format of the Control Registers is shown in Table 1 and
Table 2. Writing toany of the Control/Configuration Registers
causes a reset which lasts for 6 CLK cycles following the
assertion of
the Control Block will not clear the contentsof the Coefficient

000H

001H

REGISTERS

WR. The reset caused by Writing Registers in

6

HSP43168

Bank. As shown in Figure 2, either Configuration Control
Register can be written to during reset.

T ABLE1. CONFIGURATION/CONTROLWORD 0 BIT DEFINITIONS

CONTROL ADDRESS 000H

BITS FUNCTION DESCRIPTION

3-0 Decimation Factor (N) R = N + 1

0000 = No Decimation.
1111 = Decimation by 16.

4 Mode Select 0 = Single Filter Mode.

1 = Dual Filter Mode.
(also 20-Bit Coefficient Filter)

5 Odd/Even Filter

Coefficient Symmetry

6 FIR A Odd/Even

Number of Taps

7 FIR B Odd/Even

Number of Taps

8 FIR B Input Source 0 = Input from INA0-9.

9 Not Used Set to 0 for Proper Operation.

NOTE: Address locations002H to 011H are reserved, and writing to
these locations will have unpredictable effects on part configuration.

T ABLE2. CONFIGURATION/CONTROLWORD 1 BIT DEFINITIONS

CONTROL ADDRESS 001H

BITS FUNCTION DESCRIPTION

0 FIR A Input Format 0 = Unsigned.

1 FIR A Coefficient Format (Defined same as FIR A input).
2 FIR B Input Format (Defined same as FIR A input).
3 FIR B Coefficient (Defined same as FIRA input).
4 Data Reversal Enable 0 = Enabled.

8-5 Round Position 0000 = 2

9 Round Enable 0 = Enabled.

NOTE: Address locations 002H to 011H are reserved, and
writing to these locations will have unpredictableeffects on part
configuration.

0 = Even Symmetric Coefficients.
1 = Odd Symmetric Coefficients.

0 = Odd Number of Taps in Filter.
1 = Even Number of Taps in Filter.

(Defined Same as FIR A Above).

1 = Input from INB0-9.

1 = Two's Complement.

1 = Disabled.

-10.

1011 = 2
(See Figure 4)

1 = Disabled.

1.

The 4 LSBs of the control word loaded at address 000H are
used to select the decimation factor. The Decimation Factor
is programmed to one less than the number of delays
between filter taps

DF CLK delays between taps()1–=

(EQ. 1)

and B before entering the reverse paths of Filters A and B
(see Figure 1). Coefficient symmetry is selected by bit 5. Bits
6 and 7 are programmed to configure the FIR cells for odd or
even filter lengths (number of taps). Bit 8 selects the FIR B
input source when the FIR cells are configured for
independent operation. Bit 9 must be programmed to 0.

NOTE: When the filter is programmed for even-taps, the
TXFR signal is delayed by only three CLKS (see Figure 1).
For odd-taps, the

TXFR signal is delayed by four CLKS.

The 4 LSBs of the control word loaded at address 001H are
used to configure the format of the FIR cell's data and
coefficients. Bit 4 is programmed to enable or disable the
reversal of data sample order prior to entering the Reverse
Path Decimation Registers. Data reversal is required for
symmetric filter coefficient sets of both even or odd numbers
of filter taps. Asymmetric filters and some decimated
symmetric filters require the data reversal to be off. Bits 5-9
are used to support programmable rounding on the output.

FIR Filter Cells

Each FIRfilter cell is based on an array of four11x10-bit two's
complement multipliers. One input of the multipliers comes
from the ALU’s which combine data shifting through the
Forward and Re verse Decimation Registers. The second
multiplier inputcomes from the user programmablecoefficient
bank. The multiplier outputs are fed to an accumulator whose
result is passedto the output section where it ismultiplexed or
added with the result from the other FIR cell.

Decimation Registers

The Forwardand ReverseDecimation Shift Registerscan be
configured for decimation factors from 1 to 16 (see Table 1,
bits 0-3). NOTE: Setting the decimation factor only

affects the Delay Registers between filter taps, not the
filter controlmultiplexers. Example 4 and Example 5 inthe

Applications Section discuss how to configure the part for
actual decimation applications.

The Reverse Shifting Registers with the data reversal logic
are used to takeadvantage of symmetry in linear phase filters
by aligning data at the ALUs for pre-addition prior to
multiplication by the common coefficient. When the FIR cells
are configured in single filter mode, the Decimation Registers
in FIR cell A and FIR cell B are cascaded. This extended filter
tap delay path allows computation of a filter which is twice the
size of that capable using a single cell. The Decimation
Registers also provide data storage for polyphase or 2-D
filtering applications (See Applications Examples Section).

For example , if the 4 LSBs are prog r ammed with a value of
0010, theForward andReverse ShiftingDecimation Registers
are each configured with a delay of 3. Bit 4 is used to select
whether the FIR cells operate as two independent filters or
one extended length filter . Dual filter mode assumes Filter A
and FilterB are separate independentfilters. In thesingle filter
mode, thedata is routed through the forw ardpaths of Filters A

7

The Data FeedbackCircuitry in each FIR cell is responsible
for transferring data from the Forward to the Reverse
Shifting Decimation Registers.This circuitry feeds blocks of
samples into the reverse shifting decimation path in either
reversed or non-reversed sample order. The MUX/DEMUX
structure at the input to the Feedback Circuitry routes data
to the LIFOs or the delay stage depending on the selected

HSP43168

configuration. The MUX on the Feedback Circuitry Output
selects which storage element feeds the Reverse Shifting
Decimation Registers.

In applications requiring reversal of sample order, the FIR
cells are configured with data reversal enabled (see Table
2, CW5, bit 4 = 0). In this mode, data is transferred from the
forward to the backward Shifting Registers through a
pingponged LIFO structure. While one LIFO is being read
into the backward shifting path, the other LIFO is written
with data samples. The MUX/DEMUX controls which LIFO
is being written, and the MUX on the Feedback Circuitry
output controls which LIFO is being read. A low on
and

SHIFTEN, switches the LIFOs being read and written,

TXFR

which causes the block of data to be read from the
structure in reversedin sample order (See Example4 in the
Application Examples Section).

The frequency with which

TXFR is asserted determinessize
of the data blocks in which sample order is reversed. For
example, if

TXFR is asserted once every three CLKs, blocks
of 3 data samples with order reversed, would be fed into the
Backward Decimation Registers. NOTE: Altering the

frequency or phase of

TXFR assertion once a filtering

operation has begun will invalidate the filtering result.

In applications which do not require sample order reversal,
the FIR cells must be configured with data reversal
disabled (see Table 2, CW5, bit 4 = 1). In addition, TXFR
must be asserted to ensure proper data flow. In this
configuration, data to the backward shifting decimation
path is routed though a delaystage instead of the pingpong
LIFOs. The number of registers in the delay stage is based
on the programmed decimation factor. NOTE: Data

reversal must be disabled and TXFR must be asserted
for filtering applications which do not use decimation.

The shifting of data through the Forward and Reverse
Decimation Registers is enabled by asserting the
input. When

SHFTEN is high, data shifting is disabled, and

SHFTEN

the data sample latched into the parton the previous clockis
the last input to the filter structure. The data sample at the
filter input when

SHFTEN is asserted, will be the next data

sample into the forward decimation path.
When operating the FIR cells as two independent filters, FIR

A receives input data via INA0-9 and FIR B receives data
from either INA0-9 or INB0-9 depending on the application
(see Table 1).

When the FIR cells are configured as a single extended
length filter, the forward and reverse decimation paths of the
two FIR cells are cascaded. In this mode,data is transferred
from the forward decimation path to the reverse decimation
path by the Data Feedback Circuitry in FIR B. Thus, the
manner in which data is read into the reverse decimation
path is determined by FIR B's configuration. When the
decimation paths are cascaded, data is routed through the
fourth delay stage in FIR A's forward path to FIR B.

The configuration of the FIR cells as even or odd length filters
determines the point in the forward decimation path from
which data is multiplexed to the Data Feedback Circuitry. For
example, if the FIR cell is configured as an odd length filter,
data prior to the last register in the third forward decimation
stage is routed to the Feedback Circuitry. If the FIR cell is
configured as an even length filter, data output from the third
forward decimation stage is multiplexed to the Feedback
Circuitry.This isrequired to ensure properdata alignment with
symmetric filter coefficients (See Application Examples).

ALUs

Data shifting through the forward and reverse decimation
paths feed the “a” and “b” inputs of the ALUs respectively.
The ALUs perform an “b+a” operation if the FIR cell is
configured for even symmetric coefficients or an “b-a”
operation if configured for odd symmetric coefficients.
Control Word 0, Bit 5 is used to set the ALU operation.

Forapplications in which a pre-add or subtract is not required,
the “a” or “b” input can be zeroed by disabling
RVRS respectively. This has the effect of producing an ALU
output which is either “a”, “-a”, or “b” depending on the filter
symmetry chosen. For example, if the FIR cell is configured
for an even symmetric filter with

FWRD low andRVRS high,
the data shifting through the Forward Decimation Registers
would appear on the ALU output.

Table 3 details the ALU configurations, where “a” is the ALU
data inputfrom the front decimation delayregisters and “b” is
the ALU data from the back decimation delay registers.

TABLE 3. ALU CONFIGURATIONS

ALU

OUT SYMMETRY FWD RVS DESCRIPTION

a+b 0 (Even) 0 0 EvenNumber ofTaps, Even

Symmetry (Example 1)
+b 0 (Even) 0 1 Even Symmetry
+a 0 (Even) 1 0 Even Symmetry

- 0 (Even) 1 1 Even Symmetry

b-a 1 (Odd) 0 0 Even Number of Taps, Odd

Symmetry (Example 2)
+b 1 (Odd) 0 1 Odd Symmetry

-a 1 (Odd) 1 0 Odd Symmetry

- 1 (Odd) 1 1 Odd Symmetry

Coefficient Bank

The output of the ALU is multiplied by a coefficient from one
of 32 user programmable coefficient sets. Each set consists
of 8 coefficients (4 coefficients for FIR A and 4 for FIR B).
CSEL0-4 is used to select a coefficient set to be used.
Coefficient sets may be switched every clock to support
polyphase filtering operations.

The coefficients are loaded into On-Board Registers using
the microprocessor interface, CIN0-9, A0-8, and
multiplier within the FIR Cells is driven by a coefficient bank

FWRD or

WR. Each

8

HSP43168

with one of32 coefficients. These coefficients are addressed
as shown in Table 4. The inputs A0-1 specify the Coefficient
Bank for one of the four multipliers in each FIR Cell; A2
specifies FIR Cell A or B; Bits A7-3 specify one of 32 sets in
which the coefficient is to be stored. For example, an
address of 10dH would access the coefficient for the second
multiplier in FIR B in the second coefficient set.

TABLE 4. FIR COEFFICIENT WRITE ADDRESSES

FIR

COEFF.

A8 A7-3 A2 A1-0 FIR BANK

CSEL (4-0)

COEFF. SET

1 xxxx x 0 00 A 0
1 xxxx x 0 01 A 1
1 xxxx x 0 10 A 2
1 xxxx x 0 11 A 3
1 xxxx x 1 00 B 0
1 xxxx x 1 01 B 1
1 xxxx x 1 10 B 2
1 xxxx x 1 11 B 3

CELL

A/B

MULTIP

LIER DESTINATION

FIR Cell Accumulator

The registered outputs from the multipliers in each FIR cell
feed an accumulator. The ACCEN input controls each
accumulator's running sum and the latching of data from the
accumulator into the Output Holding Registers. When
ACCEN is low, feedback from the accumulator adder is
zeroed which disables accumulation. Also, output from the
accumulator is latched into the Output Holding Registers.
When ACCEN is asserted, accumulation is enabled and the
contents of the Output Holding Registers remain unchanged.

Input/Output Formats

The Dual FIR supports mixed mode arithmetic with both
unsigned and two's complement data and coefficients. The
input and output formats forboth data types are shown below .
If the Dual FIR is configured as an even symmetric filter with
unsigned data and coefficients, the output will be unsigned.
Otherwise, the output will be two's complement.

The MUX/Adder can be configured to implement
programmable rounding at bit locations 2
round is implemented by adding a 1 to the specified location
(see Table 2). Figure 4 illustrates the rounding operation. For
example,to configure the partsuch that the output is rounded
to the 10 MSBs, OUT18 - 27, the round position would be
chosen to be 2

-1

. The negative sign on the MSB indicates 2’s

complement format.

INPUT DATA FORMAT INA0-9, INB0-9

FRACTIONAL TWO’S COMPLEMENT

9876543210

-20.2-12-22-32-42-52-62-72-82

OUTPUT DATA FORMAT OUT9-27

FRACTIONAL TWO'S COMPLEMENT

27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9

-29282726252423222120.2-12-22-32-42-52-62-72-82

OUTPUT DATA FORMAT OUT0-8

FRACTIONAL TWO'S COMPLEMENT

876543210

-102-112-122-132-142-152-162-172-18

2

-10

through 21. The

-9

-9

Output MUX/Adder

The contents of each FIR Cell's Output Holding Register is
summed or multiplexed in the Mux/Adder. The operation of
the Mux/Adder is controlled by the MUX1-0 inputs as
shown in Table 5. Applications requiring 10-bit data and 20­bit coefficients or 20-bit data and 10-bit coefficients are
made possible by configuring the MUX/Adder to scale FIR
B's output by 2
Dual FIR is configured as two independent filters, the
MUX1-0 inputs would be used to multiplex the filter outputs
of each cell. For applications in which FIR A and B are
configured as asingle filter, the MUX/Adderis configured to
sum the output of each FIR cell.

NOTE: While a 20-bit coefficient filter is a single filter, the mode
select is set to 1 and MUX1-0 is set to 00.

MUX1-0 OUT0-27

-10

prior to summing with FIR A. When the

TABLE 5. MUX1-0 BIT DEFINITIONS

MUX1-0 DECODING

00 FIRA + FIRB (FIR B Scaled by 2
01 FIRA + FIRB
10 FIRA
11 FIRB

-10

)

INPUT DATA FORMAT INA0-9, INB0-9

FRACTIONAL UNSIGNED

9876543210

20.2-12-22-32-42-52-62-72-82

OUTPUT DATA FORMAT OUT9-27

FRACTIONAL UNSIGNED

27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9

29282726252423222120.2-12-22-32-42-52-62-72-82

OUTPUT DATA FORMAT OUT0-8

FRACTIONAL UNSIGNED

876543210

-102-112-122-132-142-152-162-172-18

2

FIGURE 3. INPUT/OUTPUT FORMAT DEFINITIONS

-9

-9

9

HSP43168

27
26
25
24
23
22
21
20

I

OUT

9-27

I

OUT

0-8

19
18
17
16
15
14
13
12
11
10

9
8

7
6
5
4
3
2
1
0

1

2

0

2

-1

2

-2

2

-3

2

-4

2

-5

2

-6

2

-7

2

-8

2

-9

2

-10

2

LOCATION OF ADDITION OF 1

OUTPUT BITS

1011

8

1010

9

1001

10

1000

11

0111

12

0110

13

0101

14

0100

15

0011

16

0010

17

0001

18

0000

19

“ROUND POSITION” VALUE

NUMBER OF OUTPUT BITS

FIGURE 4. ROUND POSITION BIT DEFINITION

Application Examples

In this section a number of examples are presented which
detail even, odd, symmetric, asymmetric, decimating and
dual FIR filter configurations. These examples are intended
to illustrate the different operational features of the
HSP43168 and should be used as a guide in developing an
application specific filter configuration. Use Table 6 to select
and find the example that best matches your application.

Two programmable Configuration Control Registers define a
unique FIR filter configuration. Register 000H has all filter
configuration unique parameters, while Register 001H, bit 4, is
filter configuration unique. Table 7 details the configuration
control register values, the number of filter coefficient banks
required andthe MUX1-0 control valuesfor each filter example.

TABLE 7. CONFIGURATION CONTROL REGISTER VALUES

REG

REG

# OF FIL TER

000

001

FILTER TYPE

Even Tap Even

COEFFICIENT

HEX

HEX

BANKS

1d0 010 1 10

MUX

1-0

Symmetric
Odd Tap EvenSymmetric 110 010 1 10
Asymmetric 110 010 2 10
Even Tap Decimate by

1dN 000 N+1 10

N+1
Odd Tap Decimate by

11N 000 N+1 10

N+1
Dual: Even and Odd Tap

Decimate by N+1

15Nor

19N

000

N+1 10 and

11

Bit 4

Example 1. Even-Tap Even Symmetric Filter
Example

The HSP43168 may be configured as two independent
8-tap symmetric filters as shown by the Block Diagram in
Figure 5. Each of the FIR cells takes advantage of
symmetric filter coefficients by pre-adding data samples
common to a given coefficient. As a result, each FIR cell
can implement an 8-tap symmetric filter using only four
multipliers. Similarly, when the HSP43168 is configured in
single filter mode a 16-tap symmetric filter is possible by
using the multipliers in both cells.

TABLE 6. FILTER EXAMPLE SELECTION GUIDE

FILTER TYPE EXAMPLE NUMBER

Even Tap Even Symmetric 1
Odd Tap Even Symmetric 2
Asymmetric 3
Even Tap Decimating 4
Odd Tap Decimating 5
Dual Decimating 6

Examples 1-5 areexplained using a single fourtap FIR cell,
but the same concept applies to FIR filters which use both
FIR cells (A and B) in a single filter configuration. Example
6 details a dual filter mode where FIR cell A and B
implement different digital filters. All examples are
functionally verified configurations. Each example details a
complete design solution, including a block diagram, a
data/coefficient alignment illustration, a data flow diagram
and a control signal timing diagram.

10

HSP43168

8-TAP EVEN SYMMETRIC

INA0-9

AA
BB

INB0-9

8-TAP EVEN SYMMETRIC

FIR A

FIR B

M
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OUT9-27

FIGURE 5. USING HSP43168 AS TWO INDEPENDENT FILTERS

The operationof the FIR cell is better understood by comparing
the data and coefficient alignment for a givenfilter output,
Figure 6, with the data flow through the FIR cell, as shown in
Figure 7. The BlockDiagrams in Figure 7 are a simplification of
the FIR cellshown in Figure 1. Forsimplicity,the ALUs and FIR
Cell Accumulators were replaced by adders, and the Pipeline
Delay Registers were omitted. In this example , w e will only
show the data flow through one of the two FIR cells.

In Figure 7, the order of the data samples within the filter
cell is shown by the numbers in the forward and backward
shifting decimation paths. The output of the filter cell is

HSP43168

given by the equation at the bottom of each block diagram.
Figure 7A shows the data sample alignment at the pre­adders for the data/coefficient alignment shown in Figure 6.

0 1 2 3

C3

C2

h(n)

x(n)

X9 X8 X7 X6 X5 X4 X3 X2 X1 X0

FIGURE 6. DATA/COEFFICIENT ALIGNMENT FOR 8-TAP

EVEN SYMMETRIC FILTER

C1

C0

C3

8 TAPS

C2

C1

C0

The dual filter application is configured by writing 1d0H to
address 000Hvia the microprocessor interface,CIN0-9, A0-8,
and

WR. Since this application does not use decimation, the
4th bit of the Control Register at Address 001H must be set to
disable data rev ersal (see Table 2). Failure to disable data
reversal will produce erroneous results.

Using this architecture, only the unique coefficients need to
be stored in the Coefficient Bank. For example, the above
filter would be stored in the first coefficient set for FIR A by
writing C0, C1, C2, and C3 to Address 100H, 101H, 102H,
and 103H respectively. To write the same filter to the first
coefficient set for FIR B, the address sequence would
change to 104H, 105H, 106H, and 107H.

To operate the HSP43168 in this mode,
ensure proper data flow; both

FWRD and RVRS are tied low

TXFR is tied low to

to enable data samples from the forward and reverse data
paths to the ALUs for pre-adding; ACCEN is tied lo w to
preventaccumulation over multiple CLKs;

SHFTEN is tiedlow
to allow shifting of data through the Decimation Registers;
MUX0-1 is programmed to multiplex the output the of either
FIR A or FIR B; CSEL0-4 is programmable to access the
stored coefficient set, in this example CSEL = 00000.

6 5 47

+ + + +

C0 C1 C2 C3

+

(X7+X0)C0+(X6+X1)C1+(X5+X2)C2+(X4+X3)C3

FIGURE 7A. DATA FLOWAS DATA SAMPLE 7 IS CLOCKED

INTO THE FEED FORWARD STAGE

1 2 3

8

C0 C1 C2 C3

(X8+X1)C0+(X7+X2)C1+(X6+X3)C2+(X5+X4)C3

FIGURE 7B. DATA FLOWAS DATA SAMPLE 8 IS CLOCKED

C0 C1 C2 C3

7 6 5

+ + + +

+

INTO THE FEED FORWARD STAGE

2 3 4 5

8 7 69

+ + + +

4

11

+

(X9+X2)C0+(X8+X3)C1+(X7+X4)C2+(X6+X5)C3

FIGURE 7C. DATA FLOWAS DATA SAMPLE 9 IS CLOCKED

INTO THE FEED FORWARD STAGE

FIGURE 7. DATA FLOWDIAGRAMSFOR 8-TAP SYMMETRIC

FILTER

HSP43168

Example 2. Odd-Tap Even Symmetric
Filter Example

The HSP43168 may be configured as two independent
7-tap symmetric filters with a Functional Block Diagram
shown in Figure 8. Again, this example shows data flow
through one of the two FIR cells. As in the 8-tap filter
example, the HSP43168 implements the filtering operation
by summing data samples sharing a common coefficient
prior to multiplication by that coefficient. However, for odd
length filters the pre-addition requires that the center
coefficient be scaled by 1/2.

HSP43168

7-TAP EVEN SYMMETRIC

INA0-9

AA
BB

INB0-9

7-TAP EVEN SYMMETRIC

FIGURE 8. USING HSP43168 AS TWO INDEPENDENT FILTERS

The operation of the FIR cell for odd length filters is better
understood by comparing the data/coefficient alignment in
Figure 9 with the Data Flow Diagrams in Figure 10. The
Block Diagrams in Figure 10 are a simplification of the FIR
cell shown in Figure 1.

FIR A

FIR B

M

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OUT9-27

0 1 2 3

6

5 4 3

+ + + +

C0 C1 C2 C3/2

+

(X6+X0)C0+(X5+X1)C1+(X4+X2)C2+(X3+X3)C3/2

FIGURE 10A. DATA FLOW AS DATA SAMPLE 6 IS CLOCKED

INTO THE FEED FORWARD STAGE

1 2 3

7

6 5 4

4

+ + + +

C0 C1 C2 C3/2

+

C3

C2

h(n)

x(n)

X9 X8 X7 X6 X5 X4 X3 X2 X1 X0

C1

C0

7-TAPS

C2

C1

C0

FIGURE 9. DATA/COEFFICIENT ALIGNMENT FOR 7-TAP

SYMMETRIC FILTER

For odd length filters, proper data/coefficient alignment is
ensured by routing data entering the last register in the
third forward decimation stage to the Backward Shifting
Registers. In this configuration, the center coefficient must
be scaled by 1/2 to compensate for the summation of the
same data sample from both the Forward and Backward
Shifting Registers.

(X7+X1)C0+(X6+X2)C1+(X5+X3)C2+(X4+X4)C3/2

FIGURE 10B. DATA FLOW AS DATA SAMPLE 7 IS CLOCKED

INTO THE FEED FORWARD STAGE

2 3 4

8

7 6 5

5

+ + + +

C0 C1 C2 C3/2

+

(X8+X2)C0+(X7+X3)C1+(X6+X4)C2+(X5+X5)C3/2

FIGURE 10C. DATA FLOW AS DATA SAMPLE 8 IS CLOCKED

INTO THE FEED FORWARD STAGE

FIGURE 10. DATA FLOWDIAGRAMSFOR 7-TAP SYMMETRIC

FILTER

12

HSP43168

In the Data Flow Diagrams of Figure10, the order of the data
samples input in to the filter cell is shown by the numbers in
the forward and backward shifting decimation paths. The
output of the filter cell is given by the equation at the bottom
of the block. The Diagram in Figure 10A shows data sample
alignment at the pre-adders for the Data/Coefficient
Alignment shown in Figure 9.

This dual filter application is configured by writing 110H to
Address 000H via the microprocessor interface, CIN0-9,
A0-8, and WR. Also, data reversal must be disabled by
setting bit 4 of the Control Register at Address 0001H. As in
the 8-tap example, only the unique coefficients need to be
stored in the Coefficient Bank. These coefficients are stored
in the first coefficientset for FIR A by writing C0, C1, C2, and
C3 to Address100H, 101H, 102H, and 103H respectively. To
write the same filter to the first coefficient set for FIR B, the
address sequence would change to 104H, 105H, 106H, and
107H. The control signals TXFR, FWRD, RVRS, ACCEN,
SHFTEN, and CSEL0-4 are controlled as described in
Example 1.

Example 3. Asymmetric Filter Example

The FIR cells within the HSP43168 can each calculate 4
asymmetric taps on each clock. Thus, a single FIR cell can
implement an 8-tap asymmetric filter if the HSP43168 is
clocked at twice the input data rate. Similarly, if the Dual is
configured as a single filter, a 16-tap asymmetric filter is
realizable. Only one of the two FIR cells are used in this
example for the Block Diagram shown in Figure 11.

For this example, the FIR cells are configured as two 8-tap
asymmetric filters which are clocked at twice the input data
rate. New data is shifted into the forward and backward
decimation paths every other CLK by the assertion of
SHFTEN. The filter output is computed bypassing data from
each decimation path to themultipliers on alternating clocks.
Two sets of coefficients are required, one for data on the
forward decimation path, and one for data on the reverse
path. The filter output is generated by accumulating the
multiplier outputs for two CLKs.

HSP43168

8-TAP ASYMMETRIC

INA0-9

AA
BB

INB0-9

FIGURE 11. USING HSP43168 AS TWO INDEPENDENT

FIR A

8-TAP ASYMMETRIC

FIR B

FILTERS

M
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OUT9-27

The operation of this configuration is better understood by
comparing the Data/Coefficient Alignment in Figure 12 with
the Data Flow Diagrams in Figure 13. The ALUs have been
omitted fromthe FIR cell diagrams becausedata is fed to the
multipliers directly from the forward and reverse decimation
paths. The data samples within the FIRcell are shown bythe
numbers in the decimation paths.

h(n)

x(n)

X9 X8 X7 X6 X5 X4 X3 X2 X1 X0

FIGURE 12. DATA/COEFFICIENT ALIGNMENT FOR 8-TAP

C7 C6 C5 C4 C3

ASYMMETRIC FILTER

8-TAPS

C2

C1

C0

13

0 1 2 3

HSP43168

0 1 2 3

6 5 4

C0 C1 C2 C3

ACCUMULATOR

(X0)C0+(X1)C1+(X2)C2+(X3)C3

FIGURE 13A. DATA SHIFTING DISABLED,BACKWARD

SHIFTING DECIMATION REGISTERS FEEDING
MULTIPLIERS

1 2 3 4

7 6 5

C0 C1 C2 C3

7

C7 C6 C5 C4

6 5 4

ACCUMULATOR

(X0)C0+(X1)C1+(X2)C2+(X3)C3

+(X7)C7+(X6)C6+(X5)C5+(X4)C4

FIGURE 13B. SHIFTING OF DATA SAMPLE 7 INTOFIR CELL

ENABLED, FORWARD SHIFTING REGISTERS
FEEDING MULTIPLIERS

1234

8

C7 C6 C5 C4

76 5

ACCUMULATOR

(X1)C0+(X2)C1+(X3)C2+(X4)C3

FIGURE 13C. DATA SHIFTING DISABLED, BACKWARD

SHIFTING DECIMATION REGISTERS FEEDING
MULTIPLIERS

FIGURE 13. DATA FLOW DIAGRAMS FOR 8-TAP ASYMMETRIC FILTER

For this application, each filter cell is configured as an odd
length filter by writing 110H to the Control Register at
Address 000H. Even though an even tap filter is being
implemented, the filter cells must be configured as odd
length to ensure proper data flow. In addition, the filters
must be set to even symmetry. Also, the 4th bit at Control
Address 001H must be set to disable data reversal, and
TXFR must be tied low. Since an 8-tap asymmetric filter is
being implemented, two sets of coefficients must be stored.

ACCUMULATOR

(X1)C0+(X2)C1+(X3)C2+(X4)C3

+(X8)C7+(X7)C6+(X6)C5+(X5)C4

FIGURE 13D. SHIFTING OF DATA SAMPLE 8 INTO FIR CELL

ENABLED, FORWARD SHIFTING REGISTERS
FEEDING MULTIPLIERS

These eight coefficients could be loaded into the first two
coefficient sets forFIR A by writing C0, C1, C2, C3, C7, C6,
C5, and C4 to address 100H, 101H, 102H, 103H, 108H,
109H, 10aH, and 10bH respectively.

The sum of products required for this 8-tap filter require
dynamic control over

FWRD, RVRS, ACCEN, and
CSEL0-4. The relative timing of these signals is shown in
Figure 14.

14

HSP43168

0 1 2 3 13 14 15 16

CLK

†

INA0-9

CSEL0-4

ACCEN

FWRD

RVRS

SHFTEN

TXFR

X0 X1

101 0 01 10

X6 X7 X8

0

(TIED LOW)

†Note that CLK is 2X data rate.

FIGURE 14. CONTROL TIMING FOR 8-TAP ASYMMETRIC

FILTER

Example 4. Even-Tap Decimating Filter Example

The HSP43168 supports filtering applications requiring
decimation to 16. In these applications the output data rate
is reduced bya factor ofN. As a result, N clockcycles can be
used for the computation of the filter output. For example,
each FIR cell can calculate 8 symmetric or 4 asymmetric
taps in one clock. If the application requires decimation by
two, the filter output can be calculated over two clocks thus,
boosting the number of taps per FIR cell to 16 symmetric or
8 asymmetric. For this example, each FIR cell is configured
as an independent 24-tap decimate x3 filter. Again, the data
flow diagrams show only one of the FIR cells shown in
Figure 15.

The alignment of data relative to the 24 filter coefficients for
a particular output is depicted graphically in Figure 16. As in
previous examples, the HSP43168 implements the filtering
operation bysumming data samples prior to multiplicationby
the common coefficient. In this example an output is
required every third CLK which allows 3 CLKs for
computation. On each CLK, one of three sets of coefficients
are used to calculate 8 of the filter taps. The Block Diagrams
in Figure 17 show the data flow and accumulator output for
the data/coefficient alignment in Figure 16.

Proper data and coefficient alignment is achieved by
asserting

TXFR once every three CLKs to switch the LIFOs
which are being read and written. This has the effect of
feeding blocks of three samples into the backward shifting
decimation path which are reversed in sample order. In
addition, ACCEN is deasserted once every three clocks to
allow accumulation over three CLKs. The three sets of
coefficients required in the calculation of a 24-tap symmetric
filter are cycled through using CSEL0-4. The timing
relationship between the CSEL0-4, ACCEN, and

TXFR are

shown in Figure 18.
To operate in this mode the Dual is configured by writing 1d2

to Address 000H via the microprocessor interface, CIN0-9,
A0-8, and WR. Data reversalmust be enabled see (Table 2).
The 12 unique coefficients for this example are stored as
three sets of coefficients for either FIR cell. For FIR A, the
coefficients are loaded into the Coefficient Bank by writing
C2, C5, C8, C11, C1, C4, C7, C10, C0, C3, C6, and C9 to
Address [100H, 101H, 102H, 103H], CSEL = 0; [108H,
109H, 10aH, 10bH], CSEL = 1; [110H, 111H, 112H, and
113H], CSEL = 2, respectively.

C11

C11

INA0-9

AA
BB

INB0-9

HSP43168

EVEN-TAP DECIMATING

FIR A

EVEN-TAP DECIMATING

FIR B

h(n)

C1

C0

M
U
X

OUT9-27

x(n)

23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

C4

C3

C2

C7

C6

C5

C10

C9

C8

C10

C9

C8

C7

C6

C5

C4

C3

FIGURE 15. EVEN-TAP DECIMATING FILTER, 24-TAP DEC = 3 FIGURE 16. DATA/COEFFICIENT ALIGNMENT FOR 24-TAP

DECIMATE BY 3 FIR FILTER

15

24-TAPS

C2

C1

C0

HSP43168

012

21

181920

345

151617

678 91011

121314

+ + + +

C2 C5 C8 C11

ACCUMULATOR

(X2+X21)C2+(X5+X18)C5+(X8+X15)C8+(X11+X12)C11

CSEL = 0

FIGURE 17A. COMPUTATIONAL FLOWAS DATASAMPLE 21 IS

CLOCKED INTO THE FEED FORWARD STAGE

4

50

202122 171819 14151623

783

10116

9

12 13

+ + + +

C0 C3 C6 C9

ACCUMULATOR

(X0+X23)C0+(X3+X20)C3+(X6+X17)C6+(X9+X14)C9
+(X1+X22)C1+(X4+X19)C4+(X7+X16)C7+(X10+X13)C10
+(X2+X21)C2+(X5+X18)C5+(X8+X15)C8+(X11+X12)C11

CSEL = 2

ACCEN ASSERTED
AND ACTIVE

TXFR ASSERTED
AND ACTIVE

501834

22

192021 161718 131415

11

67

910

12

+ + + +

C1 C4 C7 C10

ACCUMULATOR

(X1+X22)C1+(X4X19)C4+(X7+X16)C7+(X10+X13)C10

+(X2+X21)C2+(X5+X18)C5+(X8+X15)C8+(X11+X12)C11

CSEL = 1

FIGURE 17B. COMPUTATIONAL FLOWAS DATASAMPLE 22 IS

CLOCKED INTO THE FEED FORWARD STAGE

345678

24

212223 181920 151617

91011

13 12

14

+ + + +

C2 C5 C8 C11

ACCUMULATOR

(X5+X24)C0+(X8+X21)C5+(X11+X18)C8+(X14+X15)C11

CSEL = 0

FIGURE 17C. COMPUTATIONAL FLOWAS DATA SAMPLE 23 IS

CLOCKED INTO THE FEED FORWARD STAGE

FIGURE 17. DATA FLOW DIAGRAMS FOR 24-TAP DECIMATED BY 3 FIR FILTER

21 22 23

22 2321

CLK

INA0-9

CSEL0-4

ACCEN

FWRD†

RVRS†

SHIFTEN†

TXFR

0123

0

123

0120

5

4

4 5

1 2 012

†Tied low.

FIGURE 18. CONTROL SIGNAL TIMING FOR 24-TAP

DECIMATE X3 FILTER

FIGURE 17D. COMPUTATIONAL FLOWAS DATA SAMPLE 24 IS

CLOCKED INTO THE FEED FORWARD STAGE

Example 5. Odd-Tap Decimating Symmetric Filter

This example highlights the use of the HSP43168 as two
independent, 23-tap, symmetric, decimate by 3 filters. In this
example, the operational differences in the control signals
and data reversal structure may be compared to the
previously discussed even-tap decimating filter. Figure 19
shows two FIR cells. The data flow in this example uses only
one of the FIR cells.

HSP43168

ODD-TAP DECIMATING

INA0-9

AA
BB

INB0-9

FIGURE 19. USING HSP43168 AS TWO INDEPENDENT FILTERS

FIR A

ODD-TAP DECIMATING

FIR B

M
U
X

OUT9-27

16

HSP43168

As in the 24-tap example, an output is required every third
CLK which allows 3 CLKs for computation. On each CLK,
one of three sets of coefficients are used to calculate the
filter taps. Since this is an odd length filter, the center
coefficient must be scaled by 1/2 to compensate for the
summation of the same data sample from the forward and
backward shifting decimation paths. The Block Diagrams in
Figure 20 show the data flow, and theaccumulator output for
the data coefficient alignment is shown in Figure 21.

C11/2

789111012

CSEL = 0

123456

21

181920 151617 121314

+ + + +

C2

(X3+X21)C2+(X6+X18)C5+(X9+X15)C8+(X12+X12)C11/2

C5 C8

ACCUMULATOR

Proper data and coefficient alignment is achieved byasserting
TXFR once every three CLKs to switch the LIFOs which are
being read and written. In the odd-tap mode, TXFR is internally
delayed by one cloc k cycle with respect to ACCEN so that the
convolutional sum will be computed correctly. For odd length
filters, data prior to the last register in the forward decimation
path is routed to the feedback circuitry. As a result, TXFR
should be asserted one cycle prior to the input data samples
which alignwith the center tap.The timing relationshipbetween
the CSEL0-5, ACCEN, and TXFR are shown in Figure 22.

612945

22

192021

161718 131415

12

78

+ + + +

C1 C4 C7 C10

ACCUMULATOR

(X2+X22)C1+(X5+X19)C4+(X8+X16)C7+(X11+X13)C10

+(X3+X21)C2+(X6+X18)C5+(X9+X15)C8+(X12+X12)C11/2

1011

13

CSEL = 1

FIGURE 20A. COMPUTATIONAL FLOWAS DATASAMPLE 21IS

CLOCKED INTO THE FEED FORWARD STAGE
TXFR TAKES AFFECT ON THIS CLOCK CYCLE

11127

561894

23

202122 171819 141516

10

13 14

+ + + +

C0 C3 C6 C9

ACCUMULATOR

(X1+X23)C0+(X4+X20)C3+(X7+X17)C6+(X14+X10)C9

+(X2+X22)C1+(X5+X19)C4+(X8+X16)C7+(X11+X13)C10

+(X3+X21)C2+(X6+X18)C5+(X9+X15)C8+(X12+X12)C11/2

CSEL = 2

ACCEN ASSERTED
AND ACTIVE

TXFR ASSERTED

FIGURE 20C. COMPUTATIONAL FLOWAS DATASAMPLE 23 IS

CLOCKED INTO THE FEED FORWARD STAGE

FIGURE 20. DATA FLOW DIAGRAMS FOR 23-TAP DECIMATE BY 3 SYMMETRIC FILTER

FIGURE 20B. COMPUTATIONAL FLOWAS DATASAMPLE 22IS

CLOCKED INTO THE FEED FORWARD STAGE

101112 14 13

456789

24

2122

23

181920

15

151617

+ + + +

C2 C5 C8 C11/2

ACCUMULATOR

(X6+X24)C2+(X9+X21)C5+(X12+X18)C8+(X15+X15)C11/2

CSEL = 0

FIGURE 20D. COMPUTATIONAL FLOWAS DATA SAMPLE 24 IS

CLOCKED INTO THE FEED FORWARD STAGE
TXFR TAKES AFFECT ON THIS CLOCK CYCLE

17

HSP43168

C11

C10

C10

C9

h(n)

C2

C1

C0

x(n)

23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

C3

C4

C5

C6

C7

C8

C9

C8

C7

C6

C5

C4

C3

23-TAPS

C2

C1

C0

FIGURE 21. DATA/COEFFICIENT ALIGNMENT FOR 23-TAP

DECIMATE BY 3 SYMMETRIC FILTER

20 21 22

22 2321

CLK

INA0-9

CSEL0-4

ACCEN

FWRD†

RVRS†

SHIFTEN†

TXFR

0123

123

0

012 0

5

4

4 5

1 2 012

†Tied low.

FIGURE 22. CONTROL SIGNAL TIMING FOR 23-TAP

SYMMETRIC FILTER

To operate in this mode, the Dual is configured by writing
112H to Address 000H via the microprocessor interface,
CIN0-9, A0-8, and

WR. Data reversal must be enabled (see
Table 2). The 12 unique coefficients for this example are
stored as three sets of coefficients foreither FIR cell. ForFIR
A, the coefficients are loaded into the Coefficient Bank by
writing [C2, C5, C8, (C11)/ 2], CSEL = 0; [C1, C4, C7, C10],
CSEL = 1; [C0, C3, C6, and C9], CSEL = 2; to address
100H, 101H, 102H, 103H, 108H, 109H, 10aH, 10bH, 110H,
111H, 112H, and 113H, respectively.

Example 6. Dual Decimation Example

The purpose of this exampleis to givean overview of one of
the more complex applications of the HSP43168. The input
is two data streams (A) and (B) samples. Figure 23 shows
the upper level block diagram of the system being
implemented. The decimation rate was set to N. N-1 is
loaded into the decimation factor in Control Word 000H.

F

S

B3, B2, B1, B0

A3, A2, A1, A0

INB0-9

HSP43168

INA0-9

DECIMATE BY N

FIGURE 23. MULTIPLEXED DECIMATION BLOCK DIAGRAM

To demonstrate the muxed decimation, lets suppose that the
application requires filter A to be configured as an
even-decimate-by-3 filter and filter B to be configured as a
odd-decimate-by-3 filter. The output data is made of the two
decimated data streamsmultiplexed togetherand has a data
rate equal to 2 times the input sampling rate divided by the
decimation factor. Figure 24 shows the data/coefficient
alignment for FIR A and FIR B.

To operate in this mode, Control Word 000H must be written
with a 0x152. Data reversal must be enabled by setting bit 4
of Control Word 001H = 0. The filter set selected by
CSEL0-4 = 0 should be loaded by writing C2, C5, C8, C11,
D2, D5, D8, and (D11)/ 2 into 100H, 101H, 102H, 103H,
104H, 105H, 106H, and 107H. The filter set selected by
CSEL0-4 = 1 should be loaded by writing C1, C4, C7, C10,
D1, D4, D7, and D10 into 108H, 109H, 10aH, 10bH, 10cH,
10dH, 10eH, and 10fH. The filter set selected by
CSEL0-4 = 2 should be loaded by writing C0, C3, C6, C9,
D0, D3, D6, and D9 into 110H, 111H, 112H, 113H, 114H,
115H, 116H, and 117H.

2FS/(N+1)

OUT9-27

BOUT1
AOUT1
BOUT0
AOUT0

18

HSP43168

D11

D10

D10

D9

D8

D7

h2(n)

D0

B(n)

23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3210

h1(n)

C0

A(n)

23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

D3

D2

D1

C3

C2

C1

D6

D5

D4

C10

C9

C8

C7

C6

C5

C4

C11

C11

D9

C10

D8

C9

C8

D7

D6

C7

FIRB

D5

FIRA

C6

D4

C5

D3

C4

23-TAPS

D2

D1

24-TAPS

C3

C2

D0

C1

FIGURE 24. DATA/COEFFICIENTALIGNMENT FOR

MULTIPLEXED DECIMATION EXAMPLE

FIR B

789111012

B DATA

STREAM

21

123456

181920 151617 121314

+ + + +

D2 D5 D8

D11/2

CSEL = 0

Figure 25 shows the Timing Diagram required to obtained the
multiplexed/decimatedoutput. The output of the two filtersare
providedat by selecting theodd-decimation filter first, then the
even-decimation second using MUX0-1. Figure 26 shows the
Data Flow Diagram for the m ultiplexed decimation example.

12

20 21 22

21 2220

FIR B

1011

13

CSEL = 1

5

0123

CLK

0

INA0-9

CSEL0-4

ACCEN

C0

MUX0-1

TXFR

123

012 0

11 10 11 11 1110

4

4 5

1 2 201

FIGURE 25. TIMING DIAGRAMFOR MULTIPLEXED

DECIMATION EXAMPLE

612945

22

192021

161718 131415

78

+ + + +

D1 D4 D7 D10

ACCUMULATOR

(X3+X21)D2+(X6+X18)D5+(X9+X15)D8+(X12+X12)D11/2

FIR A

A DATA

STREAM

21

012

181920

345

151617

678 91011

121314

+ + + +

C2 C5 C8 C11

ACCUMULATOR

(X2+X21)C2+(X5+X18)C5+(X8+X15)C8+(X11+X12)C11

CSEL = 0

FIGURE 26A. COMPUTATIONAL FLOWAS DATASAMPLE 21 IS

CLOCKED INTO THE FEED FORWARD STAGE

19

ACCUMULATOR

(X2+X22)D1+(X5+X19)D4+(X8+X16)D7+(X11+X13)D10

+(X3+X21)D2+(X6+X18)D5+(X9+X15)D8+(X12+X12)D11/2

FIR A

501834

22

192021 161718 131415

11

67

910

12

+ + + +

C1 C4 C7 C10

ACCUMULATOR

(X1+X22)C1+(X4X19)C4+(X7+X16)C7+(X10+X13)C10

+(X2+X21)C2+(X5+X18)C5+(X8+X15)C8+(X11+X12)C11

CSEL = 1

FIGURE 26B. COMPUTATIONAL FLOWAS DATASAMPLE 22 IS

CLOCKED INTO THE FEED FORWARD STAGE

HSP43168

561894

23

202122 171819 141516

11127

+ + + +

D0 D3 D6 D9

OUTPUT OF B IS SENT

ACCUMULATOR

(X1+X23)D0+(X4+X20)D3+(X7+X17)D6+(X14+X10)D9

+(X2+X22)D1+(X5+X19)D4+(X8+X16)D7+(X11+X13)D10

+(X3+X21)D2+(X6+X18)D5+(X9+X15)D8+(X12+X12)D11/2

450783

23

202122 171819 141516

TO OUT9-27

10116

+ + + +

C0 C3 C6 C9

FIR B

10

13 14

CSEL = 2

FIR A

9

12 13

CSEL = 2

456789

24

2122

23

181920

+ + + +

D2 D5 D8 D11/2

ACCUMULATOR

(X6+X24)D2+(X9+X21)D5+(X12+X18)D8+(X15+X15)D11/2

345678

24

212223 181920 151617

+ + + +

C2 C5 C8 C11

FIR B

101112 14 13

15

151617

CSEL = 0

FIR A

91011

13 1214

CSEL = 0

ACCUMULATOR

(X0+X23)C0+(X3+X20)C3+(X6+X17)C6+(X9+X14)C9
+(X1+X22)C1+(X4+X19)C4+(X7+X16)C7+(X10+X13)C10
+(X2+X21)C2+(X5+X18)C5+(X8+X15)C8+(X11+X12)C11

FIGURE 26C. COMPUTATIONAL FLOW AS DATA SAMPLE 23

IS CLOCKED INTO THE FEED FORWARD STAGE

FIGURE 26. DATA FLOW DIAGRAM FOR MULTIPLEXED DECIMATION EXAMPLE

ACCUMULATOR

(X5+X24)C0+(X8+X21)C5+(X11+X18)C8+(X14+X15)C11

OUTPUT OF A IS SENT
TO OUT9-27

FIGURE 26D. COMPUTATIONAL FLOWAS DATA SAMPLE 24 IS

CLOCKED INTO THE FEED FORWARD STAGE

20

HSP43168

Absolute Maximum Ratings Thermal Information

Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8.0V

Input, Output or I/O Voltage. . . . . . . . . . . .GND -0.5V to VCC+0.5V

ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Class 1

Operating Conditions

Voltage Range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V ±5%

Temperature Range, Commercial . . . . . . . . . . . . . . . . . 0oC to 70oC

Temperature Range, Industrial. . . . . . . . . . . . . . . . . . . .-40oC to 85

o

Die Characteristics

Back Side Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V

Number of Transistors or Gates. . . . . . . . . . . . . . . . . . . . . . . .32529

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

1. θJA is measured with the component mounted on an evaluation PC board in free air.

DC Electrical Specifications

PARAMETER SYMBOL TEST CONDITIONS MIN MAX UNITS

Power Supply Current I

Standby Power Supply Current I
Input Leakage Current I
Output Leakage Current I
Logical One Input Voltage V
Logical Zero Input Voltage V
Logical One Output Voltage V
Logical Zero Output Voltage V
Clock Input High V
Clock Input Low V
Input Capacitance C
Output Capacitance C

CCOP

CCSB

I

O

IH

IL

OH

OL
IHC
ILC

IN

OUT

NOTES:

2. Controlled via design or process parameters and not directly tested. Characterized upon initial design and after major process and/or changes.

3. Power Supply current is proportional to operating frequency. Typical rating for I

4. Output load per test load circuit and CL= 40pF.

5. Maximum junction temperature must be considered when operating part at high clock frequencies.

VCC = Max
CLK Frequency 33MHz
Notes 3, 4, 5

VCC = Max, Outputs Not Loaded - 500 µA
VCC = Max, Input = 0V or V
VCC = Max, Input = 0V or V
VCC = Max 2.0 - V
VCC = Min - 0.8 V
IOH = -400µA, VCC = Min 2.6 - V
IOL = 2mA, VCC = Min - 0.4 V
VCC = Max 3.0 - V
VCC = Min - 0.8 V
CLK Frequency 1MHz

All measurements referenced
to GND.
TA = 25oC, Note 2

Thermal Resistance (Typical, Note 1) θJA (oC/W) θJC (oC/W)

CPGA Package . . . . . . . . . . . . . . . . . . 35 6

MQFP Package . . . . . . . . . . . . . . . . . . 33.0 N/A

PLCC Package. . . . . . . . . . . . . . . . . . . 23.0 N/A

Maximum Junction Temperature

CPGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175oC

MQFP and PLCC Packages. . . . . . . . . . . . . . . . . . . . . . . . .150oC

Maximum Storage Temperature Range. . . . . . . . . . -65oC to 150oC

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC

(MQFP and PLCC - Leads Tips Only)

- 363 mA

CC
CC

-10 10 µA

-10 10 µA

-12pF

-12pF

is 11mA/MHz.

CCOP

21

HSP43168

AC Electrical Specifications V

= +4.75V to +5.25V, TA = 0oC to 70oC Commercial, TA = -40oC to 85oC Industrial (Note 6)

CC

-33 (33MHz) -40 (40.8MHz) -45 (45MHz)

PARAMETER SYMBOL NOTES

CLK Period t
CLK High t
CLK Low t
WR Period t
WR High t
WR Low t
Setup Time A0-8 to WR Going Low t
Hold Time A0-8 from WR Going High t
Setup Time CIN0-9 to WR Going High t
Hold Time CIN0-9 from WR Going High t
Setup Time WR Low to CLK Low t
Setup Time CIN0-9 to CLK Low t
Setup Time CSEL0-5, SHFTEN, FWRD, RVRS, TXFR,

CP
CH

CL
WP
WH

WL

AWS
AWH
CWS
CWH

WLCL
CVCL

t

ECS

30 - 24.5 - 22 - ns
12 - 10 - 8 - ns
12 - 10 - 8 - ns
30 - 24.5 - 22 - ns
12 - 10 - 10 - ns
12 - 10 - 10 - ns
10 - 8 - 8 - ns

0-0-0-ns

12 - 11 - 10 - ns

1-1-1-ns
Note 7 5 - 4 - 3 - ns
Note 7 7 - 7 - 7 - ns

15 - 13 - 12 - ns

UNITSMIN MAX MIN MAX MIN MAX

INA0-9, INB0-9, ACCEN, MUX0-1 to CLK
Going High

Hold Time CSEL0-5, SHFTEN, FWRD, RVRS, TXFR,

t

ECH

0-0-0-ns

INA0-9, INB0-9, ACCEN, MUX0-1 to CLK
Going High

CLK to Output Delay OUT0-27 t
Output Enable Time t
Output Disable Time t
Output Rise, Fall Time t

DO
OE
OD
RF

Note 8 - 12 - 12 - 12 ns
Note 8 - 6 - 6 - 6 ns

-14-13-12ns

-12-12-12ns

NOTES:

6. AC tests performed with CL= 40pF,IOL= 2mA,and IOH= -400µA.Input reference level CLK = 2.0V. Input reference level for all other inputs is

1.5V. Test VIH = 3.0V, V

= 4.0V, VIL = 0V, V

IHC

ILC

= 0V.

7. Setup time requirement for loading of data on CIN0-9 to guarantee recognition on the following clock.

8. Controlled via design or process parameters and not directly tested. Characterized upon initial design and after major process and/or changes.

AC Test Load Circuit

SWITCH S1 OPEN FOR I

NOTE: Test head capacitance.

22

DUT

CCSB

C

L

AND I

S

1

(NOTE)

CCOP

±

I

OH

EQUIVALENT CIRCUIT

1.5V I

OL

Waveforms

CLK

CSEL0 - 4, MUX0 - 1

SHFTEN, FWRD

RVRS, TXFR

INA0 - 9, INB0 - 9,

ACCEN

OUT0 - 27

HSP43168

t

ECStECH

t

DO

t

WLCL

t

WL

t

CP

t

CH

t

WP

t

CL

t

WH

WR

A0 - 8

CIN0 - 9

OEL, OEH

OUT0 - 27

t

t

CVCL

CWH

1.7V

1.3V

t

AWH

1.5V
t

OD

HIGH

IMPEDANCE

t

AWS

t

1.5V

t

OE

HIGH

IMPEDANCE

CWS

FIGURE 27. OUTPUT ENABLE, DISABLE TIMING

2.0V

0.8V

2.0V

0.8V

23

t

RF

t

RF

FIGURE 28. OUTPUT RISE AND FALL TIMES

HSP43168

Metric Plastic Quad Flatpack Packages (MQFP)

E

E1

0.40

0.016
0o MIN

0o-7

-H-

o

-A-

MIN

D

D1

-D-

Q100.14x20 (JEDEC MS-022GC-1 ISSUE B)

100 LEAD METRIC PLASTIC QUAD FLATPACK PACKAGE

INCHES MILLIMETERS

SYMBOL

NOTESMIN MAX MIN MAX

A - 0.134 - 3.40 -

A1 0.010 - 0.25 - -

-B-

A2 0.101 0.113 2.57 2.87 -

b 0.009 0.015 0.22 0.38 6

b1 0.009 0.013 0.22 0.33 -

D 0.908 0.918 23.08 23.32 3

D1 0.782 0.792 19.88 20.12 4, 5

E 0.673 0.681 17.10 17.30 3

e

PIN 1

E1 0.547 0.555 13.90 14.10 4, 5

L 0.029 0.040 0.73 1.03 ­N 100 100 7
e 0.026 BSC 0.65 BSC -

SEATING

A

PLANE

ND 30 30 ­NE 20 20 -

0.076

o

12o-16

0.20

0.008

A2

A1

o

L

12o-16

0.005/0.007

BASE METAL

A-B SD SCM

0.13/0.17

WITH PLATING

0.003

-C-

b

b1

0.13/0.23

0.005/0.009

NOTES:

1. Controllingdimension: MILLIMETER.Converted inch
dimensions are not necessarily exact.

2. All dimensions and tolerances per ANSI Y14.5M-1982.

3. DimensionsD andE tobe determinedat seatingplane .

4. Dimensions D1 and E1 to be determined at datum plane

.

-H-

5. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is 0.25mm (0.010 inch) per side.

6. Dimension b does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08mm (0.003 inch) total.

7. “N” is the number of terminal positions.

Rev. 1 4/99

-C-

24

Ceramic Pin Grid Array Packages (CPGA)

HSP43168

S1

S

NOTE 7

–C–

A

C

INDEX CORNER
SEE NOTE 9

SEE

A

A

L

A1

Q

0.008 C

B

B

D

D1

S
b1

A1

e

b

M MM
M

Ø0.010 C

–A–

SECTION B-B

SEATING PLANE

Q

SECTION A-A

C

AØ0.030 B

E1

b

AT STANDOFF

k

L

b2

–B–

G84.A MIL-STD-1835 CMGA3-P84C (P-AC)

84 LEAD CERAMIC PIN GRID ARRAY PACKAGE

INCHES MILLIMETERS

SYMBOL

A 0.215 0.345 5.46 8.76 -

A1 0.070 0.145 1.78 3.68 3

b 0.016 0.0215 0.41 0.55 8
b1 0.016 0.020 0.41 0.51 ­b2 0.042 0.058 1.07 1.47 4

C - 0.080 - 2.03 -

E

D 1.140 1.180 28.96 29.97 ­D1 1.000 BSC 25.4 BSC -

E 1.140 1.180 28.96 29.97 ­E1 1.000 BSC 25.4 BSC -

e 0.100 BSC 2.54 BSC 6

k 0.008 REF 0.20 REF -

L 0.120 0.140 3.05 3.56 -

Q 0.040 0.060 1.02 1.52 5

S 0.000 BSC 0.00 BSC 10
S1 0.003 - 0.08 - -

M11 111

N - 121 - 121 2

NOTES:

1. “M” represents the maximum pin matrix size.

2. “N” represents the maximum allowable number of pins.Number
of pins and location of pins within the matrix is shown on the
pinout listing in this data sheet.

3. Dimension “A1” includes the packagebody and Lid for both cav­ity-up and cavity-down configurations. This packageis cavityup.
Dimension “A1” does not include heatsinks or other attached
features.

4. Standoffs are intrinsic and shall be located on the pin matrix di­agonals. The seating plane is defined by the standoffs at dimen­sions Q.

5. Dimension “Q” applies to cavity-up configurations only.

6. All pins shall be on the 0.100 inch grid.

7. Datum C is the plane of pin to package interface for both cavity
up and down configurations.

8. Pindiameter includes solderdip or customfinishes.Pin tipsshall
have a radius or chamfer.

9. Corner shape (chamfer, notch, radius, etc.) may vary from that
shown on the drawing. The index corner shall be clearly unique.

10. Dimension “S” is measured with respect to datums A and B.

11. Dimensioning and tolerancing per ANSI Y14.5M-1982.

12. Controlling dimension: INCH.

NOTESMIN MAX MIN MAX

Rev. 1 6/28/95

25

HSP43168

Plastic Leaded Chip Carrier Packages (PLCC)

0.042 (1.07)

0.048 (1.22)
PIN (1) IDENTIFIER

0.020 (0.51) MAX
3 PLCS

C

L

D1

D

0.026 (0.66)

0.032 (0.81)

0.045 (1.14)
MIN

0.042 (1.07)

0.056 (1.42)

0.050 (1.27) TP

VIEW “A” TYP.

C

L

EE1

0.013 (0.33)

0.021 (0.53)

0.025 (0.64)
MIN

0.004 (0.10) C

0.025 (0.64)

0.045 (1.14)

D2/E2

D2/E2

A1

A

-C-

VIEW “A”

0.020 (0.51)
MIN

SEATING
PLANE

N84.1.15 (JEDEC MS-018AF ISSUE A)

84 LEAD PLASTIC LEADED CHIP CARRIER PACKAGE

R

SYMBOL

A 0.165 0.180 4.20 4.57 -

A1 0.090 0.120 2.29 3.04 -

D 1.185 1.195 30.10 30.35 ­D1 1.150 1.158 29.21 29.41 3
D2 0.541 0.569 13.75 14.45 4, 5

E 1.185 1.195 30.10 30.35 ­E1 1.150 1.158 29.21 29.41 3
E2 0.541 0.569 13.75 14.45 4, 5

N84 846

INCHES MILLIMETERS

NOTESMIN MAX MIN MAX

Rev. 2 11/97

NOTES:

1. Controllingdimension:INCH. Converted millimeterdimensions are
not necessarily exact.

2. Dimensions and tolerancing per ANSI Y14.5M-1982.

3. Dimensions D1 and E1do not include mold protrusions. Allowable
mold protrusion is 0.010 inch (0.25mm) per side. Dimensions D1
and E1 include mold mismatch and are measured at the extreme
material condition at the body parting line.

4. To be measured at seating plane contact point.

-C-

5. Centerline to be determined where center leads exit plastic body.

6. “N” is the number of terminal positions.

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.

Intersil semiconductor products are sold by description only. Intersil Corporation reserves the rightto make changes in circuit design and/or specifications at any time with­out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringementsof patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products,see web site www.intersil.com

Sales Office Headquarters

NORTH AMERICA

Intersil Corporation
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: [phone]
FAX: [phone]

EUROPE

Intersil SA
Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
TEL: [phone]
FAX: [phone]

ASIA

Intersil (Taiwan) Ltd.
7F-6, No. 101 Fu Hsing North Road
Taipei, Taiwan
Republic of China
TEL: [phone]
FAX: [phone]

26