Datasheet HSMP-382x, HSMP- 482x Datasheet (AVAGO)

HSMP-382x, 482x

COMMON

CATHODE

#4

COMMON

ANODE

#3

SERIES

#2

SINGLE

#0

DUAL ANODE

HSMP-4820

DUAL ANODE

HSMP-482B

Surface Mount RF PIN Switch and Limiter Diodes

Data Sheet

Description/Applications

The HSMP-382x series is optimized for switching ap­plications where ultra-low resistance is required. The
HSMP-482x diode is ideal for limiting and low induc­tance switching applications up to 1.5 GHz.

A SPICE model is not available for PIN diodes as SPICE
does not provide for a key PIN diode characteristic, carrier
lifetime.

Package Lead Code Identication, SOT-23 (Top View)

Features

• Diodes Optimized for:
Low Current Switching
Low Distortion Attenuating

• Power Limiting/Circuit Protection

• Surface Mount SOT-23 and SOT-323 Packages

Single and Dual Versions
Tape and Reel Options Available

• Low Failure in Time (FIT) Rate

[1]

• Lead-free

Note:

1. For more information see the Surface Mount PIN Reliability
Data Sheet.

Package Lead Code Identication, SOT-323 (Top View)

Absolute Maximum Ratings

[1]

TC = +25°C

Symbol Parameter Unit SOT-23 SOT-323

If Forward Current (1 µs Pulse) Amp 1 1

PIV Peak Inverse Voltage V 50

50

Tj Junction Temperature °C 150 150

T

Storage Temperature °C -65 to 150 -65 to 150

stg

θjc Thermal Resistance

Notes:

1. Operation in excess of any one of these conditions may result in permanent damage to the
device.

2. TC = +25°C, where TC is dened to be the temperature at the package pins where contact is
made to the circuit board.

[2]

°C/W 500 150

Electrical Specications TC = 25°C

Package Minimum Maximum Maximum
Part Number Marking Lead Breakdown Series Resistance Total Capacitance
HSMP- Code Code Conguration Voltage VBR (V) RS (Ω) CT (pF)

3820 F0 0 Single 50 0.6 0.8
3822 F2 2 Series
3823 F3 3 Common Anode
3824 F4 4 Common Cathode

Test Conditions VR = V

BR

Measure IF = 10 mA VR = 20 V
IR ≤ 10 µA

f = 100 MHz f = 1 MHz

High Frequency (Low Inductance, 500 MHz – 3 GHz) PIN Diodes

Minimum Maximum Typical Maximum Typical
Part Package Breakdown Series Total Total Total
Number Marking Lead Voltage Resistance Capacitance Capacitance Inductance
HSMP- Code Code Conguration VBR (V) RS (Ω) CT (pF) CT (pF) LT (nH)

4820 FA A Dual Anode 50 0.6 0.75 1.0 1.0

482B FA A Dual Anode

Test Conditions VR = VBR IF = 10 mA f = 1 MHz f = 1 MHz f = 500 MHz–
Measure VR = 20 V VR = 0 V 3 GHz
IR ≤ 10 µA

Typical Parameters at TC = 25°C

Part Number Series Resistance Carrier Lifetime Reverse Recovery Time Total Capacitance
HSMP- RS (Ω) τ (ns) Trr (ns) CT (pF)

382x 1.5 70 7 0.60 @ 20 V

Test Conditions f = 100 MHz IF = 10 mA VR = 10 V
IF = 10 mA IF = 20 mA
90% Recovery

2

Typical Parameters at TC = 25°C (unless otherwise noted), Single Diode

Figure 3. RF Resistance at 25C vs. Forward Bias Current.

100

10

1

0.1

RF RESISTANCE (OHMS)

IF – FORWARD BIAS CURRENT (mA)

0.01 0.1 1 10 100

1.4

1.2

1.0

0.8

0.6
0 10 20 30 40 50

VR – REVERSE VOLTAGE (V)

CAPACITANCE (pF)

Figure 4. Capacitance vs. Reverse Voltage.

120

115

110

105

100

95

90

85

1 10 30

IF – FORWARD BIAS CURRENT (mA)

Figure 5. 2nd Harmonic Input Intercept Point vs.
Forward Bias Current.

INPUT INTERCEPT POINT (dBm)

Diode Mounted as a
Series Attenuator in a
50 Ohm Microstrip and
Tested at 123 MHz

FORWARD CURRENT (mA)

Figure 2. Reverse Recovery Time vs. Forward Current
for Various Reverse Voltages.

T

rr

– REVERSE RECOVERY TIME (ns)

1

10

100

10 20 30

VR = 2V

VR = 5V

VR = 10V

100

10

1

0.1

0.01
0 0.2 0.4 0.6 0.8 1.0 1.2

I

F

– FORWARD CURRENT (mA)

VF – FORWARD VOLTAGE (mA)

Figure 1. Forward Current vs. Forward Voltage.

125C

25C

–50C

CW POWER IN (dBm)

Figure 6. Large Signal Transfer Curve of the
HSMP-482x Limiter.

CW POWER OUT (dBm)

0

30

25

20

15

10

5

0

4010

5

20 25 30 3515

Measured with external
bias return

1.0 GHz

1.5 GHz

RF COMMON

RF 1

BIAS 1

RF 2

BIAS 2

RF COMMON

BIAS BIAS

RF 2

RF 1

Typical Applications for Multiple Diode Products

Figure 7. Simple SPDT Switch, Using Only Positive Current.

3

Figure 8. High Isolation SPDT Switch, Dual Bias.

Typical Applications for Multiple Diode Products, continued

BIAS

RF COMMON

RF 1 RF 2

BIAS

RF COMMON

RF 2

RF 1

BIAS

Figure 9. Switch Using Both Positive and Negative Bias Current.

Figure 11. High Isolation SPST Switch (Repeat Cells as Required.

Figure 10. Very High Isolation SPDT Switch, Dual Bias.

Figure 12. Power Limiter Using HSMP-3822 Diode Pair.
See Application Note 1050 for details.

4

Typical Applications for HSMP-482x Low Inductance

50 OHM MICROSTRIP LINES

PAD CONNECTED TO

GROUND BY TWO

VIA HOLES

1 2

3

HSMP-482x

0.3 nH

0.3 nH

0.8 pF

1.5 nH 1.5 nH

Co-Planar Waveguide
Groundplane

Center Conductor

Groundplane

0.8 pF

0.75 nH

Series

Microstrip Series Connection for HSMP-482x Series

In order to take full advantage of the low inductance
of the HSMP-482x series when using them in series
applications, both lead 1 and lead 2 should be connected
together, as shown in Figure 14.

Figure 13. Internal Connections.

Figure 14. Circuit Layout.

Microstrip Shunt Connections for HSMP-482x Series

Figure 16. Equivalent Circuit.

Co-Planar Waveguide Shunt Connection for HSMP-482x Series

Co-Planar waveguide, with ground on the top side of
the printed circuit board, is shown in Figure 17. Since
it eliminates the need for via holes to ground, it oers
lower shunt parasitic inductance and higher maximum
attenuation when compared to a microstrip circuit. See
AN1050 for details.

In Figure 15, the center conductor of the microstrip line
is interrupted and leads 1 and 2 of the HSMP-482x diode
are placed across the resulting gap. This forces the 0.5
nH lead inductance of leads 1 and 2 to appear as part of
a low pass lter, reducing the shunt parasitic inductance
and increasing the maximum available attenuation.
The 0.3 nH of shunt inductance external to the diode
is created by the via holes, and is a good estimate for

0.032" thick material.

Figure 15. Circuit Layout, HSMP-482x Limiter.

Figure 17. Circuit Layout.

Figure 18. Equivalent Circuit.

5

Assembly Information

0.026

0.039

0.079

0.022

Dimensions in inches

0.039
1

0.039
1

0.079

2.0

0.031

0.8

Dimensions in

inches

mm

0.035

0.9

SOT-323 PCB Footprint

A recommended PCB pad layout for the miniature SOT­323 (SC-70) package is shown in Figure 19 (dimensions
are in inches). This layout provides ample allowance for
package placement by automated assembly equipment
without adding parasitics that could impair the
performance.

Figure 19. Recommended PCB Pad Layout
for Avago’s SC70 3L/SOT-323 Products.

SOT-23 PCB Footprint

Figure 20. Recommended PCB Pad Layout
for Avago’s SOT-23 Products.

6

SMT Assembly

25

Time

Temperature

Tp

T

L

tp

t

L

t 25° C to Peak

Ramp-up

ts

Ts

min

Ramp-down

Preheat

Critical Zone
T

L

to Tp

Ts

max

Reliable assembly of surface mount components is a
complex process that involves many material, process,
and equipment factors, including: method of heating
(e.g., IR or vapor phase reow, wave soldering, etc.) circuit
board material, conductor thickness and pattern, type of
solder alloy, and the thermal conductivity and thermal
mass of components. Components with a low mass, such
as the SOT-323/-23 package, will reach solder reow
temperatures faster than those with a greater mass.

Avago’s diodes have been qualied to the time­temperature prole shown in Figure 21. This prole is
representative of an IR reow type of surface mount
assembly process.

After ramping up from room temperature, the circuit
board with components attached to it (held in place with
solder paste) passes through one or more preheat zones.

The preheat zones increase the temperature of the
board and components to prevent thermal shock and
begin evaporating solvents from the solder paste. The
reow zone briey elevates the temperature suciently
to produce a reow of the solder.

The rates of change of temperature for the ramp-up and
cool-down zones are chosen to be low enough to not
cause deformation of the board or damage to components
due to thermal shock. The maximum temperature in the
reow zone (T

) should not exceed 260°C.

MAX

These parameters are typical for a surface mount
assembly process for Avago diodes. As a general
guideline, the circuit board and components should be
exposed only to the minimum temperatures and times
necessary to achieve a uniform reow of solder.

Figure 21. Surface Mount Assembly Prole.

Lead-Free Reow Prole Recommendation (IPC/JEDEC J-STD-020C)

Reow Parameter Lead-Free Assembly

Average ramp-up rate (Liquidus Temperature (T

Preheat Temperature Min (T

Temperature Max (T

Ts(max) to TL Ramp-up Rate 3°C/second max

Time maintained above: Temperature (TL) 217°C

Peak Temperature (TP) 260 +0/-5°C

Time within 5 °C of actual Peak temperature (tP) 20-40 seconds

Ramp-down Rate 6°C/second max

Time 25 °C to Peak Temperature 8 minutes max

Time (min to max) (tS) 60-180 seconds

Time (tL) 60-150 seconds

Note 1: All temperatures refer to topside of the package, measured on the package body surface

7

to Peak) 3°C/ second max

S(max)

) 150°C

S(min)

) 200°C

S(max)

Package Dimensions

e

B

e2

e1

E1

C

E

XXX

L

D

A

A1

Notes:
XXX-package marking
Drawings are not to scale

DIMENSIONS (mm)

MIN.

0.79

0.000

0.30

0.08

2.73

1.15

0.89

1.78

0.45

2.10

0.45

MAX.

1.20

0.100

0.54

0.20

3.13

1.50

1.02

2.04

0.60

2.70

0.69

SYMBOL

A

A1

B
C
D

E1

e
e1
e2

E

L

e

B

e1

E1

C

E

XXX

L

D

A

A1

Notes:
XXX-package marking
Drawings are not to scale

DIMENSIONS (mm)

MIN.

0.80

0.00

0.15

0.08

1.80

1.10

1.80

0.26

MAX.

1.00

0.10

0.40

0.25

2.25

1.40

2.40

0.46

SYMBOL

A
A1

B

C

D
E1

e
e1

E

L

1.30 typical

0.65 typical

Outline 23 (SOT-23)

Outline SOT-323 (SC-70)

Package Characteristics

Lead Material ....................................................... Copper (SOT-323); Alloy 42 (SOT-23)

Lead Finish ............................................................................ Tin 100% (Lead-free option)

Maximum Soldering Temperature ............................................... 260°C for 5 seconds

Minimum Lead Strength .............................................................................. 2 pounds pull

Typical Package Inductance ..........................................................................................2 nH

Typical Package Capacitance ................................................. 0.08 pF (opposite leads)

Ordering Information

Specify part number followed by option. For example:
HSMP - 382x - XXX

Bulk or Tape and Reel Option
Part Number; x = Lead Code
Surface Mount PIN

Option Descriptions

-BLKG = Bulk, 100 pcs. per antistatic bag

-TR1G = Tape and Reel, 3000 devices per 7" reel

-TR2G = Tape and Reel, 10,000 devices per 13" reel

Tape and Reeling conforms to Electronic Industries RS-481, “Taping of Surface
Mounted Components for Automated Placement.”

8

Device Orientation

USER
FEED
DIRECTION

COVER TAPE

CARRIER

TAPE

REEL

9° MAX

A

0

P

P

0

D

P

2

E

F

W

D

1

Ko

8° MAX

B

0

13.5° MAX

t1

DESCRIPTION SYMBOL SIZE (mm) SIZE (INCHES)

LENGTH
WIDTH
DEPTH
PITCH
BOTTOM HOLE DIAMETER

A

0

B

0

K

0

P
D

1

3.15 ± 0.10

2.77 ± 0.10

1.22 ± 0.10

4.00 ± 0.10

1.00 + 0.05

0.124 ± 0.004

0.109 ± 0.004

0.048 ± 0.004

0.157 ± 0.004

0.039 ± 0.002

CAVITY

DIAMETER
PITCH
POSITION

D
P

0

E

1.50 + 0.10

4.00 ± 0.10

1.75 ± 0.10

0.059 + 0.004

0.157 ± 0.004

0.069 ± 0.004

PERFORATION

WIDTH
THICKNESS

Wt18.00 + 0.30 – 0.10

0.229 ± 0.013

0.315 + 0.012 – 0.004

0.009 ± 0.0005

CARRIER TAPE

CAVITY TO PERFORATION
(WIDTH DIRECTION)

CAVITY TO PERFORATION
(LENGTH DIRECTION)

F

P

2

3.50 ± 0.05

2.00 ± 0.05

0.138 ± 0.002

0.079 ± 0.002

DISTANCE
BETWEEN
CENTERLINE

Note: "AB" represents package marking code.
"C" represents date code.

END VIE

W

8 mm

4 mm

TOP VIEW

ABC ABC ABC ABC

For Outlines SOT-23/323

Tape Dimensions and Product Orientation
For Outline SOT-23

9

P

P

0

P

2

F

W

C

D

1

D

E

A

0

An

t1 (CARRIER TAPE THICKNESS) Tt (COVER TAPE THICKNESS)

An

B

0

K

0

DESCRIPTION SYMBOL SIZE (mm) SIZE (INCHES)

LENGTH
WIDTH
DEPTH
PITCH
BOTTOM HOLE DIAMETER

A

0

B

0

K

0

P
D

1

2.40 ± 0.10

2.40 ± 0.10

1.20 ± 0.10

4.00 ± 0.10

1.00 + 0.25

0.094 ± 0.004

0.094 ± 0.004

0.047 ± 0.004

0.157 ± 0.004

0.039 + 0.010

CAVITY

DIAMETER
PITCH
POSITION

D
P

0

E

1.55 ± 0.05

4.00 ± 0.10

1.75 ± 0.10

0.061 ± 0.002

0.157 ± 0.004

0.069 ± 0.004

PERFORATION

WIDTH
THICKNESS

W
t

1

8.00 ± 0.30

0.254 ± 0.02

0.315 ± 0.012

0.0100 ± 0.0008

CARRIER TAPE

CAVITY TO PERFORATION
(WIDTH DIRECTION)

CAVITY TO PERFORATION
(LENGTH DIRECTION)

F

P

2

3.50 ± 0.05

2.00 ± 0.05

0.138 ± 0.002

0.079 ± 0.002

DISTANCE

FOR SOT-323 (SC70-3 LEAD) An 8°C MAX

FOR SOT-363 (SC70-6 LEAD) 10°C MAX

ANGLE

WIDTH
TAPE THICKNESS

C
T

t

5.4 ± 0.10

0.062 ± 0.001

0.205 ± 0.004

0.0025 ± 0.00004

COVER TAPE

Tape Dimensions and Product Orientation
For Outline SOT-323

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Data subject to change. Copyright © 2005-2009 Avago Technologies. All rights reserved. Obsoletes 5989-4026EN
AV02-1395EN - June 2, 2009