Datasheet HRF3205 Datasheet (Fairchild Semiconductor)

HRF3205, HRF3205S

Data Sheet December 2001

100A, 55V, 0.008 Ohm, N-Channel, Power
MOSFETs

These are N-Channel enhancement mode silicon gate
power field effect transistors. They are advanced power
MOSFETs designed, tested, and guaranteed to withstand a
specified level of energy in the breakdown avalanche mode
of operation. All of these power MOSFETs are designed for
applications such as switc hi ng r egulators, s w itc hing
converters, motor drivers, relay drivers, and drivers for high
power bipolar switching transistors requiring high speed and
low gate drive power. These types can be operated directly
from integrated circuits.

NOTE: Calculated continuous current based on maximum
allowable junction temperature. Package limited to 75A
continuous, see Figure 9.

Ordering Information

PART NUMBER PACKAGE BRAND

HRF3205 TO-220AB HRF3205
HRF3205S TO-263AB HRF3205S

NOTE: When ordering, use the entir e part number. Add the suffix T
to obtain the TO-263AB variant in tape and reel, e.g., HRF3205ST.

Features

• 100A, 55V (See Note)

• Low On-Resistance, r

• Temperature Compensating PSPICE

DS(ON)

= 0.008Ω

®

Model

• Thermal Impedance SPICE Model

• UIS Rating Curve

• Related Literature

- TB334, “Guidelines f or Solde ring Surface Mount
Components to PC Boards”

Symbol

D

G

S

Packaging

DRAIN

(FLANGE)

JEDEC TO-220AB JEDEC TO-263AB

SOURCE
DRAIN

GATE

GATE

SOURCE

DRAIN
(FLANGE)

©2001 Fairchild Semiconductor Corpo ration HRF3205, HRF3205S Rev. B

D

HRF3205, HRF3205S

Absolute Maximum Ratings

Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

Drain to Gate Voltage (R

Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

= 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

GS

TC = 25oC, Unless Othewise Specified

DSS

DGR

GS

55 V
55 V

±20V V

Drain Current

Continuous. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I

Pulsed Drain Current (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I

Pulsed Avalanche Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P

Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T

, T

J

STG

D

DM

AS

D

100
390

Figure 10

175

1.17

-55 to 175

Maximum Temperature for Soldering

Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T

Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T

CAUTION: Stresses above those listed in “A bsolute Maximu m Rating s” may cause per manent d amage to t he device. This is a str ess on ly rating and operation o f the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

L

pkg

300
260

A
A

W

W/oC

o

C

o

C

o

C

NOTE:

= 25oC to 150oC.

1. T

J

Electrical Specifications

TC = 25oC, Unless Otherwise Specified

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Drain to Source Breakdown Voltage BV
Gate to Source Threshold Voltage V

GS(TH)VGS

Zero Gate Voltage Drain Current I

Gate to Source Leakage Current I
Breakdown Voltage Temperature

∆V

(BR)DSS

Coefficient
Drain to Source On Resistance r
Turn-On Delay Time t

DS(ON)ID

d(ON)

Rise Time t
Turn-Off Delay Time t

d(OFF)

Fall Time t
Total Gate Charge Q
Gate to Source Charge Q
Gate to Drain “Miller” Charge Q
Input Capacitance C
Output Capacitance C
Reverse Transfer Capacitance C
Internal Source Inductance L

DSSID

DSS

GSS

∆T

J

r

f

g

gs

gd

ISS
OSS
RSS

S

= 250µA, VGS = 0V 55 - - V

= VDS, ID = 250µA2-4V
VDS = 55V, VGS = 0V - - 25 µA
V

= 44V, VGS = 0V, TC = 150oC - - 250 µA

DS

VGS = ±20V - - 100 nA

/

Reference to 25oC, ID = 250µA - 0.057 - V

= 59A, VGS = 10V (Figure 4) - 0.0065 0.008 Ω

VDD = 28V, ID ≅ 59A,

= 0.47Ω, VGS = 10V,

R

L

= 2.5Ω

R

GS

-14 - ns

- 100 - ns

-43 - ns

-70 - ns

VDD = 44V, ID ≅ 59A,

= 10V, I

V

GS

(Figure 6)

g(REF)

= 3mA

- - 170 nC

- - 32 nC

- - 74 nC

VDS = 25V, VGS = 0V,
f = 1MHz (Figure 5)

- 4000 - pF

- 1300 - pF

- 480 - pF

Measured From the Contact
Screw on Tab to Center of Die

Measured From the Drain
Lead, 6mm (0.25in) From

Modified MOSFET
Symbol Showing the
Internal Devices In­ductances

-7.5 - nH

Package to Center of Die

L

Internal Drain Inductance L

Thermal Resistance Junction to Case R
Thermal Resistance Junction to

Ambient

Measured From the Source

D

Lead, 6mm (0.25in) From Head­er to Source Bonding Pad

θJC

R

θJA

TO-220 - - 62

G

TO-263 (PCB Mount, Steady State) - - 40

D

L

S

S

-4.5 - nH

- - 0.85

o
o
o

C/W
C/W
C/W

©2001 Fairchild Semiconductor Corpo ration HRF3205, HRF3205S Rev. B

Source to Drain Diode Specifications

0

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Continuous Source to Drain Current I

Pulsed Source to Drain Current (Note 2) I

HRF3205, HRF3205S

SD

SDM

MOSFET
Symbol Showing
The Integral
Reverse P-N
Junction Diode

D

- - 100
(Note 1

A

- - 390 A

G

S

Source to Drain Diode Voltage V
Reverse Recovery Time t
Reverse Recovered Charge Q

SD

RR

ISD = 59A (Note 4) - - 1.3 V
ISD = 59A, dISD/dt = 100A/µs (Note 4) - 110 170 ns

rr

ISD = 59A, dISD/dt = 100A/µs (Note 4) - 450 680 nC

NOTE:

2. Repetitive rating; pulse width limited by maximum junction temperature (See Figure 11)

Typical Performance Curves

1000

V

IN DECENDING ORDER

GS

15V

10V

8.0V

7.0V

6.0V

5.5V

5.0V

100

4.5V

, DRAIN TO SOURCE CURRENT (A)

D

I

10

0.1 1.0 10 10
V

, DRAIN TO SOURCE VOLTAGE (V)

DS

20µs PULSE WIDTH

T

= 25oC

C

FIGURE 1. OUTPUT CHARACTERISTICS FIGURE 2. OUTPUT CHARACTERISTICS

1000

100

, DRAIN TO SOURCE CURRENT (A)

D

I

10

0.1 1 10 100

IN DECENDING ORDER

V

GS

15V
10V

8.0V

7.0V

6.0V

5.5V

5.0V

4.5V

, DRAIN TO SOURCE VOLTAGE (V)

V

DS

20µs PULSE WIDTH

= 175oC

T

C

1000

TJ = 25oC

100

10

, DRAIN TO SOURCE CURRENT(A)

D

I

1

34.567.59

TJ = 175oC

= 25V

V

DS

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX

VGS, GATE TO SOURCE VOLTAGE (V)

2.5
ID = 98A, VGS = 10V

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX

2.0

1.5

1.0

ON RESISTANCE

0.5

NORMALIZED DRAIN TO SOURCE

0

-80 -40 0 40 80 120 160 200
TJ, JUNCTION TEMPERATURE (oC)

FIGURE 3. TRANSFER CHARACTERISTICS FIGURE 4. NORMALIZED DRAIN TO SOURCE ON

RESISTANCE vs JUNCTION TEMPERATURE

©2001 Fairchild Semiconductor Corpo ration HRF3205, HRF3205S Rev. B

HRF3205, HRF3205S

OSS

(Continued)

20

ID = 59A

16

12

8

4

, GATE TO SOURCE VOLTAGE (V)

GS

V

0

0 36 72 108 144 180

Qg, GATE CHARGE (nC)

V

DS

VDS = 28V

= 11V

VDS = 44V

Typical Performance Curves

8000

V

= 0V, f = 1MHz

GS

= CGS + C

C

C, CAPACITANCE (pF)

7000

6000

5000

4000

3000

2000

1000

ISS

C

= C

RSS

C

≈ CDS + C

OSS

0

1

GD

GD

GS

C

ISS

C

C

RSS

VDS, DRAIN TO SOURCE VOLTAGE (V)

10 100

FIGURE 5. CAPACITANCE vs DRAIN TO SOURCE VOLTA GE FIGURE 6. GATE CHARGE WA VEFORMS FOR CONSTANT

GATE CURRENT

1000

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX

TJ = 175oC

100

1000

100

10µs

100µs

10

, REVERSE DRAIN CURRENT(A)

SD

I

1

0.5 1.0 1.5 2.0

TJ = 25oC

VSD, SOURCE TO DRAIN VOLTAGE (V)

OPERATION IN THIS
AREA MAY BE
LIMITED BY r

10

, DRAIN CURRENT (A)

D

I

1

110100

DS(ON)

V

DSS(MAX)

, DRAIN TO SOURCE VOLTAGE (V)

V

DS

= 55V

1ms

10ms

FIGURE 7. SOURCE TO DRAIN DIODE FORWARD VOLTAGE FIGURE 8. FORWARD BIAS SAFE OPERATING AREA

120

90

60

, DRAIN CURRENT (A)

30

D

I

CURRENT LIMITED
BY PACKAGE

0

25 50 75 100 125 150 175

TC, CASE TEMPERATURE (oC)

1000

If R = 0
tAV = (L)(IAS)/(1.3*RATED BV

If R ≠ 0
t

= (L/R)ln[(IAS*R)/(1.3*RATED BV

AV

100

STARTING TJ = 150oC

, AVALANCHE CURRENT (A)

AS

I

10

- VDD)

DSS

DSS

STARTING TJ = 25oC

0.1

tAV, TIME IN AVALANCHE (ms)

1101000.01

- VDD) +1]

FIGURE 9. MAXIMUM CONTINUOUS DRAIN CURRENT vs

CASE TEMPERATURE

©2001 Fairchild Semiconductor Corpo ration HRF3205, HRF3205S Rev. B

FIGURE 10. UNCLAMPED INDUCTIVE SWITCHING

CAPABILITY

HRF3205, HRF3205S

Typical Performance Curves

10

DUTY CYCLE - DESCENDING ORDER

0.5

0.2

0.1

0.05

0.02

1

0.01

, NORMALIZED

JC

0.1

θ

Z

THERMAL IMPEDANCE

0.01

-5

10

SINGLE PULSE

-4

10

FIGURE 11. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE

Test Circuits and Waveforms

TO OBTAIN

VARY t

P

REQUIRED PEAK I

V

GS

AS

R

G

(Continued)

10

V

DS

L

DUT

-3

-2

10

t, RECTANGULAR PULSE DURATION (s)

+

V

DD

-

NOTES:
DUTY FACTOR: D = t

PEAK TJ = PDM x Z

-1

10

t

P

I

AS

BV

10

P

θ

DSS

DM

0

JC

1/t2

x R

t

1

t

2

+ T

JC

C

θ

1

10

V

DS

V

DD

0V

P

I

AS

0.01Ω

0

t

AV

t

FIGURE 12. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 13. UNCLAMPED ENERGY WAVEFORMS

V

DD

Q

g(TOT)

Q

gd

Q

gs

V

DS

V

GS

0

I

G(REF)

I

G(REF)

V

DS

R

L

V

GS

+

V

DD

-

DUT

0

FIGURE 14. GATE CHARGE TEST CIRCUIT FIGURE 15. GATE CHARGE WAVEFORM

©2001 Fairchild Semiconductor Corpo ration HRF3205, HRF3205S Rev. B

HRF3205, HRF3205S

Test Circuits and Waveforms

V

DS

V

GS

R

GS

V

GS

FIGURE 16. SWITCHING TIME TEST CIRCUIT FIGURE 17. RESISTIVE SWITCHING WAVEFORMS

(Continued)

R

L

DUT

t

ON

t

d(ON)

t

V

DS

+

V

DD

-

0

V

GS

10%

0

r

90%

10%

50%

PULSE WIDTH

t

d(OFF)

90%

t

OFF

50%

t

f

90%

10%

©2001 Fairchild Semiconductor Corpo ration HRF3205, HRF3205S Rev. B

PSPICE Electrical Model

SUBCKT HRF3205P3 2 1 3 ; rev 7/ 25/97

CA 12 8 4.9e-9
CB 15 14 4.9e-9
CIN 6 8 3.45e-9

DBODY 7 5 DBODYMOD
DBREAK 5 11 D B REAK MOD
DPLCAP 10 5 DPLCAPMOD

EBREAK 11 7 17 18 57
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8 1
EVTEMP 20 6 18 22 1

GATE

IT 8 17 1
LDRAIN 2 5 1e-9

LGATE 1 9 2.6e-9
LSOURCE 3 7 1.1e-9
K1 LGATE LSOURCE 0.0085

MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD

RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 3.5e-4
RGATE 9 20 0.36
RLDRAIN 2 5 10
RLGATE 1 9 26
RLSOURCE 3 7 11
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 4.5e-3
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTE MPMOD 1

LGATE

1

RLGATE

RGATE

9

CA

HRF3205, HRF3205S

DPLCAP

10

RSLC2

­6

ESG

8

EVTHRES

+

+

-

EVTEMP
+

-

18
22

20

S1A

12

13

8

S1B

EGS EDS

13

19

8

6

CIN

S2A

14
13

+

+

-

-

15

S2B

CB

+

6
8

5
8

-

5

RSLC1

51

+

5

51

­50

RDRAIN

21

MSTRO

14

ESLC

16

8

MMED

DBREAK

11

EBREAK

MWEAK

RSOURCE

RBREAK

17 18

IT

8

RVTHRES

LDRAIN

RLDRAIN

+

17
18

-

DBODY

LSOURCE

7

RLSOURCE

RVTEMP
19

­VBAT

+

22

DRAIN

2

SOURCE

3

S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD

VBAT 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*550),3))}
.MODEL DBODYMOD D (IS = 4.25e-12 RS = 1.8e-3 TRS1 = 2.75e-3 TRS2 = 5e-6 CJO = 5.95e-9 TT = 4e-7 M = 0.55)

.MODEL DBREAKMOD D (RS = 0.0 6IKF = 30 TRS1 = -3e- 3TRS2 = 3e-6)
.MODEL DPLCAPMOD D (CJO = 4.45e- 9IS = 1e-3 0N = 1 M = 0.88 VJ = 1.45)
.MODEL MMEDMO D NMOS (VTO = 2. 93 KP = 9.5 IS = 1e-30 N = 10 TOX = 1 L = 1 u W = 1u RG = 1)
.MODEL MSTR OMOD NMOS (VTO = 3.23 KP = 150 IS = 1e-3 0 N = 1 0 T OX = 1 L = 1u W = 1u)
.MODEL MWEAKMOD NMOS (VTO = 2.35 KP = 0.02 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 10)
.MODEL RBREAKMOD RES (TC1 = 8e- 4TC2 = 4e-6)
.MODEL RDRAINMOD RES (TC1 = 8e-2 TC2 = 5e-6)
.MODEL RSLCMOD RES (TC1 = 1e-4 TC2 = 1.05 e-6)
.MODEL RSOURCEMOD RES (TC1 = 1e-4 TC2 = 1.5e-5)
.MODEL RVTHRESMOD RES (TC1 = -2.3e-3 TC2 = -1.2e-5)
.MODEL RVTEMPMOD RES (TC1 = -2.2e- 3TC2 = -7e-6)

.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -9 VOFF= -4)
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -4 VOFF= -9)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 0 VOFF= 2.5)
.MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VO N = 2.5 VOFF= 0)

.ENDS

NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Powe r El ectronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.

©2001 Fairchild Semiconductor Corpo ration HRF3205, HRF3205S Rev. B

HRF3205, HRF3205S

SPICE Thermal Model

REV 25 July 97

HRF3205

CTHERM1 7 6 2.53e-5
CTHERM2 6 5 1.38e-3
CTHERM3 5 4 7.00e-3
CTHERM4 4 3 2.50e-2
CTHERM5 3 2 1.33e-1
CTHERM6 2 1 5.75e-1

RTHERM1 7 6 7.78e-4
RTHERM2 6 5 8.55e-3
RTHERM3 5 4 3.00e-2
RTHERM4 4 3 1.42e-1
RTHERM5 3 2 2.65e-1
RTHERM6 2 1 2.33e-1

RTHERM1

RTHERM2

RTHERM3

RTHERM4

JUNCTION

7

CTHERM1

6

CTHERM2

5

CTHERM3

4

CTHERM4

RTHERM5

RTHERM6

3

CTHERM5

2

CTHERM6

1

CASE

©2001 Fairchild Semiconductor Corpo ration HRF3205, HRF3205S Rev. B

TRADEMARKS

The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is
not intended to be an exhaustive list of all such trademarks.

ACEx™
Bottomless™
CoolFET™
CROSSVOLT™
DenseTrench™
DOME™
EcoSPARK™
E2CMOS
EnSigna

TM

TM

FACT™
FACT Quiet Series™

STAR*POWER is used under license

FAST
FASTr™
FRFET™
GlobalOptoisolator™
GTO™
HiSeC™
ISOPLANAR™
LittleFET™
MicroFET™
MicroPak™
MICROWIRE™



OPTOLOGIC™
OPTOPLANAR™
PACMAN™
POP™
Power247™
PowerTrench



QFET™
QS™
QT Optoelectronics™
Quiet Series™
SILENT SWITCHER

SMART START™
STAR*POWER™
Stealth™
SuperSOT™-3
SuperSOT™-6
SuperSOT™-8
SyncFET™
TinyLogic™
TruTranslation™
UHC™



UltraFET

VCX™



DISCLAIMER

FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER
NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD
DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT
OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT
RIGHTS, NOR THE RIGHTS OF OTHERS.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:

1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, or (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in significant injury to the
user.

PRODUCT STATUS DEFINITIONS
Definition of Terms

Datasheet Identification Product Status Definition

Advance Information

Preliminary

No Identification Needed

Formative or
In Design

First Production

Full Production

2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or

effectiveness.

This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.

This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.

This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.

Obsolete

Not In Production

This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.

Rev. H4