Datasheet HPLU3103 Datasheet (Intersil Corporation)

HPLR3103, HPLU3103

Data Sheet July 1999 File Number

52A, 30V, 0.019 Ohm, N-Channel Logic
Level, Power MOSFETs

These are N-Channel enhancement mode silicon gate
power field effect transistors. They are advanced power
MOSFETs designed, tested, and guaranteed to withstand a
specified level of energy in the breakdown avalanche mode
of operation. All of these power MOSFETs are designed for
applications such as switching regulators, switching
converters, motor drivers, relay drivers, and drivers for high
power bipolar switching transistors requiring high speed and
low gate drive power. These types can be operated directly
from integrated circuits.

Ordering Information

PART NUMBER PACKAGE BRAND

HPLU3103 TO-251AA HP3103
HPLR3103 TO-252AA HP3103

NOTE: Whenordering, use the entire part number.AddthesuffixT
to obtain the TO-252AA variant in tape and reel, e.g., HPLR3103T.

4501.2

Features

• Logic Level Gate Drive

• 52A†, 30V

• Low On-Resistance, r

DS(ON)

= 0.019Ω

• UIS Rating Curve

• Related Literature

- TB334, “Guidelines for Soldering Surface Mount
Components to PC Boards”

Calculated continuous current based on maximum allowable junction

†

temperature. Package limited to 20A continuous, see Figure 9.

Symbol

D

G

S

Packaging

(FLANGE)

JEDEC TO-251AA JEDEC TO-252AA

DRAIN

SOURCE

DRAIN

GATE

GATE
SOURCE

DRAIN

(FLANGE)

6-3

CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.

http://www.intersil.com or 407-727-9207

| Copyright © Intersil Corporation 1999

HPLR3103, HPLU3103

Absolute Maximum Ratings T

= 25oC, Unless Othewise Specified

C

HPLR3103, HPLU3103 UNITS

Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V

Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I

Pulsed Drain Current (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I

Single Pulse Avalanche Energy (Note 4). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P

DSS

DGR

GS

D

DM

AS

D

Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, T

STG

Maximum Temperature for Soldering

Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .T

Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationofthe
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

L

pkg

30 V
30 V

±16V V

52
390
240 mj

89

0.71

-55 to 150

300
260

A
A

W

W/oC

o

C

o

C

o

C

NOTE:

1. TJ = 25oC to 125oC.

Electrical Specifications T

= 25oC, Unless Otherwise Specified

C

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Drain to Source Breakdown Voltage BV
Gate to Source Threshold Voltage V
Zero Gate Voltage Drain Current I

DSSID

GS(TH)VGS

DSS

= 250µA, VGS = 0V 30 - - V

= VDS, ID = 250µA1--V
VDS = 30V, VGS = 0V - - 25 µA
VDS = 24V, VGS = 0V, TC = 125oC - - 250 µA

Gate to Source Leakage Current I
Breakdown Voltage Temperature

Coefficient
Drain to Source On Resistance

∆V

(BR)DSS

/∆T

r

DS(ON)ID

(Note 3)

Turn-On Delay Time t

d(ON)

Rise Time t
Turn-Off Delay Time (Note 3) t

d(OFF)

Fall Time t
Total Gate Charge Q
Gate to Source Charge Q
Gate to Drain “Miller” Charge Q
Input Capacitance C
Output Capacitance C
Reverse Transfer Capacitance C
Internal Source Inductance L

Internal Drain Inductance L

GSS

OSS
RSS

VGS = ±16V - - 100 nA
Reference to 25oC, ID = 1mA - 0.037 - V

J

= 28A, VGS = 10V - - 0.019 Ω
ID = 23A, VGS = 4.5V - - 0.024 Ω
VDD= 15V, ID≅34A, RL= 0.441Ω,VGS=4.5V,

RGS =3.4Ω, I

r

g(REF)

= 3mA

-9 - ns

- 210 - ns

-20 - ns

f

VDD = 24V

g

ID≅ 34A,

gs

VGS = 4.5V
(Figure 6)

gd

VDS = 25V, VGS = 0V,

ISS

f = 1MHz (Figure 5)

-54 - ns

- - 50 nC

- - 14 nC

- - 28 nC

- 1600 - pF

- 640 - pF

- 320 - pF

Measured From the

S

SourceLead,6mm(0.25in)
FromPackage toCenter of
Die

Measured From the Drain-

D

Lead, 6mm (0.25in) From

ModifiedMOSFET
Symbol Showing
the Internal Devic­es Inductances

D

L

D

- 7.5 - nH

- 4.5 - nH

Package to Center of Die

G

L

S

S

6-4

HPLR3103, HPLU3103

Electrical Specifications T

= 25oC, Unless Otherwise Specified

C

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Thermal Resistance Junction to Case R
Thermal Resistance Junction to Ambient R

θJC
θJA

(PCB Mount Steady State) - - 50

Source to Drain Diode Specifications

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Continuous Source to Drain Current I

Pulsed Source to Drain Current (Note 2) I

Source to Drain Diode Voltage (Note 3) V

SD

SDM

SD

Reverse Recovery Time (Note 3) t
Reverse Recovered Charge (Note 3) Q

RR

NOTES:

2. Repetitive rating; pulse width limited by maximum junction temperature (See Figure 11).

3. Pulse width ≤ 300µs; duty cycle ≤ 2%.

4. VDD = 15V, starting TJ= 25oC, L = 300µH, RG= 25Ω, peak IAS = 34A, (Figure 10).

MOSFET
Symbol Showing
The Integral
Reverse P-N
Junction Diode

ISD = 28A - - 1.3 V
ISD = 34A, dISD/dt = 100A/µs - 81 120 ns

rr

ISD = 34A, dISD/dt = 100A/µs - 210 310 nC

- - 1.4

- - 110

D

- - 52(Note1)A

o

C/W

o

C/W

o

C/W

- - 220 A

G

S

Typical Performance Curves

1000

VGSIN DECENDING ORDER

15V

12V

10V

8.0V

100

6.0V

4.0V

3.0V

2.5V

10

, DRAIN TO SOURCE CURRENT (A)

D

I

1

0.1 1.0 10 100
, DRAIN TO SOURCE VOLTAGE (V)

V

DS

FIGURE 1. OUTPUT CHARACTERISTICS FIGURE 2. OUTPUT CHARACTERISTICS

20µs PULSE WIDTH

= 25oC

T

C

1000

V

IN DECENDING ORDER

GS

15V
12V
10V

8.0V

100

6.0V

4.0V

3.0V

2.5V

10

, DRAIN TO SOURCE CURRENT (A)

D

I

1

0.1 1 10 100
, DRAIN TO SOURCE VOLTAGE (V)

V

DS

20µs PULSE WIDTH
T

= 150oC

C

6-5

HPLR3103, HPLU3103

Typical Performance Curves

1000

100

10

, DRAIN TO SOURCE CURRENT(A)

D

I

3200

2800

2400

= 15V

V

DS

20µs PULSE WIDTH

TJ = 25oC

TJ = 150oC

1

24

3

V

, GATE TO SOURCE VOLTAGE (V)

GS

5

6

FIGURE 3. TRANSFER CHARACTERISTICS FIGURE 4. NORMALIZED DRAIN TOSOURCE ON

VGS= 0V, f = 1MHz
C

= CGS + C
C
C

ISS
RSS
OSS

= C

≈ C

GD

DS

+ C

GD

GS

(Continued)

79

8

2.5

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX

= 46A, VGS = 10V

I

D

2.0

1.5

1.0

ON RESISTANCE

0.5

NORMALIZED DRAIN TO SOURCE

0

-80 -40 0 40 80 120 160 200
TJ, JUNCTION TEMPERATURE (oC)

RESISTANCE vs JUNCTION TEMPERATURE

20

ID = 34A

16

VDS = 15V

VDS = 24V

2000

1600

1200

800

C, CAPACITANCE (pF)

400

0

1

C

ISS

C

OSS

C

RSS

VDS, DRAIN TO SOURCE VOLTAGE (V)

10 100

12

8

4

, GATE TO SOURCE VOLTAGE (V)

GS

V

0

0

10 20 30 40

, TOTAL GATE CHARGE (nC)

Q

G

FIGURE 5. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE FIGURE 6. GATECHARGE WAVEFORMS FOR CONSTANT

GATE CURRENT

1000

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX

= 46A, VGS = 10V

I

D

100

TJ = 175oC

TJ = 25oC

, REVERSE DRAIN CURRENT(A)

SD

I

10

0.4 1.2 2.0 2.8

0.8
, SOURCE TO DRAIN VOLTAGE (V)

V

SD

1.6

2.4

1000

10µs

100

100µs

OPERATION IN THIS
AREA MAY BE

10

LIMITED BY r

, DRAIN CURRENT (A)

D

I

1

1 10 100

DS(ON)

V

MAX = 30V

DSS

V

, DRAIN TO SOURCE VOLTAGE (V)

DS

1ms

10ms

FIGURE 7. SOURCE TO DRAIN DIODE FORWARD VOLTAGE FIGURE 8. FORWARD BIAS SAFE OPERATING AREA

6-6

HPLR3103, HPLU3103

Typical Performance Curves

60

45

30

, DRAIN CURRENT (A)

15

D

I

0

25 50

75

TC, CASE TEMPERATURE (oC)

(Continued)

100 125 150

FIGURE 9. MAXIMUM CONTINUOUS DRAIN CURRENT vs

CASE TEMPERATURE

2

DUTY CYCLE - DESCENDING ORDER

0.5

1

0.2

0.1

0.05

0.02

0.01

0.1

, NORMALIZED

JC

θ

Z

THERMAL IMPEDANCE

0.01

-5

10

SINGLE PULSE

-4

10

1000

If R = 0
tAV = (L)(IAS)/(1.3*RATED IASV

If R ≠ 0
t

AV

100

10

, AVALANCHE CURRENT (A)

AS

I

1

0.001

FIGURE 10. UNCLAMPED INDUCTIVE SWITCHING

-3

10

t, RECTANGULAR PULSE DURATION (s)

-2

10

DSS

= (L/R)ln[(IAS*R)/(1.3*RATED BV

EASPOINT

STARTING TJ = 150oC

0.01

0.1

tAV, TIME IN AVALANCHE (ms)

CAPABILITY

P

DM

NOTES:
DUTY FACTOR: D = t
PEAK TJ = PDM x Z

-1

10

θ

0

10

- VDD)

- VDD) +1]

DSS

STARTING TJ = 25oC

1 10 100

t

1

t

2

1/t2

x R

JC

+ T

JC

C

θ

1

10

FIGURE 11. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE

Test Circuits and Waveforms

V

DS

BV

DSS

L

VARY t

TO OBTAIN

P

REQUIRED PEAK I

V

GS

t

0V

P

AS

R

G

DUT

I

AS

0.01Ω

+

V

DD

-

0

FIGURE 12. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 13. UNCLAMPED ENERGY WAVEFORMS

6-7

t

P

I

AS

t

AV

V

DS

V

DD

HPLR3103, HPLU3103

Test Circuits and Waveforms

V

DS

V

GS

I

G(REF)

FIGURE 14. GATE CHARGE TEST CIRCUIT FIGURE 15. GATE CHARGE WAVEFORMS

V

(Continued)

R

L

DUT

DS

R

L

V

DD

Q

g(TOT)

Q

gd

Q

gs

+

V

DD

-

0

I

G(REF)

0

t

ON

t

d(ON)

t

V

DS

90%

r

V

DS

V

GS

t

d(OFF)

t

OFF

t

f

90%

V

GS

R

GS

V

GS

DUT

+

V

DD

-

0

V

GS

10%

0

10%

50%

PULSE WIDTH

10%

90%

50%

FIGURE 16. SWITCHING TIME TEST CIRCUIT FIGURE 17. RESISTIVE SWITCHING WAVEFORMS

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.

Intersil semiconductor products are sold by description only. Intersil Corporationreserves the right to make changes in circuit design and/or specifications at any time with­out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see web site http://www.intersil.com

Sales Office Headquarters

NORTH AMERICA

Intersil Corporation
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: [phone]
FAX: [phone]

EUROPE

Intersil SA
Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
TEL: [phone]
FAX: [phone]

ASIA

Intersil (Taiwan) Ltd.
7F-6, No. 101 Fu Hsing North Road
Taipei, Taiwan
Republic of China
TEL: [phone]
FAX: [phone]

6-8