Datasheet HN58V65AFP-10, HN58V65AP-10, HN58V65AT-10, HN58V66AFP-10, HN58V66AP-10 Datasheet (HIT)

HN58V65A Series HN58V66A Series

64 k EEPROM (8-kword × 8-bit)

Ready/Busy function, RES function (HN58V66A)

ADE-203-539B (Z)

Rev. 2.0

Nov. 1997

Description

The Hitachi HN58V65A series and HN58V66A series are a electrically erasable and programmable EEPROM’s organized as 8192-word × 8-bit. They have realized high speed, low power consumption and high relisbility by employing advanced MNOS memory technology and CMOS process and circuitry technology. They also have a 64-byte page programming function to make their write operations faster.

Features

• Single supply: 2.7 to 5.5 V

• Access time:  100 ns (max) at 2.7 V ≤ VCC < 4.5 V  70 ns (max) at 4.5 V ≤ VCC ≤ 5.5 V

• Power dissipation:  Active: 20 mW/MHz (typ)  Standby: 110 µW (max)

• On-chip latches: address, data, CE, OE, WE

• Automatic byte write: 10 ms (max)

• Automatic page write (64 bytes): 10 ms (max)

• Ready/Busy

• Data polling and Toggle bit

• Data protection circuit on power on/off

• Conforms to JEDEC byte-wide standard

• Reliable CMOS with MNOS cell technology

HN58V65A Series, HN58V66A Series

Features (cont)

• 105 erase/write cycles (in page mode)

• 10 years data retention

• Software data protection

• Write protection by RES pin (only the HN58V66A series)

• Industrial versions (Temperatur range: –20 to 85˚C and –40 to 85˚C) are also available.

Ordering Information

Access time

Type No. 2.7 V ≤ V

HN58V65AP-10 100 ns 70 ns 600 mil 28-pin plastic DIP (DP-28) HN58V66AP-10 100 ns 70 ns HN58V65AFP-10 100 ns 70 ns 400 mil 28-pin plastic SOP (FP-28D) HN58V66AFP-10 100 ns 70 ns HN58V65AT-10 100 ns 70 ns 28-pin plastic TSOP(TFP-28DB) HN58V66AT-10 100 ns 70 ns

< 4.5 V 4.5 V ≤ VCC ≤ 5.5 V Package

CC

Pin Arrangement

HN58V65AP Series

HN58V65AFP Series

RDY/Busy

A12 A7 A6 A5 A4 A3 A2 A1

A0 I/O0 I/O1 I/O2

V

SS

1 2 3 4 5 6 7 8 9 10 11 12 13 14

(Top view)

28 27 26 25 24 23 22 21 20 19 18 17 16 15

V

CC

WE

NC A8 A9 A11

OE

A10

CE

I/O7 I/O6 I/O5 I/O4 I/O3

RDY/Busy

A12 A7 A6 A5 A4 A3 A2 A1

A0 I/O0 I/O1 I/O2

V

SS

HN58V66AP Series

HN58V66AFP Series

1 2 3 4 5 6 7 8 9 10 11 12 13 14

(Top view)

28 27 26 25 24 23 22 21 20 19 18 17 16 15

V

CC

WE RES

A8 A9 A11

OE

A10

CE

I/O7 I/O6 I/O5 I/O4 I/O3

Pin Arrangement (cont)

SS

15 16 17 18 19 20 21 22 23 24 25 26 27 28

A2 A1 A0 I/O0 I/O1 I/O2 V I/O3 I/O4 I/O5 I/O6 I/O7 CE A10

HN58V65A Series, HN58V66A Series

HN58V65AT Series

(Top view)

HN58V66AT Series

(Top view)

14 13 12 11 10 9 8 7 6 5 4 3 2 1

A3 A4 A5 A6 A7 A12 RDY/Busy V

CC

WE

NC A8 A9 A11

OE

A3 A4 A5 A6 A7 A12 RDY/Busy V

CC

WE RES

A8 A9 A11

OE

HN58V65A Series, HN58V66A Series

Pin Description

Pin name Function

A0 to A12 Address input I/O0 to I/O7 Data input/output

OE Output enable CE Chip enable WE Write enable

V

CC

V

SS

RDY/Busy Ready busy

1

RES* NC No connection

Notes: 1. This function is supported by only the HN58V66A series.

Block Diagram

Power supply Ground

Reset

Notes: This function is supported by only the HN58V66A series.

V

CC

V

SS

RES

OE

CE WE

RES

A0

to

A5

A6

to

A12

1

*

1

*

High voltage generator

Control logic and timing

Address buffer and latch

Y decoder

X decoder

to

I/O0 I/O7

I/O buffer and input latch

Y gating

Memory array

RDY/Busy

Data latch

Operation Table

HN58V65A Series, HN58V66A Series

VH*

V V

3

1

H

RDY/Busy I/O

High-Z Dout

High-Z to V

Din

OL

High-Z High-Z

× ——

V

H

IL

V

OL

Dout (I/O7)

High-Z High-Z

Operation CE OE WE RES*

Read V Standby V Write V Deselect V

IL

IH

IL

V ×* V V

IL

2

IH

Write Inhibit ××V

Data Polling V

× V

IL

V

IL

V

IH

×× High-Z High-Z V

IL

V

IH

×× —— V

IH

Program reset ×××V Notes: 1. Refer to the recommended DC operating conditions.

2. × : Don’t care

3. This function supported by only the HN58V66A series.

Absolute Maximum Ratings

Parameter Symbol Value Unit

Power supply voltage relative to V Input voltage relative to V Operating temperature range *

SS

2

SS

V

CC

Vin –0.5*1 to +7.0* Topr 0 to +70 ˚C

Storage temperature range Tstg –55 to +125 ˚C Notes: 1. Vin min : –3.0 V for pulse width ≤ 50 ns.

2. Including electrical characteristics and data retention.

3. Should not exceed V

+ 1 V.

CC

–0.6 to +7.0 V

3

V

HN58V65A Series, HN58V66A Series

Recommended DC Operating Conditions

Parameter Symbol Min Typ Max Unit

Supply voltage V

Input voltage V

V

V VH*

CC

SS

IL

IH

4

Operating temperature Topr 0 — 70 ˚C Notes: 1. VIL min: –1.0 V for pulse width ≤ 50 ns.

2. V

= 2.2 V for VCC = 3.6 to 5.5 V.

IH

3. V

max: VCC + 1.0 V for pulse width ≤ 50 ns.

IH

4. This function is supported by only the HN58V66A series.

5. V

= 0.8 V for VCC = 3.6 V to 5.5 V

IL

DC Characteristics (Ta = 0 to + 70˚C, VCC = 2.7 to 5.5 V)

Parameter Symbol Min Typ Max Unit Test conditions

Input leakage current I Output leakage current I Standby VCC curren I

Operating VCC current I

Output low voltage V Output high voltage V

LI

LO

CC1

I

CC2

CC3

OL

OH

Note: 1. ILI on RES : 100 µA max (only the HN58V66A series)

——2*1µA Vin = 0 V to V ——2µA Vout = 0 V to V — 1 to 2 5 µA CE = VCC – 0.3 V to VCC + 1.0 V ——1mACE = V — — 6 mA Iout = 0 mA, Duty = 100%,

— — 8 mA Iout = 0 mA, Duty = 100%,

— — 12 mA Iout = 0 mA, Duty = 100%,

— — 25 mA Iout = 0 mA, Duty = 100%,

— — 0.4 V IOL = 2.1 mA VCC × 0.8 — — V IOH = –400 µA

2.7 — 5.5 V 000V –0.3*

1.9*

1

— 0.6*

2

—V

5

+ 0.3*3V

CC

V

VCC – 0.5 — VCC + 1.0 V

CC

IH

Cycle = 1 µs at V

Cycle = 100 ns at V

Cycle = 70 ns at V

= 3.6 V

CC

= 5.5 V

CC

= 5.5 V

CC

= 3.6 V

Capacitance (Ta = 25˚C, f = 1 MHz)

Parameter Symbol Min Typ Max Unit Test conditions

Input capacitance Cin* Output capacitance Cout*

1

Note: 1. This parameter is sampled and not 100% tested.

— — 6 pF Vin = 0 V — — 12 pF Vout = 0 V

HN58V65A Series, HN58V66A Series

AC Characteristics (Ta = 0 to + 70˚C, VCC = 2.7 to 5.5 V)

Test Conditions

• Input pulse levels : 0.4 V to 2.4 V (VCC = 2.7 to 3.6 V), 0.4 V to 3.0 V (VCC = 3.6 to 5.5 V)

0 V to VCC (RES pin*2)

• Input rise and fall time : ≤ 5 ns

• Input timing reference levels : 0.8, 1.8 V

• Output load : 1TTL Gate +100 pF

• Output reference levels : 1.5 V, 1.5 V

Read Cycle 1 (VCC = 2.7 to 4.5 V)

HN58V65A/HN58V66A

-10

Parameter Symbol Min Max Unit Test conditions

Address to output delay t

CE to output delay t OE to output delay t

Address to output hold t

OE (CE) high to output float*1t RES low to output float* RES to output delay*

1, 2

2

ACC

CE

OE

OH

DF

t

DFR

t

RR

— 100 ns CE = OE = VIL, WE = V — 100 ns OE = VIL, WE = V 10 50 ns CE = VIL, WE = V 0—nsCE = OE = VIL, WE = V 040nsCE = VIL, WE = V 0 350 ns CE = OE = VIL, WE = V 0 450 ns CE = OE= VIL, WE = V

IH

HN58V65A Series, HN58V66A Series

Write Cycle 1 (VCC = 2.7 to 4.5 V)

Parameter Symbol Min*3Typ Max Unit Test conditions

Address setup time t Address hold time t

CE to write setup time (WE controlled) t CE hold time (WE controlled) t WE to write setup time (CE controlled) t WE hold time (CE controlled) t OE to write setup time t OE hold time t

Data setup time t Data hold time t

WE pulse width (WE controlled) t CE pulse width (CE controlled) t

Data latch time t Byte load cycle t Byte load window t Write cycle time t Time to device busy t Write start time t Reset protect time* Reset high time*

Notes: 1. tDF and t

2

2, 6

are defined as the time at which the outputs achieve the open circuit conditions

DFR

and are no longer driven.

2. This function is supported by only the HN58V66A series.

3. Use this device in longer cycle than this value.

4. t

must be longer than this value unless polling techniques or RDY/Busy are used. This

WC

device automatically completes the internal write operation within this value.

5. Next read or write operation can be initiated after t used.

6. This parameter is sampled and not 100% tested.

7. A6 through A12 are page addresses and these addresses are latched at the first falling edge of WE.

8. A6 through A12 are page addresses and these addresses are latched at the first falling edge of CE.

9. See AC read characteristics.

t t

AS

AH

CS

CH

WS

WH

OES

OEH

DS

DH

WP

CW

DL

BLC

BL

WC

DB

DW

RP

RES

0 ——ns 50——ns 0 ——ns 0 ——ns 0 ——ns 0 ——ns 0 ——ns 0 ——ns 50——ns 0 ——ns 200 — — ns 200 — — ns 100 — — ns

0.3 — 30 µs 100 — — µs — — 10*

4

ms

120 — — ns

5

0*

——ns 100 — — µs 1——µs

if polling techniques or RDY/Busy are

DW

HN58V65A Series, HN58V66A Series

Read Cycle 2 (VCC = 4.5 to 5.5 V)

HN58V65A/HN58V66A

-10

Parameter Symbol Min Max Unit Test conditions

Address to output delay t

CE to output delay t OE to output delay t

Address to output hold t

OE (CE) high to output float*1t RES low to output float* RES to output delay*

1, 2

2

ACC

CE

OE

OH

DF

t

DFR

t

RR

—70nsCE = OE = VIL, WE = V —70nsOE = VIL, WE = V 10 40 ns CE = VIL, WE = V 0—nsCE = OE = VIL, WE = V 030nsCE = VIL, WE = V 0 350 ns CE = OE = VIL, WE = V 0 450 ns CE = OE= VIL, WE = V

IH

HN58V65A Series, HN58V66A Series

Write Cycle 2 (VCC = 4.5 to 5.5 V)

Parameter Symbol Min*3Typ Max Unit Test conditions

Address setup time t Address hold time t

CE to write setup time (WE controlled) t CE hold time (WE controlled) t WE to write setup time (CE controlled) t WE hold time (CE controlled) t OE to write setup time t OE hold time t

Data setup time t Data hold time t

WE pulse width (WE controlled) t CE pulse width (CE controlled) t

Data latch time t Byte load cycle t Byte load window t Write cycle time t Time to device busy t Write start time t Reset protect time* Reset high time*

Notes: 1. tDF and t

2

2, 6

are defined as the time at which the outputs achieve the open circuit conditions

DFR

and are no longer driven.

2. This function is supported by only the HN58V66A series.

3. Use this device in longer cycle than this value.

4. t

must be longer than this value unless polling techniques or RDY/Busy are used. This

WC

device automatically completes the internal write operation within this value.

5. Next read or write operation can be initiated after t used.

6. This parameter is sampled and not 100% tested.

7. A6 through A12 are page addresses and these addresses are latched at the first falling edge of WE.

8. A6 through A12 are page addresses and these addresses are latched at the first falling edge of CE.

9. See AC read characteristics.

t t

AS

AH

CS

CH

WS

WH

OES

OEH

DS

DH

WP

CW

DL

BLC

BL

WC

DB

DW

RP

RES

0 ——ns 50——ns 0 ——ns 0 ——ns 0 ——ns 0 ——ns 0 ——ns 0 ——ns 50——ns 0 ——ns 100 — — ns 100 — — ns 50——ns

0.2 — 30 µs 100 — — µs — — 10*

4

ms

120 — — ns

5

0*

——ns 100 — — µs 1——µs

if polling techniques or RDY/Busy are

DW

Read Timing Waveform

Address

HN58V65A Series, HN58V66A Series

t

ACC

CE

OE

WE

Data Out

2

RES *

High

t

CE

t

OE

OH

t

DF

Data out valid

t

RR

t

DFR

HN58V65A Series, HN58V66A Series

Byte Write Timing Waveform(1) (WE Controlled)

Address

t

AH

CS

CE

t

CH

t

WC

WE

OE

Din

RDY/Busy

RES *

V

CC

t

AS

t

OES

t

WP

t

DS

High-Z

t

RP

t

RES

2

t

BL

t

OEH

t

DH

t

DW

t

DB

High-Z

HN58V65A Series, HN58V66A Series

Byte Write Timing Waveform(2) (CE Controlled)

Address

t

CE

WE

OE

t

AS

t

OES

WS

AH

t

CW

t

OEH

t

BL

WH

t

WC

Din

RDY/Busy

2

RES *

V

CC

t

DS

High-Z High-Z

t

RP

t

RES

t

DH

t

DW

t

DB

HN58V65A Series, HN58V66A Series

Page Write Timing Waveform(1) (WE Controlled)

Address A0 to A12

WE

CE

OE

Din

RDY/Busy

*7

t

AH

AS

t

WP

t

DL

t

CS

t

OES

t

DS

High-Z High-Z

t

RP

t

CH

t

DH

t

DB

t

BLC

t

OEH

BL

t

WC

t

DW

RES *

V

CC

2

t

RES

HN58V65A Series, HN58V66A Series

Page Write Timing Waveform(2) (CE Controlled)

Address A0 to A12

CE

WE

OE

Din

RDY/Busy

*8

t

AH

t

AS

t

CW

t

DL

t

WS

t

OES

t

DS

High-Z High-Z

t

RP

t

WH

t

DH

t

DB

t

BLC

t

OEH

t

BL

t

WC

t

DW

RES *

V

CC

2

t

RES

HN58V65A Series, HN58V66A Series

Data Polling Timing Waveform

Address

CE

WE

OE

I/O7

*9

t

CE

An

*9

Dout X

t

Dout X

WC

An An

t

OEH

t

OE

Din X

t

DW

t

OES

HN58V65A Series, HN58V66A Series

Toggle Bit

This device provide another function to determine the internal programming cycle. If the EEPROM is set to read mode during the internal programming cycle, I/O6 will charge from “1” to “0” (toggling) for each read. When the internal programming cycle is finished, toggling of I/O6 will stop and the device can be accessible for next read or program.

Toggle Bit Waveform

Notes: 1. I/O6 begining state is “1”.

2. I/O6 ending state will vary.

3. See AC read characteristics.

4. Any address location can be used, but the address must be fixed.

Next mode

*4

Address

*3

t

CE

WE

OE

I/O6

Din

t

OEH

*3

t

OE

*1 *2 *2

Dout

Dout Dout Dout

t

WC

t

DW

t

OES

HN58V65A Series, HN58V66A Series

Software Data Protection Timing Waveform(1) (in protection mode)

V

CC

CE

WE

t

BLC

t

WC

Address Data

1555 AA

0AAA 55

1555 A0

Write address

Write data

Software Data Protection Timing Waveform(2) (in non-protection mode)

V

CC

CE

WE

Address Data

1555AA0AAA551555801555AA0AAA551555

20

t

WC

Normal active mode

HN58V65A Series, HN58V66A Series

Functional Description

Automatic Page Write

Page-mode write feature allows 1 to 64 bytes of data to be written into the EEPROM in a single write cycle. Following the initial byte cycle, an additional 1 to 63 bytes can be written in the same manner. Each additional byte load cycle must be started within 30 µs from the preceding falling edge of WE or CE. When CE or WE is kept high for 100 µs after data input, the EEPROM enters write mode automatically and the input data are written into the EEPROM.

Data Polling

Data polling indicates the status that the EEPROM is in a write cycle or not. If EEPROM is set to read mode during a write cycle, an inversion of the last byte of data outputs from I/O7 to indicate that the EEPROM is performing a write operation.

RDY/Busy Signal

RDY/B us y signal also allows status of the EEPROM to be determined. The RDY/Busy signal has high impedance except in write cycle and is lowered to VOL after the first write signal. At the end of a write cycle, the RDY/Busy signal changes state to high impedance.

RES Signal (only the HN58V66A series)

When RES is low, the EEPROM cannot be read or programmed. Therefore, data can be protected by keeping RES low when VCC is switched. RES should be high during read and programming because it doesn’t provide a latch function.

V

CC

RES

Read inhibit Read inhibit

Program inhibit

HN58V65A Series, HN58V66A Series

WE, CE Pin Operation

During a write cycle, addresses are latched by the falling edge of WE or CE, and data is latched by the rising edge of WE or CE.

Write/Erase Endurance and Data Retention Time

The endurance is 105 cycles in case of the page programming and 104 cycles in case of the byte programming (1% cumulative failure rate). The data retention time is more than 10 years when a device is page-programmed less than 104 cycles.

Data Protection

1. Data Protection against Noise on Control Pins (CE, OE, WE) during Operation

During readout or standby, noise on the control pins may act as a trigger and turn the EEPROM to programming mode by mistake.

To prevent this phenomenon, this device has a noise cancellation function that cuts noise if its width is 15 ns or less.

Be careful not to allow noise of a width of more than 15 ns on the control pins.

WE CE

OE

15 ns max

V 0 V

IH

HN58V65A Series, HN58V66A Series

2. Data protection at VCC on/off

When VCC is turned on or off, noise on the control pins generated by external circuits (CPU, etc) may act as a trigger and turn the EEPROM to program mode by mistake. To prevent this unintentional programming, the EEPROM must be kept in an unprogrammable state while the CPU is in an unstable state.

Note: The EEPROM shoud be kept in unprogrammable state during VCC on/off by using CPU RESET

signal.

V

CC

CPU RESET

*

Unprogrammable

(1) Protection by CE, OE, WE

To realize the unprogrammable state, the input level of control pins must be held as shown in the table below.

*

Unprogrammable

CE V

CC

OE × V

××

SS

WE ×× V ×: Don’t care.

V

: Pull-up to VCC level.

CC

V

: Pull-down to VSS level.

SS

×

CC

HN58V65A Series, HN58V66A Series

(2) Protection by RES (only the HN58V66A series)

The unprogrammable state can be realized by that the CPU’s reset signal inputs directly to the EEPROM’s RES pin. RES should be kept VSS level during VCC on/off. The EEPROM breaks off programming operation when RES becomes low, programming operation doesn’t finish correctly in case that RES falls low during programming operation. RES should be kept high for 10 ms after the last data input.

V

CC

RES

WE

or CE

Program inhibit

1 µs min

100 µs min

10 ms min

Program inhibit

HN58V65A Series, HN58V66A Series

3. Software data protection

To prevent unintentional programming caused by noise generated by external circuits, this device has the software data protection function. In software data protection mode, 3 bytes of data must be input before write data as follows. And these bytes can switch the non-protection mode to the protection mode. SDP is enabled if only the 3 bytes code is input.

Address

1555

↓

0AAA

↓

1555

↓

Write address Normal data input

Data

AA

↓

55

↓

A0

↓

Write data }

Software data protection mode can be cancelled by inputting the following 6 bytes. After that, this device turns to the non-protection mode and can write data normally. But when the data is input in the cancelling cycle, the data cannot be written.

Address

1555

↓

0AAA

↓

1555

↓

1555

↓

0AAA

↓

1555

Data

AA

↓

55

↓

80

↓

AA

↓

55

↓

20

The software data protection is not enabled at the shipment.

Note: There are some differences between Hitachi’s and other company’s for enable/disable sequence

of software data protection. If there are any questions , please contact with Hitachi sales offices.

HN58V65A Series, HN58V66A Series

Package Dimensions

HN58V65AP Series HN58V66AP Series (DP-28)

35.6

28

36.5 Max

Unit: mm

15

13.4

14.6 Max

1

1.9 Max

2.54 ± 0.25

1.2

0.48 ± 0.10

14

5.70 Max

2.54 Min

0.51 Min

Hitachi Code JEDEC Code EIAJ Code Weight

(reference value)

0° – 15°

15.24

+ 0.11

0.25

– 0.05

DP-28 — SC-510-28E

4.6 g

Package Dimensions (cont)

HN58V65AFP Series HN58V66AFP Series (FP-28D)

18.3

18.8 Max

HN58V65A Series, HN58V66A Series

Unit: mm

28

1

1.12 Max

1.27

0.40 ± 0.08

0.38 ± 0.06

Dimension including the plating thickness

Base material dimension

0.15

0.20

14

M

15

8.4

0.20 ± 0.10

2.50 Max

Hitachi Code JEDEC Code EIAJ Code Weight

11.8 ± 0.3

0.17 ± 0.05

0.15 ± 0.04

1.0 ± 0.2

(reference value)

1.7

0° – 8°

FP-28D MO-059-AC —

0.7 g

HN58V65A Series, HN58V66A Series

Package Dimensions (cont)

HN58V65AT Series HN58V66AT Series (TFP-28DB)

8.00

8.20 Max

28

15

11.80

Unit: mm

1

14

0.55

0.22 ± 0.08

0.20 ± 0.06

0.10

M

0.45 Max

0.10

1.20 Max

Dimension including the plating thickness

Base material dimension

0.17 ± 0.05

0.15 ± 0.04

13.40 ± 0.30

+0.07

–0.08

0.13

0° – 5°

Hitachi Code JEDEC Code EIAJ Code Weight

(reference value)

0.80

0.50 ± 0.10

TFP-28DB — —

0.23 g

HN58V65A Series, HN58V66A Series

When using this document, keep the following in mind:

1. This document may, wholly or partially, be subject to change without notice.

2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without Hitachi’s permission.

3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the user’s unit according to this document.

4. Circuitry and other examples described herein are meant merely to indicate the characteristics and performance of Hitachi’s semiconductor products. Hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein.

5. No license is granted by implication or otherwise under any patents or other rights of any third party or Hitachi, Ltd.

6. MEDICAL APPLICATIONS: Hitachi’s products are not authorized for use in MEDICAL APPLICATIONS without the written consent of the appropriate officer of Hitachi’s sales company. Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi’s products are requested to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL APPLICATIONS.

Hitachi, Ltd.

Semiconductor & IC Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109

For further information write to:

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Hitachi Europe GmbH Electronic Components Group Continental Europe Dornacher Straße 3 D-85622 Feldkirchen München Tel: 089-9 91 80-0 Fax: 089-9 29 30 00

Hitachi Europe Ltd. Electronic Components Div. Northern Europe Headquarters Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA United Kingdom Tel: 0628-585000 Fax: 0628-778322

Hitachi Asia Pte. Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 0104 Tel: 535-2100 Fax: 535-1533

Hitachi Asia (Hong Kong) Ltd. Unit 706, North Tower, World Finance Centre, Harbour City, Canton Road Tsim Sha Tsui, Kowloon Hong Kong Tel: 27359218 Fax: 27306071