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HN58C65 Series
8192-word × 8-bit Electrically Erasable and Programmable CMOS
ROM
ADE-203-374A (Z)
Rev. 1.0
Apr. 12, 1995
Description
The Hitachi HN58C65 is a electrically erasable and programmable ROM organized as 8192-word × 8-bit. It
realizes high speed, low power consumption, and a high level of reliability, employing advanced MNOS
memory technology and CMOS process and circuitry technology. It also has a 32-byte page programming
function to make its erase and write operations faster.
Features
• Single 5 V Supply
• On chip latches: address, data, CE, OE, WE
• Automatic byte write: 10 ms max
• Automatic page write (32 byte): 10 ms max
• Fast access time: 250 ns max
• Low power dissipation: 20 mW/MHz typ (Active)
2.0 mW typ (Standby)
• Data polling and Ready/Busy
• Data protection circuity on power on/power off
• Conforms to JEDEC byte-wide standard
• Reliable CMOS with MNOS cell technology
• 105 erase/write cycles (in page mode)
• 10 year data retention
Ordering Information
Type No. Access Time Package
HN58C65P-25 250 ns 600 mil 28 pin plastic DIP (DP-28)
HN58C65FP-25 250 ns 28 pin plastic SOP*1 (FP-28D/DA)
Note: 1. T is added to the end of the type no. for a SOP of 3.0 mm (max) thickness.
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HN58C65 Series
Pin Arrangement
HN58C65P/FP Series
RDY/Busy
V
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
(Top View)
Pin Description
Pin Name Function
A0 – A12 Address input
I/O1 – I/O7 Data input/output
OE Output enable
CE Chip enable
WE Write enable
V
CC
V
SS
NC No connection
RDY/Busy Ready/Busy
Power (+5 V)
Ground
V
CC
WE
NC
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
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Block Diagram
HN58C65 Series
V
CC
V
SS
OE
CE
WE
A0
A4
A5
A12
High Voltage Generator
Control Logic and Timing
Address
Buffer and
Latch
Y Decoder
X Decoder
I/O0 I/O7
I/O Buffer
and
Input Latch
Y Gating
Memory Array
Data Latch
RDY/Busy
Mode Selection
Pin Mode CE OE WE RDY/Busy I/O
Read V
Standby V
Write V
Deselect V
IL
IH
IL
IL
Write inhibit X X V
XVILX High-Z —
Data polling V
IL
Note: 1. X = Don’t care
V
IL
*1
X
V
IH
V
IH
V
IL
V
IH
High-Z Dout
X High-Z High-Z
V
IL
V
IH
IH
V
IH
High-Z to V
OL
Din
High-Z High-Z
V
OL
Data out (I/O7)
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HN58C65 Series
Absolute Maximum Ratings
Parameter Symbol Value Unit
Supply voltage
Input voltage
*1
*1
Operating temperature range
Storage temperature range Tstg –55 to +125 °C
Notes: 1. With respect to V
2. –3.0 V for pulse width ≤ 50 ns.
3. Including electrical characteristics and data retention.
Recommended DC Operating Conditions
Parameter Symbol Min Typ Max Unit
Supply voltage V
Input voltage V
Operating temperature Topr 0 — 70 °C
V
CC
–0.6 to +7.0 V
Vin –0.5*2 to +7.0 V
*3
Topr 0 to +70 °C
SS
CC
IL
V
IH
4.5 5.0 5.5 V
–0.3 — 0.8 V
2.2 — VCC + 1 V
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HN58C65 Series
DC Characteristics (Ta = 0 to +70°C, VCC = 5 V ± 10%)
Parameter Symbol Min Typ Max Unit Test Conditions
Input leakage current I
Output leakage current I
VCC current (Standby) I
VCC current (Active) I
Input low voltage V
Input high voltage V
Output low voltage V
Output high voltage V
LI
LO
CC1
CC2
IL
IH
OL
OH
Note: 1. –1.0 V for pulse width ≤ 50 ns
——2 µAV
——2 µAV
——1 mACE = VIH, CE = V
— — 8 mA Iout = 0 mA
— — 25 mA Iout = 0 mA
*1
–0.3
— 0.8 V
2.2 — VCC + 1 V
— — 0.4 V IOL = 2.1 mA
2.4 — — V I
= 5.5 V
CC
Vin = 5.5 V
= 5.5 V
CC
Vout = 5.5/0.4 V
Duty = 100%
Cycle = 1 µs at
V
= 5.5 V
CC
Duty = 100%
Cycle = 250 ns at
V
= 5.5 V
CC
= –400 µA
OH
CC
Capacitance (Ta = 25°C, f = 1 MHz)
Parameter Symbol Min Typ Max Unit Test Conditions
Input capacitance
Output capacitance
*1
*1
Cin — — 6 pF Vin = 0 V
Cout — — 12 pF Vout = 0 V
Note: 1. This parameter is periodically sampled and not 100% tested.
AC Characteristics (Ta = 0 to +70°C, VCC = 5 V ± 10%)
Test Conditions
• Input pulse levels: 0.4 V to 2.4 V
• Input rise and fall time: ≤ 20 ns
• Output load: 1TTL gate + 100 pF
• Reference levels for measuring timing: 0.8 V and 2 V
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HN58C65 Series
Read Cycle
Parameter Symbol Min Max Unit Test Conditions
Address to output delay t
CE to output delay t
OE to output delay t
Address to output hold t
OE, CE high to output float
ACC
CE
OE
OH
*1
t
DF
Note: 1. tDF is defined at which the outputs archieve the open circuit conditions and are no longer driven.
Read Timing Waveform
Address
— 250 ns CE = OE = VIL, WE = V
— 250 ns OE = VIL, WE = V
10 100 ns CE = VIL, WE = V
IH
IH
0—nsCE = OE = VIL, WE = V
090nsCE = VIL, WE = V
t
ACC
IH
IH
IH
CE
OE
WE
Data Out
High
t
OH
t
CE
t
t
OE
DF
Data Out Valid
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Write Cycle
HN58C65 Series
Parameter Symbol Min
Address setup time t
Address hold time t
CE to write setup time (WE controlled) t
CE hold time (WE controlled) t
WE to write setup time (CE controlled) t
WE hold time (CE controlled) t
OE to write setup time t
OE hold time t
Data setup time t
Data hold time t
WE pulse width (WE controlled) t
CE pulse width (CE controlled) t
Data latch time t
Byte lode cycle t
Byte lode window t
Write cycle time t
Time to devce busy t
Write start time t
AS
AH
CS
CH
WS
WH
OES
OEH
DS
DH
WP
CW
DL
BLC
BL
WC
DB
DW
0 ——ns
150 — — ns
0 ——ns
0 ——ns
0 ——ns
0 ——ns
0 ——ns
0 ——ns
100 — — ns
20——ns
200 — — ns
200 — — ns
100 — — ns
0.30 — 30 µs
100 — — µs
——10*2ms
120 — — ns
150 — — ns
Notes: 1. Use this device in longer cycle than this value.
2. t
must be longer than this value unless polling technique is used. This device automatically
WC
completes the internal write operation within this value.
*1
Typ Max Unit Test Conditions
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HN58C65 Series
Byte Write Timing Waveform (1) (WE Controlled)
Address
t
CS
CE
t
AS
WE
t
OES
OE
t
WC
t
AH
t
CH
t
BL
tWP
t
OEH
Din
RDY/Busy
High-Z
t
DS
t
DH
t
DW
t
DB
High-Z
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Byte Write Timing Waveform (2) (CE Controlled)
Address
t
WS
CE
HN58C65 Series
t
t
AH
t
CW
t
WC
BL
WE
OE
Din
RDY/Busy
t
AS
t
OES
t
DS
High-Z High-Z
t
WH
t
OEH
t
DH
t
DW
t
DB
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HN58C65 Series
Page Write Timing Waveform (1) (WE Controlled)
Address
A5 to A12
Address
A0 to A4
WE
CE
t
CS
t
OES
t
AH
t
AS
t
WP
t
DL
t
CH
t
BLC
t
OEH
t
BL
t
WC
OE
Din
RDY/Busy
t
DS
t
DH
t
High-Z High-Z
DB
t
DW
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Page Write Timing Waveform (2) (CE Controlled)
Address
A5 to A12
Address
A0 to A4
CE
WE
t
WS
t
OES
t
AH
t
AS
t
CW
t
DL
t
WH
t
BLC
t
OEH
HN58C65 Series
t
BL
t
WC
OE
Din
RDY/Busy
t
DS
t
DH
t
High-Z High-Z
DB
t
DW
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HN58C65 Series
Data Polling Timing Waveform
Address
CE
WE
OE
I/O7
An An
Din X
Functional Description
An
t
DW
t
OES
t
BL
t
OE
Dout X
t
WC
Dout X
Automatic Page Write
Page-mode write feature allows 1 to 32 bytes of data to be written into the EEPROM in a single write cycle.
Following the initial byte cycle, an additional 1 to 31 bytes can be written in the same manner. Each
additional byte load cycle must be started within 30 µs of the preceding rising edge of the WE. When CE or
WE is high for 100 µs after data input, the EEPROM enters write mode automatically and the input data are
written into the EEPROM.
Data Polling
Da ta polling allows the status of the EEPROM to be determined. If EEPROM is set to read mode during a
write cycle, an inversion of the last byte of data to be loaded outputs from I/O7 to indicate that the EEPROM
is performing a write operation.
RDY/Busy Signal
RDY/Busy signal also allows the status of the EEPROM to be determined. The RDY/Busy signal has high
impedance, except in write cycle and is lowered to VOL after the first write signal. At the end of a write cycle,
the RDY/Busy signal changes state to high impedance.
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HN58C65 Series
WE, CE Pin Operation
During a write cycle, addresses are latched by the falling edge of WE or CE and data is latched by the rising
edge of WE or CE.
Write/Erase Endurance and Data Retention Time
The endurance is 105 cycles in case of the page programming and 3 × 103 cycles in case of byte programming
(1% cumulative failure rate). The data retention time is more than 10 years when a device is pageprogrammed less than 104 cycles.
Data Protection
1. Data Protection against Noise on Control Pins (CE, OE, WE) during Operation
During readout or standby, noise on the control pins may act as a trigger and turn the EEPROM to progam
mode by mistake. To prevent this phenomenon, this device has a noise cancelation function that cuts
noise if its width is 20 ns or less in program mode. Be careful not to allow noise of a width of more than
20 ns on the control pins.
WE
CE
OE
5 V
0 V
5 V
0 V
20 ns max
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HN58C65 Series
2. Data Protection at VCC On/Off
When VCC is turned on or off, noise on the control pins generated by external circuits (CPU, etc.) may act
as a trigger and turn the EEPROM to program mode by mistake. To prevent this unintentional
programming, the EEPROM must be kept in an unprogrammable state while the CPU is in an unstable
state.
V
CC
CPU
RESET
*
Unprogrammable
*
Unprogrammable
*The EEPROM should be kept in unprogrammable
state during V
on/off by using CPU RESET signal.
CC
In addition, when VCC is turned on or off, the input level of on control pins must be held as shown in the
table below.
CE V
CC
OE XV
WE XXV
X: Don’t care.
V
: Pull-up to VCC level
CC
V
: Pull-down to VSS level.
SS
XX
SS
X
CC
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HN58C65 Series
Package Dimensions
HN58C65P series (DP-28) Unit: mm
35.60
28
36.50 Max
15
13.40
14.60 Max
1
1.90 Max
1.20
14
15.24
5.70 Max
+ 0.11
0.25
– 0.05
2.54 ± 0.25
0.48 ± 0.10
2.54 Min
0.51 Min
0° – 15°
HN58C65FP Series (FP-28D) Unit: mm
18.30
18.75 Max
+ 0.10
– 0.05
15
8.40
14
11.80 ± 0.30
+ 0.08
– 0.07
2.50 Max
1.70
0.17
0 – 10 °
1.00 ± 0.20
M
0.20 ± 0.10
1.12 Max
28
1
1.27
0.40
0.20
0.15
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HN58C65 Series
HN58C65FP Series (FP-28DA) Unit: mm
18.00
18.75 Max
1.27 Max
1.27 ± 0.10
28
15
8.40
1
14
3.00 Max
+ 0.08
– 0.07
11.80 ± 0.30
1.70
0.17
0 – 10 °
0.40
+ 0.10
– 0.05
1.00 ± 0.20
0.20 ± 0.10
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