Datasheet HMS81C4260, HMS81C4360, HMS81C4360SK, HMS81C4460, HMS87C4260 Datasheet (HYNIX)

HYNIX SEMICONDUCTOR INC.

8-BIT SINGLE-CHIP MICROCONTROLLERS

HMS81C4x60

User’s Manual (Ver. 1.1)

Version 1.1
Published by MCU Application Team

Heung-il Bae([e-mail]) , Byoung-jin Lim( [e-mail])
2001 Hynix Semiconductor Inc. All rights reserved.

Additional information of this manual may be served by Hynix Semiconductor offices in Korea or Distributors and Repre­sentatives listed at address directory.

Hynix Semiconductor reserves the right to make changes to any information here in at any time without notice.
The information, diagrams and other data in this manual are correct and reliable; however, Hynix Semiconductor is in no

way responsible for any violations of patents or other rights of the third party generated by the use of this manual.

HMS81C4x60

HMS81C4x60

CMOS SINGLE-CHIP 8-BIT MICROCONTROLLER

FOR TELEVISION

1. OVERVIEW

1.1 Description

The HMS81C4x60 is an advanced CMOS 8-bit micro controller with 60 K bytes of ROM. This is one of the HMS8 00 family.
This is a powerful microcontroller which provides a high flexibility and cost effective solution to many TV applications. The
HMS81C4x60 provides following standard features: 60K bytes of ROM, 1024 bytes of RAM, 8/16-bit timer/counter, on­chip PLL oscillator and clock circuitry. In addition, there are othe r package types, HMS81C4360(32PDIP),
HMS81C4360SK(32SKDIP), HMS81C4 460 (42SDIP).
This document is explained for the base of HMS81C4x60, the eliminated functions are same as below.

Device name ROM Size EPROM Size RAM Size I/O Package

HMS81C4260 60K bytes - 1024bytes 31 52SDIP
HMS87C4260 60K bytes 1024bytes 31 52SDIP

1.2 Features

• 60K Bytes of On-chip Program Memory

• 1024 Bytes of On-chip Data RAM

• Minimum Instruction Cycle Time

- 256ns (NOP operation)

• PLL Oscillator for OSD and System Clock

- External 4MHz Crystal Input

• 31 Programmable I/O pins

- 26 Input/Output and 5 Input pins

2

C Bus Interface

•I

- Multimaster (2 Pairs interface pins)

• A/D Converter

- 8-bit

• Pulse Width Modulation

- 14-bit

- 8-bit

•Timer

- Timer/Counter : 8-bit

- Basic interval timer

× 5

× 1

× 5

ch

ch

ch

ch(16-bit × 2 ch)

× 4

- Watch Dog Timer

• Number of Interrupt Source

- 16 Interrupts

- 3 External Interrupts

•On Screen Display

- 512 character fonts pattern

- Character Size : 1.0, 1.5, 2.0 times

- Character Pixel size : 12 × 10, 12 × 12, 12 × 14,
12 × 16, 16 × 18

- Display Capability : 48 Characters × 16 Lines

- Character, Background color : 512 colors, 8 pal­let

- Special functions : Rounding, Outline, Shadow,
Underline, Double scanned line OSD

• Buzzer Driving Port

- 500Hz ~ 250KHz @4MHz (Duty 50%)

• Vertical Blanking Interveral Information cap­ture for EIA-608(Closed Caption) or VPS, etc

November 2001 Ver 1.1 1

HMS81C4x60

1.3 Development Tools

Note: There are several setting switches in the Emulator.

User should read carefully and do setting properly before
developing the program. Otherwise, the Emulator may not
work properly.

The HMS87C4x60 is sup po rte d b y a fu ll-f eat ured mac ro ass em­bler, an in-circuit emulator CHOICE-Dr.
grammers. There are two different type progra mmers such as
single type and gang type. For more de tail, refer to EP ROM Pro ­gramming chapter. Macro assembler operates under the MS­Windows 95/98

Please contact sales part of Hynix Semiconductor.

TM

.

TM

and EPROM pro-

1.4 Ordering Information

Device na me ROM Size (bytes) RAM size Package

Mask ROM version HMS81C4260 60K bytes 1024 bytes 52SDIP
OTP ROM version HMS87C4260 60K bytes EPROM (OTP) 1024 bytes 52SDIP
Mask ROM version HMS81C4360SK 60K bytes 1024 bytes 32SKDIP
OTP ROM version HMS87C4360SK 60K bytes EPROM (OTP) 1024 bytes 32SKDIP
Mask ROM version HMS81C4360 60K bytes 1024 bytes 32PDIP
OTP ROM version HMS87C4360 60K bytes EPROM (OTP) 1024 bytes 32PDIP
Mask ROM version HMS81C4460 60K bytes 1024 bytes 42SDIP
OTP ROM version HMS87C4460 60K bytes EPROM (OTP) 1024 bytes 42SDIP

2 November 2001 Ver 1.1

2. BLOCK DIAGRAM

VS

HS

HMS81C4x60

Vdd

RESET

Xin

Xout

Vss

TEST

YM

YS

CVBS

SCAP

R10/AN0
R11/AN1

R12/AN2
R13/AN3
R14/AN4

R30/PWM0
R31/PWM1
R32/PWM2
R33/PWM3

R34/PWM4

R35/PWM5

R36/BUZ

R40/SCL0

R41/SDA0

R42/SCL1

R43/SDA1

R24/EC2
R25/EC3

R37/TMR1

PLL

R
G
B

OSD

CLOCK

G8MC
CORE

GENERATION
/ SYSTEM

DATA

SLICER

CONTROLLER

RAM ( 1024)

PRESCALER

/BIT

ADC

WATCH DOG

MASK ROM
( User ROM
: 60KB
Font ROM
: 32KB )

TIMER

PWM

2

C

I

BUZZER

REMOCON

INTERRUPT
CONTROLLER

R4 PORT
R3 PORT
R2 PORT
R1 PORT
R0 PORT

R40 ~ R43

R30 ~ R37

R20 ~ R25

R10 ~ R14

R00 ~ R07

TIMER

R21/INT1

R22/INT2

R23/INT3

Figure 2-1 Block Diagram

November 2001 Ver 1.1 3

HMS81C4x60

3. PIN ASSIGNMENT

R40/SCL0
R41/SDA0
R42/SCL1
R43/SDA1
R04
R05
R06
R07
VDD
R14/AD4
SCAP
CVBS
VDD
VSS

R10/AD0
R11/AD1
R12/AD2
R13/AD3
HS
VS
R20
R21/INT1
R22/INT2
R23/INT3
R24/EC2
R25/EC3

1
2
3
4
5
6
7
8
9

HMS81C4260

10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

52SDIP

52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27

R30/PWM0
R31/PWM1
R32/PWM2
R33/PWM3
R34/PWM4
R35/PWM5
R36/BUZ
R37/TMR1
TEST
VSS
YM
YS
B
G
R
VDD
VSS
XIN
XOUT
RESET
R03
R02
VDD
VSS
R01
R00

Figure 3-1 52SDIP

4 November 2001 Ver 1.1

HMS81C4x60

R40/SCL0
R41/SDA0

R42/SCL1
R43/SDA1
R04
VDD
R14/AD4
SCAP
CVBS
VDD
VSS
R10/AD0
R11/AD1
R12/AD2
R13/AD3
HS
VS
R21/INT1
R22/INT2
R23/INT3
R24/EC2

1
2
3
4
5
6
7
8
9

HMS81C4460

10
11
12
13
14
15
16
17
18
19
20
21

42SDIP

42
41

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22

R31/PWM1
R32/PWM2

R33/PWM3
R34PWM4
R35/PWM5
R36/BUZ
R37/TMR1
TEST
YM
YS
B
G
R
XIN
XOUT
RESET
R03
R02
R01
R00
R25/EC3

Figure 3-2 42SDIP

November 2001 Ver 1.1 5

HMS81C4x60

R40/SCL0
R41/SDA0
R42/SCL1
R43/SDA1
VDD
R14/AD4
SCAP
CVBS
VDD
VSS
R10/AD0
R13/AD3
HS
VS

R21/INT1
R22/INT2

1
2
3
4
5
6
7

HM S81C 4360SK

8
9
10
11
12
13
14
15
16

32SKDIP

Figure 3-3 32SKDIP

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

R33/PWM3
R34/PWM4
R35/PWM5
R37/TMR1
TEST
YM
YS
B
G
R
XIN
XOUT
RESET
R02
R24/EC2
R23/INT3

R40/SCL0
R41/SDA0

R42/SCL1
R43/SDA1
VDD
R14/AD4
SCAP
CVBS
VDD
VSS
R10/AD0
R11/AD1
R12/AD2
R13/AD3

HS
VS

1
2
3
4
5
6
7
8

HMS81C4360

9
10
11
12
13
14
15
16

32PDIP

Figure 3-4 32PDIP

32
31

30
29
28
27
26
25
24
23
22
21
20
19
18
17

R34PWM4
R35PWM5

R37/TMR1
TEST
YM
YS
B
G
R
XIN
XOUT
RESET
R02
R24/EC2
R23/INT3
R21/INT1

6 November 2001 Ver 1.1

4. PACKAGE DIAGRAM

HMS81C4x60

HYNIX

HMS81C4260

1

45.97

0.13

0.76

0.47 0.13 1.02 0.25

0.13

1.778

0.25

2752

13.97

0.25

26

3.81 0.13

0.50 Min.

15.24

0.25

4.38 Max.

3.24

0.20

UNIT: mm

0 ~ 15

0.25 0.05

0.2 max

1

0.022

0.015

HYNIX

HMS81C4360

1.665

1.645

0.065

0.045

1732

16

0.1 BSC

MIN 0.015

0.140

0.120

TYP 0.600 BSC

0 ~ 15°

0.550

0.530

UNIT: inch

0

.

0

.

0

2

1

8

0

0

November 2001 Ver 1.1 7

HMS81C4x60

HYNIX

HMS81C4460

1

0.13

0.76

0.47 0.13 1.02 0.25

36.83

0.13

1.778

0.25

2242

13.97

0.25

21

3.81 0.13

0.50 Min.

15.24

0.25

4.38 Max.

3.24

0.20

UNIT: mm

0 ~ 15

0.25 0.05

32

HY NIX

HM S81C4360S K

1

27.68

0.76

0.13

0.47 0.13 1.02 0.2 5

0.13

17

16

1.778

0.25

Figure 4-1 Package Diagram

10.16

0.25

3.81 0.13

0 ~ 15

8.89

0.25

0.25 0.0 5

4.38 Max.

3.24

0.50 Min.

0.20

UNIT: mm

8 November 2001 Ver 1.1

5. PIN FUNCTION

HMS81C4x60

VDD: Supply voltage.
V

: Circuit ground.

SS

TEST

: Used for shipping inspection of the IC. For normal

operation, it should not be connected .

RESET
X

: Reset the MCU.

: Input to the inverting oscillator amplifier and input to

IN

the internal main clock operating circuit.

X

: Output from the inverting oscillator amplifier.

OUT

R00~R07: R0 is an 8-bit bidirectional I/O port. R0 pin s 1

or 0 written to the Port Direction Register can be used as
outputs or inputs.

R10~R14: R1 is a 5-bit read only port. R1 pins 1 or 0 writ ­ten to the Port Direction Register can be used as inputs.

In addition, R1 serves the functions of the various follow­ing special features.

Port pin Alternate function

R10
R11
R12
R13
R14

AD0 (A/D converter input 0)
AD1 (A/D converter input 1)
AD2 (A/D converter input 2)
AD3 (A/D converter input 3)
AD4 (A/D converter input 4)

R20~R25: R2 is a 6-bit CMOS bidirectional I/O port. Each
pins 1 or 0 written to the their Port Direction Regist er can
be used as outputs or inputs.

R30~R37: R3 is 8-bit CMOS bidirectional I/O port. R0
pins 1 or 0 written to the Port Direction Register can be
used as outputs or inputs.

In addition, R3 serves the functions of the various follow ­ing special features.

Port pin Alternate function

R30
R31
R32
R33
R34
R35

R36
R37

PWM0 (Pulse Width Modulation outp ut 0)
PWM1 (Pulse Width Modulation outp ut 1)
PWM2 (Pulse Width Modulation outp ut 2)
PWM3 (Pulse Width Modulation outp ut 3)
PWM4 (Pulse Width Modulation outp ut 4)
PWM5 (Pulse Width Modulation outp ut 5)
with 14bit resolution
BUZ (Buzzer output)
TMR1 (Timer Interrupt 1)

R40~R43: R4 is a 4- bit open drain I/ O por t. Each pi ns 1 or
0 written to the their Port Direction Register can b e used as
outputs or inputs.

In addition, R4 serves the functions of the various follow ­ing special features.

Port pin Alternate function

2

R40
R41
R42
R43

SCL0 (I
SDA0 (I
SCL1 (I
SDA1 (I

C Clock 0)

2

C Data0)

2

C Clock 1)

2

C Data 1)

In addition, R2 serves the functions of the various follow­ing special features.

Port pin Alternate function

R21
R22
R23
R24
R25

PIN NAME Pin No. In/Out Function

V

DD

V

SS

INT1 (External interrupt input 1)
INT2 (External interrupt input 2)
INT3 (External interrupt input 3)
EC2 (Event counter input 2)
EC3 (Event counter input 3)

9,13,30,

37

14,29,

36,43

- Supply voltage

- Circuit ground

Table 5-1 Port Function Description

R,G,B: R,G,B are output port. Each pins controls Red,
Green, Blue color control.

YM,YS: YM,YS are CMOS output port. Each pins con­trols Background, Edge control.

HS,VS: HS,VS are CMOS input port. Each pins Vertical
Sync. input and Horizaltal Sync. inputs.

CVBS: CVBS is a CVBS(Composit Video in) signal input
pin.

November 2001 Ver 1.1 9

HMS81C4x60

PIN NAME Pin No. In/Out Function

TEST 44 I TEST signal input (internal pull up resister)
RESET
X

IN

X

OUT

HS 19 I Horisontal Sync. input
VS 20 I Vertical Sync. input
R 38 O Red signal output
G 39 O Green signal output
B 40 O Blue signal output
YS 41 O Edge signal output
YM 42 O Background signal output
R30/PWM0 52 I/O
R31/PWM1 51 I/O 8bit PWM (pull up)
R32/PWM2 50 I/O 8bit PWM (pull up)
R33/PWM3 49 I/O 8bit PWM (pull up)
R34/PWM4 48 I/O 8bit PWM
R35/PWM5 47 I/O 14bit PWM
R36/BUZ 46 I/O Buzzer (pull up)
R37/TMR1 45 I/O Timer Interrupt 1
R40/SCL0 1 I/O

R41/SDA0 2 I/O
R42/SCL1 3 I/O
R43/SDA1 4 I/O
R20 21 I/O

R21/INT1 22 I/O External interrupt input 1
R22/INT2 23 I/O External interrupt input 2 (pull up)
R23/INT3 24 I/O External interrupt input 3
R24/EC2 25 I/O Event counter input 2
R25/EC3 26 I/O Event counter input 3 (pull up)

SCAP 11 I
R10/AD0 15 I

R11/AD1 16 I Analog input 1
R12/AD2 17 I Analog input 2
R13/AD3 18 I Analog input 3
R14/AD4 10 I Analog input 4
CVBS 12 I Composit video input

33 I Reset signal input
35 I Main oscillation input
34 O Main oscillation output

PWM functions

2

I

C functions (open drain)

External interrupt functions

A/D conversion functions

8bit PWM (pull up)

I2C Serial clock 0

2

C Serial data 0

I

2

C Serial clock 1

I

2

C Serial data 1

I
(pull up)

Data slicer comparation reference
voltage

Analog input 0

Table 5-1 Port Function Description

10 November 2001 Ver 1.1

PIN NAME Pin No. In/Out Function

HMS81C4x60

R00 27 I/O
R01 28 I/O (normal I/O, pull up)
R02 31 I/O (normal I/O)
R03 32 I/O (normal I/O, pull up)
R04 5 I/O (open drain, pull up)
R05 6 I/O (open drain, pull up)
R06 7 I/O (open drain, pull up)
R07 8 I/O (open drain, pull up)

Table 5-1 Port Function Description

Digital I/O functions

(normal I/O, pull up)

November 2001 Ver 1.1 11

HMS81C4x60

6. PORT STRUCTURES

XIN, X

OUT

V

DD

X

IN

V

DD

V

SS

X

OUT

V

SS

Main frequency
clock

V

SS

R03~R00,R37~R30,HS,VS,YS,YM

Data out

Out Enable

R14~10, CVBS

V

V

DD

Data out

Out Enable

V

SS

Data in

Data in

STOP

Analog in

Analog in

V

DD

V

DD

R07~R04, R43~R40, TEST

I/O

Pin

Data out

Out Enable

DD

V

SS

SchmittÛ{

V

DD

I

Pin

V

SS

V

DD

I/O

Pin

Data in

Data in

Schmitt

V

V

SS

SS

V

SS

V

SS

Data in

Û

{

Data in

Schmitt Û{

12 November 2001 Ver 1.1

HMS81C4x60

R,G,B

R25~R20, RESET

SCAP

V

V

DD

Data In

V

DD

I/O

Pin

V

SS

V

SS

DD

I/O

Pin

V

SS

Data out

Out Enable

Data in

Data in

Schmitt

V

DD

V

SS

Noise Filter

Û

{

V

DD

I/O

Pin

V

SS

November 2001 Ver 1.1 13

HMS81C4x60

7. ELECTRICAL CHARACTERISTICS

7.1 Absolute Maximum Ratings

Supply voltage...........................................-0.3 to +6.0 V

Storage Temperature ................................-40 to +125 °C

Voltage on any pin with respect to Ground (V

................................ ............................... -0.3 to V

SS

)

DD

+0.3

Maximum current out of Vss pin.........................160 mA

Maximum current into V
Maximum current sunk by(I
Maximum output current sourced by (I

pin ..........................160 mA

DD

per I/O Pin) .........20 mA

OL

per I/O Pin)

OH

.................................................................................8 mA

7.2 Recommended Operating Conditions

Parameter Symbol Condition

Supply Voltage
Operating Frequency
Operating Temperature

V

f

T

DD

XIN

OPR

VDD=4.5~5.5V

f

XIN

7.3 DC Electrical Characteristics

=4MHz

Maximum current (ΣI
Maximum current (ΣI

)....................................100 mA

OL

)......................................80 mA

OH

Note: Stresses above those listed under “Absolute Maxi­mum Ratings” may cause per manent damage to the d e­vice. This is a stress ra ting only and functional ope r ati on of
the device at any oth er c ond iti ons ab ov e tho se ind ic ated in
the oper ati o na l se c ti ons of this s pe c ifi ca t io n i s no t i m pl ie d .
Exposure to absolute maximum rating conditions for ex­tended periods may affect device reliability.

Specifications

Unit

Min. Max.

4.5 5.5 V

-4.0(typical)MHz

-10 70

C

°

(TA=-10~70°C, VDD=4.5~5.5V)

Parameter Symbol Condition

High level input voltage

Low level input voltage

High level output voltage

Low level output voltage
Supply current in

ACTIVE mode

pull-up lekage current

High input leakage
current

V

V

V

V

I

I

RUP

I

,

TEST, RESET, Xin, R0, R1, R2, R3,

IH

HS, VS
TEST, RESET, Xin, R0, R1, R2, R3,R4

IL

HS, VS
I

= -5mA

OH

OH

R0, R1, R2, R3, YS, YM
I

= 5mA

OL

OL

R0, R1, R2, R4
V

DD

IZH

DD

VDD = 5.5v, V

, R00, R01, R03, R04, R05, R06,

TEST

PIN

= 0.4V

R07, R20, R22, R25, R30, R31, R32, R33
R36

V

= 5.5V, V

DD

PIN

= V

DD

All input, I/O pins ex cept X

Specifications

Unit

Min. Typ. Max.

0.8 V

DD

-

0-

VDD - 1

-

--V

-1.0v

V

DD

0.12 V

DD

V

V

-4080mA

-1.5 -400

IN

-5 - 5

A

µ

A

µ

14 November 2001 Ver 1.1

HMS81C4x60

Parameter Symbol Condition

V

Low input leakage
current

RAM data retention
voltage

Hysterisis
Comparator operating

range

Comparator resolution

RGB DAC
Resolution 1

I

IZL

V

RAM

Vt+ ~

Vt-

V

rCVBS

V

aCVBS

RGB

R1

= 5.5V, V

DD

All input, I/O pins ex cept X
V

DD

, RESET, Xin, HS, VS, R07 ~ R00,

TEST
R21, R23, R24, R25, R37 ~ R30

V

= 5V

DD

CVBS pin
V

= 5V

DD

CVBS pin
V

= 5V

DD

No in/out current in R,G,B pin
RGB DAC On

No in/out current in R,G,B pin
Level 0
Level 1

RGB DAC
Output voltage

V

RGB

Level 2
Level 3
Level 4
Level 5
Level 6
Level 7
V

= 5V

DD

RGB V

RGB V

oh

ol

V

V

ohrgb

olrgb

RGB DAC On
Level 7

= -3mA

I

OH

V

= 5V

DD

RGB DAC On
Level 0

= 3mA

I

OL

PIN

= 0V

, OSC1

IN

Specifications

Unit

Min. Typ. Max.

-5 - 5

A

µ

1.2 - - V

1.0 - - V

1.2 - 3.5 V

- - 0.08 V

--5%

3/40V

dd

5/40V

dd

8/40V

dd

12/40V
17/40V
23/40V
30/40V
38/40V

dd
dd
dd
dd
dd

V

3.1 3.5 3.9 V

0.4 0.6 0.8 V

7.4 AC Characteristics

(TA=-10~70°C, VDD=5V±10%, VSS=0V)

Parameter Symbol Pins

Crystal oscillator Frequency

External Clock Pulse Width

External Clock Transition Time

f

XIN

t

MCPW

t

SCPW

t

MRCP,tMFCP

t

SRCP,tSFCP

X

IN

X

IN

S

CLK

X

IN

S

CLK

Specifications

Unit

Min. Typ. Max.

345MHz

180 - 350 nS

0.5 -

S

µ

- - 20 nS

- - 20 nS

November 2001 Ver 1.1 15

HMS81C4x60

Parameter Symbol Pins

Oscillation Stabilizing Time
Interrupt Pulse Width
RESET Input Width
Event Counter Input Pulse

Width
Event Counter Transition Time

1. t

is one of 1/f

SYS

main clock operation mode,

XIN

X

IN

t

ST

t

IW

t

RST

t

ECW

t

REC,tFEC

Specifications

Unit

Min. Typ. Max.

XIN, X

OUT

INT1~3 2 - ­RESET 8--

EC2, EC3 2 - -

--20mS

1

t

SYS

1

t

SYS

1

t

SYS

EC2, EC3 - - 20 nS

t

t

MRCP

MCPW

1/f

XIN

t

MFCP

t

MCPW

0.5V

-0.5V

V

DD

INT1 ~ 3

RESET

EC2, EC3

0.8V

t

REC

t

IW

DD

t

RST

t

ECW

t

FEC

Figure 7-1 Timing Chart

t

ECW

t

IW

0.2V

DD

0.2V

DD

0.8V

DD

0.2V

DD

16 November 2001 Ver 1.1

7.5 A/D Converter Characteristics

(TA=25°C, VDD=5V, VSS=0V)

HMS81C4x60

Parameter Symbol Condition

Analog Input Voltage Range
Overall Accuracy CAIN - ­Non Linearity Error NNLE - ­Differential Non Linearity Error NDNLE - ­Zero Offset Error NZOE - ­Full Scale Error NFSE - ­Gain Error NGE - ­Conversion Time TCONV

V

AN

f

MAIN

-

=4MHz

Min. Typ. Max.

VSS-0.3

Specifications

-

1.5

±

1.5

±

1.5

±

0.5

±

0.75

±

1.5

±

--15µS

VDD+0.3

2.5

±

2.5

±

2.5

±

2.0

±

1.0

±

2.0

±

Unit

V

LSB

November 2001 Ver 1.1 17

HMS81C4x60

7.6 Typical Characteristics

These graphs and tables are for design guidance only and
are not tested or guaranteed.

In some graphs or tables, the datas presented are out­side specified operating range (e.g. outside specified
VDD range). This is for information only and devices
are guaranteed to operate properly only within the
specified range.

I

OH

(mA)

-16

-14

-12

-10

I

OH

70°C

-8

-6

-4

-2
0

V

−

OH

-20°C

25°C

2.0 3.0

, VDD=5.2V

4.0

5.0

V

(V)

OH

The data is a statistical summary of data collected on units
from different lots over a period of time. “Typical” repre­sents the mean of the distribution while “max” or “min”
represents (mean + 3σ) and (mean − 3σ) r espectively
where σ is standard deviation

I

OL

(mA)

40

30

20

10

I

OL

-20°C

, VDD=5.2V

V

−

OL

25°C

70°C

1.0 3.02.0

4.0

V

(V)

OL

V

V

−

DD

Hysterisis

f

=4MHz

MAIN

Ta=25°C

44.5

IH

55.5

V

DD

(V)

6

V

V

−

DD

IH

V

IH1

f

=4MHz

MAIN

(V)

Ta=25°C

4

3

2

1

0

44.5

55.5

V

DD

(V)

6

V

IH2

(V)

4

3

2

1

0

18 November 2001 Ver 1.1

HMS81C4x60

V

V

−

DD

V

V

−

DD

IL

V

V

IL1

f

=4MHz

MAIN

(V)

Ta=25°C

IL1

(V)

Hysterisis

f

=4MHz

MAIN

Ta=25°C

IL

3

2

1

44.5

Operating Area

f

MAIN

Ta= -20~70°C

(MHz)

(Main-clock)

6
5
4
3
2
1

0

44.555.5 6.5

55.5

6

3

2

V

DD

(V)

6

1

44.5

55.5

V

DD

(V)

6

Normal Mode (Main opr.)

I

V

−

DD1

I

DD

(mA)

60

50

40

30

V

(V)

DD

20

DD

Ta=25°C

f

=4MHz

MAIN

44.555.56

V

DD

(V)

November 2001 Ver 1.1 19

HMS81C4x60

8. MEMORY ORGANIZATION

The GMS81C4x60 has separate address spaces for Pro­gram memory, Data Memory and D isplay memory. Pro­gram memory can only be read, not written to. It can be up

8.1 Registers

This device has six registers that are the Program Counter
(PC), a Accumulator (A), two index registers (X, Y), the
Stack Pointer (SP), and the Program Status Word (PSW).
The Program Counter consists of 16-bit register.

A

X

Y

SP

PCLPCH

PSW

Figure 8-1 Configuration of Registers

Accumulator: The Accumulato r is the 8-bit gen eral pur­pose register, used for data operation such as transfer, tem­porary saving, and conditional judgement, etc.

The Accumulator can be used as a 16-bit register with Y
Register as shown below.

ACCUMULATOR

X REGISTER

Y REGISTER
STACK POINTER

PROGRAM COUNTER
PROGRAM STATUS

WORD

to 60K bytes of Program mem ory. Data memory can be
read and written to up to 1024 bytes including the stack ar­ea. Font memory has prepared 32K bytes for OSD.

Generally, SP is automatically updated when a subrout ine
call is executed or an interrupt is accepted. However, if it
is used in excess of the stack area permitted by the data
memory allocating configuration, the user-processed data
may be lost.

The stack can be located at any position within 0 0

to FF

H

of the internal data memory. The SP is not initialized by
hardware, requiring to write the initial value (the location
with which the use of the stack starts) by using the initial­ization routine. Normally, the initial value of “FF

H”

is

used.

Stack Address (00

15 087

1

Hardware fixed

~ FFH)

H

SP

Caution:
The Stack Pointer must be initialized by software be-

cause its value is undefined after RESET.

Example: To initialize the SP

H

Y

Y A

A

LDX #0FFH
TXSP ; SP ← FFH

Program Counter: The Program Count er is a 16-bit wid e

Two 8-bit Registers can be used as a “YA” 16-bit Register

which consists of two 8-bit registers, PCH and PCL. This
counter indicates the address of the next instruction to be

Figure 8-2 Configuration of YA 16-bit Register

X, Y Registers: In the addressing mode which uses these
index registers, the register conten ts a re added to the spec­ified address, which becomes the actual address. These
modes are extremely effective for referencing subroutine
tables and memory tables . The index regi sters also h ave in­crement, decrement, comparison and data transfer func­tions, and they can be used as simple accumulators.

Stack Pointer: The Stack Pointer is an 8-bit register used
for occurrence interrupts and calling out subroutines. Stack
Pointer identifies the location in the stack to be accessed
(save or restore).

executed. In reset state, the program counter has reset rou­tine address (PC

:0FFH, PCL:0FEH).

H

Program Status Word: The Program Status Word (PSW)
contains several bits that reflect the current state of the
CPU. The PSW is described in Figure 8-3. It contains the
Negative flag, the Overflow flag, the Break flag the Half
Carry (for BCD operation), the Interrupt enable flag, the
Zero flag, and the Carry flag.

[Carry flag C]
This flag stores any carry or borrow from the ALU of CPU

after an arithmetic operation and is also changed by the
Shift Instruction or Rotate Instruction.

20 November 2001 Ver 1.1

HMS81C4x60

[Zero flag Z]
This flag is set when the result of an arithmetic operat ion

MSB LSB

N

PSW

NEGATIVE FLAG

OVERFLOW FLAG

SELECT DIRECT PAGE

when g=1, page is addressed by RPR

BRK FLAG

Figure 8-3 PSW (Program Status Word) Register

V G B H I Z C

[Interrupt disable flag I]
This flag enables/disables all interrupts except interrupt

caused by Reset or software BRK instruction. All inter­rupts are disabled when cleared to “0”. This flag immedi­ately becomes “0” when an interrupt is served. It is set by
the EI instruction and cleared by the DI instruction.

or data transfer is “0” and is cleared by any other result.

RESET VALUE : 00

CARRY FLAG RECEIVES
CARRY OUT

ZERO FLAG

INTERRUPT ENABLE FLAG
HALF CARRY FLAG RECEIVES

CARRY OUT FROM BIT 1 OF
ADDITION OPERLANDS

H

This flag assigns RAM page for direct addressing mode. In
the direct addressing mode, addressing area is from zero
page 00

to 0FFH when this flag is "0". If it is set to "1",

H

addressing area is assigned by RPR register (address
0F3

). It is set by SETG instruction and cleared by CLRG.

H

[Overflow flag V]
[Half carry flag H]
After operation, this is set when there is a carry from bit 3

of ALU or there is no borrow from bit 4 of ALU. This bit
can not be set or cleared except CLRV instruction with
Overflow flag (V).

[Break flag B]
This flag is set by software BRK instruction to distinguish

BRK from TCALL instruction with the same vector ad­dress.

[Direct page flag G]

This flag is set to “1” when an overflow occurs as the result

of an arithmetic operation involving signs. An overflow

occurs when the result of an addition or subtraction ex-

ceeds +127 (7F

) or −128 (80H). The CLRV instruction

H

clears the overflow flag. There is no set instruction. When

the BIT instruction is executed, bit 6 of memory is copied

to this flag.

[Negative flag N]

This flag is set to match the sign bit (bit 7) status of the re-

sult of a data or arithmetic operation. When the BIT in-

struction is executed, bit 7 of memory is copied to this flag.

November 2001 Ver 1.1 21

HMS81C4x60

At execution of a
CALL/TCALL/PCALL

01BC
01BD
01BE

01BF

SP before
execution

SP after
execution

PCL
PCH

01BF

01BD

Push
down

01BC
01BD

SP before
execution

SP after
execution

01BC
01BD
01BE

01BF

At execution
of PUSH instruction
PUSH A (X,Y,PSW)

01BE
01BF

A

01BF

01BE

At acceptance
of interrupt

PSW

PCL

PCH

01BF

01BC

Push
down

Push
down

01BC
01BD
01BE

01BF

At execution
of RET instruction

01BC
01BD
01BE

01BF

At execution
of POP instruction
POP A (X,Y,PSW)

PCL

PCH

01BD

01BF

A

01BE

01BF

Pop
up

Pop
up

At execution
of RETI instruction

01BC

0100

01BF

PSW

H

H

01BD
01BE

01BF

PCL

PCH

01BC

01BF

Stack
depth

Pop
up

Figure 8-4 Stack Operation

22 November 2001 Ver 1.1

8.2 Program Memory

HMS81C4x60

A 16-bit program counter is capable of addressing up to
64K bytes, but this device has 6 0K bytes program memory
space only physically implemented. Accessing a location
above FFFF

will cause a wrap-around to 0000H.

H

Figure 8-5 shows a map of Program Memory. After reset,
the CPU begins execution from reset vector which is stored
in address FFFE

and FFFFH as shown in Figure 8-6.

H

As shown in Figure 8-5, each area is assigned a fix ed loca­tion in Program Memory. Program Memory area contains
the user program.

1000

H

PROGRAM

FEFF
FF00

FFC0

FFDF

FFE0
FFFF

H
H

H
H

H

INTERRUPT

VECTOR ARE A

H

TCALL

AREA

MEMORY

PCALL

AREA

Example: Usage of TCALL

LDA #5

TCALL 15 ;
:;

:;
;
;TABLE CALL ROUTINE
;
FUNC_A: LDA LRG0

RET
;
FUNC_B: LDA LRG1

RET
;
;TABLE CALL ADD. AREA
;

ORG 0FFC0H ;

DW FUNC_A

DW FUNC_B

1BYTE INSTRUCTION
INSTEAD OF 2 BYTES
NORMAL CALL

1

2

TCALL ADDRESS AREA

The interrupt causes the CPU to jum p to specific location,
where it commences the execution of the service routine.
The External interrupt 1, for example, is assigned to loca­tion 0FFF8
interval: 0FFF6
0FFE8

Any area from 0FF00

. The interrupt service locations spaces 2-byte

H

and 0FFF7H for External Interru pt 2,

H

and 0FFE9H for External Interrupt 3, etc.

H

to 0FFFFH, if it is not going to be

H

used, its service location is available as general purpose
Program Memory.

Figure 8-5 Program Memory Map

Page Call (PCALL) area contains subroutine program to
reduce program byte length by using 2 bytes PCALL in­stead of 3 bytes CALL instruction. If it is frequently called,
it is more useful to save program byte length .

Table Call (TCALL) c auses the CPU to jump to each
TCALL address, where it commences the execution of the
service routine. The Table Call service area spaces 2-byte
for every TCALL: 0FFC0

for TCALL15, 0FFC2H for

H

TCALL14, etc., as shown in Figure 8-7.

Address Vector Area Memo ry

0FFE0

H

E2
E4
E6
E8
EA
EC
EE
F0

F2
F4
F6
F8
FA
FC
FE

2

C Bus Interface Interrupt Vector

I

-

Basic Interval Timer Interrupt Vector

Watchdog Timer Interrupt Vector

External Interrupt 3/4 Vector
Timer/Counter 3 Interrupt Vector
Timer/Counter 1 Interrupt Vector

V-Sync Interrupt Vector

Slicer Interrupt Vector
Timer/Counter 2 Interrupt Vector
Timer/Counter 0 Interrupt Vector

External Interrupt 2 Vector
External Interrupt 1 Vector

On Screen Display Interrupt Vector

-

RESET Vector

NOTE:

"-" means reserved area.

Figure 8-6 Interrupt Vector Area

November 2001 Ver 1.1 23

HMS81C4x60

Address PCALL Area Memory

0FF00

0FFFF

Address Program Memory

0FFC0

H

C1
C2

C3
C4
C5

H

PCALL Area

(256 Bytes)

H

C6
C7
C8
C9
CA
CB
CC
CD
CE
CF

D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF

NOTE:

* means that the BRK software interrupt is using
same address with TCALL0.

TCALL 15

TCALL 14

TCALL 13

TCALL 12

TCALL 11

TCALL 10

TCALL 9

TCALL 8

TCALL 7

TCALL 6

TCALL 5

TCALL 4

TCALL 3

TCALL 2

TCALL 1

TCALL 0 / BRK *

Figure 8-7 PCALL and TCALL Memory Area

PCALL→ rel

4F35 PCALL 35

~

~

0FF00

H

0FF35

H

0FFFF

H

H

4F

35

NEXT

~

~

TCALL→ n

4A TCALL 4

4A

~

~

0D125

0FF00

0FFD6
0FFD7

0FFFF

NEXT

H

H

H
H

H

25
D1

~

~

PC:

à : index address

01001010

11111111

FHFHDH6

Reverse

11010110

ÀÃ

H

24 November 2001 Ver 1.1

Example: The usage software example of Vector address and the initialize part.

ORG 0FFE0H
DW I2C_INT

DW NOT_USED
DW BIT_INT
DW WDT_INT
DW IR_INT
DW TIMER3
DW TIMER1
DW VSYNC_INT
DW SLICE_INT
DW T2_INT
DW T0_INT
DW EXT2_INT
DW EXT1_INT
DW OSD_INT
DW NOT_USED
DW RESET

ORG 0F000H

;********************************************
; MAIN PROGRAM *
;********************************************
;
RESET: DI ;Disable All Interrupts

CLRG
LDX #0

RAM_CLR: LDA #0 ;RAM Clear(!0000H->!00BFH)

STA {X}+
CMPX #0C0H
BNE RAM_CLR

;

LDX #0FFH ;Stack Pointer Initialize
TXSP

;

LDM PLLC,#0000_0101b ;16MHz system clock

;

LDM R0, #0FFh ;Normal Port 0
LDM R0DIR,#0FFh ;Normal Port Direction
:
:
LDM TM0,#0000_0000B ;timer stop
:
:
CALL VRAM_CLR ;Clear VRAM
:
:

HMS81C4x60

November 2001 Ver 1.1 25

HMS81C4x60

8.3 Data Memory

Figure 8-8 shows the internal Data Memory space availa­ble. Data Memory is divided in to four groups, a user RAM,
control registers, Stack, and OSD memory.

0000H

00C0H

0100H

0200H

0300H

0400H
0440H

0500H

0600H

0700H

0A00H

0AC0H

0B00H

0BC0H
0C00H

RAM (192 bytes)

Peripheral Reg. (64 bytes)

RAM (256 bytes)

Stack area

RAM (256 bytes)

RAM (256 bytes)

RAM (64 bytes)

NOT USED

NOT USED

RAM (Slicer RAM)

( 256 Byte)

Not Used

OSD RAM (192 bytes)

Peripheral Reg. (32 bytes)

OSD RAM (192 bytes)

Peripheral Reg. (32 bytes)

NOT USED

Page0

Page1

Page2

Page3

Page4

Page5

Page6

PageA

PageB

in each peripheral section.

Note: Write only registers can not be accessed by bit ma­nipulation instruction. Do not use read-modify-write instruc­tion. Use byte manipulation instruction.

Example; To write at CKCTLR

LDM CKCTLR,#05H ;Divide ratio ÷ 8

Stack Area

The stack provides the area where the return address is
saved before a jump is performed during the processing
routine at the execution of a subroutine call instruction or
the acceptance of an interrupt.

When returning from the processing routine, execu ting the
subroutine return instruction [RET] restores the contents of
the program counter from the stack; ex ecuting the interrupt
return instruction [RETI] restores the contents of the pro­gram counter and flags.

The save/restore locations in the stack are determined by
the stack pointed (SP). The SP is automatically decreased
after the saving, and increased before the restoring. This
means the value of the SP indicates the stack location
number for the next save. Refer to Figure 8-4 on page 22.

0FFFH

Figure 8-8 Data Memory Map

User Memory

The GMS81C4x60 has 1,024 × 8 bits for the user memory
(RAM) except Peripheral Reg. (64 bytes) .

Control Registers

The control registers are used by the CPU and Peripheral
function blocks for controlling the desired operation of the
device. Therefore these registers contain control and status
bits for the interrupt system, the timer/ counters, analog to
digital converters and I/O ports. The control registers are in
address range of 0C0

to 0FFH.

H

Note that unoccupied addresses may not be implemented
on the chip. Read accesses to these addresses will in gen­eral return random data, and write accesses will have an in­determinate effect.

More detailed informations of each register are explained

Address Symbol R/W Reset Value

00C0H
00C1H
00C2H
00C3H
00C4H
00C5H
00C6H
00C7H
00C8H
00C9H
00CAH
00CBH
00CCH
00CDH
00CEH
00CFH

R0

R0DD

R1

R1DD

R2

R2DD

R3

R3DD

R4

R4DD
reserved
reserved
reserved
reserved

FUNC

PLLC

R/W

W

R

W

R/W

W

R/W

W

R/W

W

-

-

-

­W
W

????????
00000000
????????

---00000
????????

--000000
????????
00000000
????????

----0000

-

-

-

-

0000000-

-0000000

Table 8-1Control registers

Addressin

g mode

byte, bit

2

byte

byte, bit

byte

byte, bit

byte

byte, bit

byte

byte, bit

byte

-

-

-

­byte
byte

1

26 November 2001 Ver 1.1

HMS81C4x60

0D0H
0D1H
0D2H
0D3H
0D4H
0D5H
0D6H
0D6H
0D7H
0D8H
0D9H
0DAH

0DBH
0DCH
0DEH
0DFH

0E0H

0E1H

0E2H

0E3H

0E4H

0E5H

0E6H

0E7H

0E8H

0E9H
0EAH
0EBH
0ECH
0EDH
0EEH

0EFH

0F0H

0F1H

0F2H

0F3H

0F4H

0F5H

0F6H

0F7H

0F8H

0F9H

0FAH

0FBH
0FCH
0FDH

0FEH

0FFH

TM0

TM2
TDR0
TDR1
TDR2
TDR3

BITR

CKCTLR

WDTR

ICAR

ICDR

ICSR

ICCR

reserved
reserved
reserved

PWMR0
PWMR1
PWMR2
PWMR3
PWMR4

PWMR5H

PWMR5L

reserved
reserved

reserved
PWMCR1
PWMCR2

reserved

reserved

reserved

AIPS

ADCM

ADR

IEDS

IMOD

IENL
IRQL
IENH

IRQH

reversed

IDCR

IDFS

IDR

DPGR

TMR
reserved
reserved

R/W
R/W
R/W
R/W
R/W
R/W

R
W
W

R/W
R/W
R/W
R/W

-

-

-

W
W
W
W
W

R/W
R/W

-

-

­R/W
R/W

-

-

-

W

R/W

R

W
R/W
R/W
R/W
R/W
R/W

-

R/W

R
R

R/W

W

-

-

-0000000

-0000000
????????
????????
????????
????????
????????

--010111

-0111111
00000000
11111111
0001000­00000000

????????
????????
????????
????????
????????
????????

--??????

00000000

-----000

--000000
????????

????????

--000000

--000000
00000000
00000000
00000000
00000000

0000-000
1----001
????????

----0000
????????

Table 8-1Control registers

byte

byte
byte, bit
byte, bit
byte, bit
byte, bit

byte

byte

byte
byte, bit
byte, bit
byte, bit
byte, bit

-

-

-

-

-

-

byte

byte

byte

byte

byte

byte
byte, bit

-

-

-

-

-

­byte, bit
byte, bit

-

-

-

-

-

-

byte

byte, bit

byte

byte
byte, bit
byte, bit
byte, bit
byte, bit
byte, bit

-

-

byte, bit

byte

byte
byte, bit

byte

-

-

-

-

0AD0
0AD1
0AD2
0AD3
0AD4
0AD5
0AD6
0AD7
0AD8

0AD9
0ADA
0ADB
0ADC
0ADD
0ADE
0ADF

0AE0H
0AE1H
0AE2H
0AE3H
0AE4H
0AE5H
0AE6H
0AE7H
0AE8H
0AE9H
0AEAH

0AEBH
0AECH
0AEDH

0AEEH

0AEFH

0AF0H

0AF1H

0AF2H

0AF3H

0AF4H

0AF5H

0AF9H

0BE0H

0BE1H

0BE2H

0BE3H

0BE4H

0BE7H

0BE8H

1. "byte, bit" means that register can be addressed by not only bit
but byte manipulation instruction.

2. "byte" means that register can be addressed by only byte
manipulation instruction. On the other hand, do not use any
read-modify-write instruction such as bit manipulation for clear­ing bit.

RED0
RED1

RED2
GREEN0
GREEN1
GREEN2

BLUE0
BLUE1

BLUE2
reserved
reserved
reserved
reserved
reserved
reserved
reserved

OSDCON1
OSDCON2
OSDCON3

FDWSET

EDGECOL

CHEDCL

OSDLN
LHPOS

DLLMOD

DLLTST

L1ATTR
L1EATR
L1VPOS

L2ATTR
L2EATR
L2VPOS

WINSH
WINSY
WINEH
WINEY

VCNT
HCNT

CULTAD

SLCON
SLINF0
SLINF1

RIKST

RIKED
SNCST
SNCED

W
W
W
W
W
W
W
W
W

-

-

-

-

-

-

-

R/W
R/W

W
W
W
W

R
W
W

R
W
W
W
W
W
W
W
W
W
W

R

R
W

R/W

W
W
W
W
W
W

????????
????????
????????
????????
????????
????????
????????
????????
????????

00000000
00000000
00000000
01111010
10000111
????????

---00000
????????
00000000

--000000
??????-?

---?????
????????
????????

---?????
????????
????????
????????
????????
????????
????????
????????
????????

00000000
00000000
00000000
????????
????????
????????
????????

Table 8-1Control registers

byte, bit-

byte, bit
byte, bit
byte, bit
byte, bit
byte, bit
byte, bit
byte, bit
byte, bit

-

-

-

-

-

-

-

-

-

-

-

-

-

-

byte, bit
byte, bit
byte, bit

byte
byte
byte
byte
byte
byte

byte
byte, bit
byte, bit

byte
byte, bit
byte, bit
byte, bit

byte

byte

byte

byte

byte

byte

byte
byte, bit

byte, bit
byte, bit

byte

byte

byte

byte

November 2001 Ver 1.1 27

HMS81C4x60

8.4 Addressing Mode

The GMS81C4x60 uses six addressing modes;

• Register addressing

• Immediate addressing

• Direct page addressing

• Absolute addressing

• Indexed addressing

• Register-indirect addressing

(1) Register Addressing

Register addressing accesses the A, X, Y, C and PSW.

(2) Immediate Addressing → #imm

In this mode, second byte (operand) is accessed as a data
immediate ly.

Example:

FE0435 ADC #35

MEMORY

H

04
35

A+35H+C → A

(3) Direct Page Addressing → dp

In this mode, a address is specified within direct page.
Example; G=0

E551: C535 LDA 35

35

H

data

H

;A ←RAM[35H]

À

0E550

0E551

~

~

H
H

C5
35

~

~

data → A

þ

þ : direct page

(4) Absolute Addressing → !abs

Absolute addressing sets corresponding memory data to
Data, i.e. second byte (Operand I) of command bec omes
lower level address and third byte (Operand II) becomes
upper level address.
With 3 bytes command, it is possible to access to whole
memory area.

ADC, AND, CMP, CMPX, CMPY, EOR, LDA, LDX,
LDY, OR, SBC, STA, STX, STY

When G-flag is 1, then RAM address is defined by 16-bit
address which is composed of 8-bit RAM paging register
(RPR) and 8-bit immediate data.

Example: G=1, RPR=01

E45535 LDM 35H,#55

0135

H

~

~

þ

0F100

H

0F101

H

0F102

H

data

E4
55
35

H

H

data

55

←

H

~

~

À

Example;

F100: 0735F0 ADC !0F035H ;A ←ROM[0F035H]

0F035

0F100
0F101
0F102

H

H
H
H

data

~

~

07
35
F0

~

~

À

þ

A+data+C → A

address: 0F035

28 November 2001 Ver 1.1

HMS81C4x60

The operation within data memory (RAM)
ASL, BIT, DEC, INC, LSR, ROL, ROR

Example; Addressing accesses the address 0135

regard-

H

less of G-flag and RPR.

F100: 981501 INC !0115H;A ←ROM[115H]

115

0F100
0F101
0F102

H

H
H
H

data

~

~

98
15
01

~

~

Ã

À

data+1 → data

þ

address: 0115

(5) Indexed Addressing

X indexed direct page (no offset) → {X}

In this mode, a address is specified by the X register.
ADC, AND, CMP, EOR, LDA, OR, SBC, STA, XMA
Example; X=15

E550: D4 LDA {X} ;ACC←RAM[X].

115

H

H

, G=1, RPR=01

data

H

À

X indexed direct page, auto increment→ {X}+

In this mode, a address is specified within direct page by
the X register and the content of X is increased by 1.

LDA, STA
Example; G=0, X=35

F100: DB LDA {X}+

35

H

~

~

data

DB

H

À

þ

data → A

36H → X

~

~

X indexed direct page (8 bit offset) → dp+X

This address value is the second byte (Operand) of com­mand plus the data of -register. And it assigns the mem­ory in Direct page.

ADC, AND, CMP, EOR, LDA, LDY, OR, SBC, STA
STY, XMA, ASL, DEC, INC, LSR, ROL, ROR

Example; G=0, X=0F5

E550: C645 LDA 45H+X

H

data → A

3A

þ

H

data

Ã

data → A

À

þ

45H+0F5H=13A

H

0E550
0E551

~

~

H
H

C6

45

~

~

0E550

~

~

H

D4

~

~

November 2001 Ver 1.1 29

HMS81C4x60

Y indexed direct page (8 bit offset) → dp+Y

This address value is the second byte (Operand) of com­mand plus the data of Y-register, which assigns Memory in
Direct page.

This is same with above (2). Use Y register instead of X.

Y indexed absolute → !abs+Y

Sets the value of 16-bit absolute address plus Y-register
data as Memory. This addressing mode can specify mem­ory in whole area.

Example; Y=55

F100: D500FA LDA !0FA00H+Y

0F100
0F101
0F102

0FA55

H

H
H
H

H

D5

00
FA

~

~

data

þ

0FA00H+55H=0FA55

~

~

H

À

data → A

Ã

FA00: 3F35 JMP [35H]

0E30A

0FA00

35

H

36

H

~

~

H

H

0A

E3

jump to address 0E30A

À

~

~

NEXT

~

~

3F
35

~

~

þ

H

X indexed indirect → [dp+X]

Processes memory data as Data, assigned by 16-bit pair
memory which is determined by pair data
[dp+X+1][dp+X] Operand plus X-register data in Direct
page.

ADC, AND, CMP, EOR, LDA, OR, SBC, STA

(6) Indirect Addressing

Direct page indirect → [dp]

Assigns data address to use for accomplishing command
which sets memory data (or pair memory) by Operand.
Also index can be used with Index register X,Y.

JMP, CALL
Example; G=0

Example; G=0, X=10

H

FA00: 1625 ADC [25H+X]

0E005

0FA00

35

H

36

H

~

~

H

~

~

H

05
E0

data

16
25

~

~

~

~

À

0E005

H

25 + X(10) = 35

þ

A + data + C → A

Ã

H

30 November 2001 Ver 1.1

HMS81C4x60

Y indexed indirect → [dp]+Y

Processes memory data as Data, assigned by the data
[dp+1][dp] of 16-bit p air memory paired by Operan d in Di­rect page plus Y-register data.

ADC, AND, CMP, EOR, LDA, OR, SBC, STA
Example; G=0, Y=10

FA00: 1725 ADC [25H]+Y

25

H

26

H

~

~

0E015

H

~

~

0FA00

H

05

E0

data

17
25

H

0E005H + Y(10) = 0E015

À

~

~

H

þ

~

~

A + data + C → A

Ã

Absolute indirect → [!abs]

The program jumps to address specified by 16-bit absolute
address.

JMP
Example; G=0

FA00: 1F25E0 JMP [!0E025H]

PROGRAM MEMORY

0E025

H

0E026

H

~

~

0E725

0FA00

H

~

~

H

þ

25
E7

NEXT

1F
25

E0

~

~

~

address 0E725

H

jump to

À

~

November 2001 Ver 1.1 31

HMS81C4x60

9. I/O PORTS

The HMS81C4x60 has 5 ports (R0, R1, R2, R3 and R4)
and OSD ports (R,G,B,YS,YM). These ports pins may be
multiplexed with an alternatefunction for the p eripheral

9.1 Registers for Port

Port Data Registers

The Port Data Registers (R0, R1, R2, R3, R4) are repre­sented as a D-Type flip-flop, which will clock in a value
from the internal bus in response to a “write t o data regis­ter” signal from the CPU. The Q output of the flip-flop is
placed on the internal bus in response to a “read data reg­ister” signal from the CPU. The level of the port pin itself
is placed on the internal bus in response to “read data reg­ister” signal from the CPU. Some inst ructions that read a
port activating the “read register” signal, and others acti­vating the “read pin” signal.

Port Direction Registers

All pins have data direction registers which can define
these ports as output or input. A “1” in the port direction
register configure the corresponding port pin as output.
Conversely, write “0” to the corresponding bit to specif y it
as input pin. For example, to use the even numbered bit of
R0 as output ports and the odd numbe red bits as input
ports, write “55

” to address 0C1H (R0 port direction reg-

H

features on the device. In general, in an initial reset state,
R ports are used as a general purpose digital port.

ister) during initial setting as sho w n in Figure 9-1.
All the port direction registers in the HMS81C 4x60 have

been written to zero by reset function. On the other hand,
its initial status is input.

WRITE “55

0C0

H

R0 DATA

0C1

R0 DIRECTION

H

~

~

0C8
0C9

H

R4 DIRECTION

H

R4 DATA

Figure 9-1 Example of port I/O assignment

” TO PORT R0 DIRECTION REGISTER

H

0 1 0 1 0 1 0 1
76543210

~

~

0 1 0 1 0 1 0 1
76543210

I O I O I O I O

76543210

I : INPUT PORT

O : OUTPUT PORT

BIT

BIT

PORT

32 November 2001 Ver 1.1

9.2 I/O Ports Configuration

HMS81C4x60

R0 Ports

R07 ~ R04 is an open drain bidirectional I/O port and R0 3
~ R00 is a CMOS bidirectional I/O port(a ddress 0C0

H

Each I/O pin can independently used as an input or an out­put through the R0DD register (address 0C1

).

H

The control registers for R0 are shown below.

R0 Data Register

R/W

R0

R0 Direction Register

R07

R0DD

R/W

R06

R/W

R05

Port Direction
0: Input
1: Output

ADDRESS : 00C0
RESET VALUE : Undefined

R/W

R/W

R04

R/W

R03

R02

ADDRESS : 00C1
RESET VALUE : 0000 0000

W WWW WW W W

R/W

R01

H

R/W

R00

H

b

R1 Ports

R1 is a 5-bit CMOS inpu t port only(ad dress 0C2

). Each

H

pin can independently used as an input through the R1DD
register (address 0C 3

). User can use R0DD register when

H

its bit is 0 only. The control registers for R1 are shown be­low.

R1 Data Register

R R R R

R1

R1 Direction Register

W

R1DD

-

WWWWWW

-

AIPS

MSB LSB

ADDRESS : 00C2
RESET VALUE : Undefined

R

R

R13

R14

ADDRESS : 00C3
RESET VALUE : ---0 0000

W WWW-W

Port Direction
0 : use Input only

ADDRESS: 00EF
INITIAL VALUE: --00 0000

AIPS.5 ~ AIPS.0

0 : R0 Port
1 : ADC Input

R

R12

AIPS2AIPS3AIPS4AIPS5-- AIPS0

H

R

R11

R10

H

W W

H

WW

AIPS1

b

H

functions as following table.

).

Port Pin Alternate Function

R10
R11
R12
R13
R14

AN0 (A/D input 0)
AN1 (A/D input 1)
AN2 (A/D input 2)
AN3 (A/D input 3)
AN4 (A/D input 4)

Port R1 is multiplexed with various special features.The
control registers controls the selection of alternate func­tion. After reset, this value is “0”, port may be used as nor­mal input port. The way to select alternate function such as
comparator input will be shown in each peripheral section.

In addition, R1 port is used as key scan function which op­erate with normal input port.

Input or output is configured automatically by each func­tion register (KSMR) regardless of R1DD.

R2 Port

R2 is a 6-bit CMOS bidirectional I/O port (addres s 0C4

).

H

Each I/O pin can independently used as an input or an out­put through the R2DD register (address 00C5

).The con-

H

trol registers for R2 are shown below.

R2 Data Register

R/W R/W

R/W R/W

R2

R2 Direction Register

R2DD

-

WWWWWW

R25

FUNC

MSB LSB

FUNC.5 ~ FUNC.1

0 : R2 Port
1 : INT mode, EC mode

ADDRESS : 00C4
RESET VALUE : Undefined

R/W

R/W

R23

R24

ADDRESS : 00C5
RESET VALUE : 0000 0000

W WWW-WW

Port Direction
0: Input
1: Output

ADDRESS: 00CE
INITIAL VALUE: 0000 0000

R/W

R22

INT 2 SINT 3 SEC2SEC3S--1

H

R/W

R21

R20

H

W W

H

WW

IN T1S

user must set 1

b

b

R1 port also can use the value bit5 ~ bit0 of AIPS register
to secondary function register. R1 port have secondary

R2 port also use the value bit5 ~ bit1 of FUNC register to
secondary function register. R2 port have seco ndary func-

November 2001 Ver 1.1 33

HMS81C4x60

tions as following table.

Port Pin Alternate Function

R21
R22
R23
R24
R25

INT1 (External Interrupt 1)
INT2 (External Interrupt 2)
INT3 (External Interrupt 3)
EC2 (Event Counter 2)
EC3 (Event Counter 3)

R3 Port

R3 is a 8-bit CMOS bidirectional output port (add ress

). Each I/O pin can indepe ndently used as an in put or

0C6

H

an output through the R3DD register (address 0C7

).

H

The control registers for R3 are shown below.

R3 Data Register

R/W

R3

R3 Direction Register

R37

R/W

R36

R/W

R35

ADDRESS : 00C6
RESET VALUE : Undefined

R/W

R/W

R34

R/W

R33

R32

ADDRESS : 00C7
RESET VALUE : 0000 0000

W WWW WW W W

R3DD

Port Direction
0: Input
1: Output

ADDRESS: 0 0E A
INITIAL VALUE: 0000 0000

R/W R/W R/W R/W R/W R/W

PWMCR1

MSB LSB

PWMCR.7 ~ PWMCR.0

0 : R3 Port
1 : PWM, BUZ, TMR1

H

R/W

R/W

R31

R30

H

H

R/W

R/W

EN2EN3EN4EN5BU ZTMR1 EN0

EN1

b

b

R4 Port

R4 is a 4-bit open drain and bidirectional I/O port (address
0C8

). Each I/O pin can independently used as an input or

H

an output through the R4DD register (address 0C9

).

H

The control registers for R4 are shown below.

R4 Data Register

R4

R4 Direction Register

W

R4DD

-

R/W R/W R/W R/W R/W R/W

ICCR

MSB

W-W

ADDRESS : 00C8
RESET VALUE : Undefined

R/W

R/WR/W R/WR/W R/W

-

-

Port Direction
0: Input
1: Output

ICCR.7 ~ ICCR.6

00 : R4 Port
01 : SCL0, SDA0, R42, R43
10 : SCL1, SDA1, R40, R41
11 : SCL0, SDA0, SCL1, SDA1

R/W

R43

R42

ADDRESS : 00C9
RESET VALUE : 0000 0000

W WW

ADDRESS: 00DB
INITIAL VALUE: 0000 0000

CCR2CCR3ESOACKbBSEL0BSEL1 CCR0

H

R41

H

W W

H

R/W R/W

CCR1

R/W

R40

b

b

LSB

R4 port also use the value bit7 ~ bit6 of ICCR register to
secondary function register. R4 port have seco ndary func­tions as following table.

R40
R41
R42
R43

SCL0 (Serial Clock 0)
SDA0 (Serial Data 0)
SCL1 (Serial Clock 1)
SDA1 (Serial Data 1)

R3 port also use the value bit7 ~ bit0 of PWMCR1 register
to secondary function register. R3 port have secondary
functions as following table.

R30
R31
R32
R33
R34
R35
R36
R37

PWM0 (Pulse Width Modulation 0)
PWM1 (Pulse Width Modulation 1)
PWM2 (Pulse Width Modulation 2)
PWM3 (Pulse Width Modulation 3)
PWM4 (Pulse Width Modulation 4)
PWM5 (Pulse Width Modulation 5 - 14bit)
BUZ (Buzzer Output)
TMR1 (Timer Interrup 1)

34 November 2001 Ver 1.1

10. CLOCK GENERATOR

HMS81C4x60

As shown in Figure 10-1 , the clock generation Circuit con ­sist PLL that generate multiplicated frequency of Crystal
clock, Generation Circuit which create CPU clock, Pres­caler which generate input clock of Basic Interval Timer
and variable hardware clock, Basic Interval timer which is

OSC
Circuit

PLL

ENPCK

8

070 5

MUX Basic Interval Timer(8) Watch Dog Timer(6)

Clock Pulse Gene rator

PRESCALER (11)

BTCL

generate standard time, Wat ch Dog Timer wh ich i s pr otect
Software Overflow.

See “12.1 BASIC INTERVAL TIMER” on pag e for de­tails.

Data Slicer Clock
OSD Clock

Internal System Clock
(16MHz typical)

Peripheral Circuit

11

IFBIT

WDTCL

6

CKCTRL

012345

6

8

Internal DATA BUS

10.1 Clock Generation Circuit

The clock signal come from crystal oscillator or ceramic
via Xin and Xout or from external clock via Xin is supplied
to Clock Pulse Generator and Prescaler.

Internal System Clock for CPU is made by Clock Pulse

COMPARATOR

6

WDTON

056

WDTR WDTCL

7

Generator, and several peripherial clock is divided by pres­caler.

Clock Generation circuit of Crystal Oscillator or Ceramic
Resonator is shown as below.

IFWDT

to RESET
CIRCUIT

November 2001 Ver 1.1 35

HMS81C4x60

Xout

Cout

GND

Xin

Cin

Figure 10-1 Cristal Oscillator or Ceramic Resonator

10.2 Phase Locked Loop

PLL(Phase Locked Loop) from OSC 4MHz clock circuit
generate Internal Syste m clock, Timer clock(PS0 ), Data

Figure 10-3 PLL Control Register

WWWWWW

PCF1PCF2----PLLON

PLLC

MSB LSB

PCF0

Slicer Clock, OSD clock, etc.

WW

Xout

Xin

Open

External Clock

Figure 10-2 External Clock

ADDRESS: 00CF
INITIAL VALUE: -000 0000

PLL clock freque nc y

0 : Off PLL
1 : On PLL, in the case system clock supply OSD circuit

PLL clock frequency

000 : 8MHz
001 : 12MHz
010 : 16MHz(typical)
011 : 24MHz
100 : 32Mhz

Test mode

H

b

10.3 PRESCALER

Prescaler consistor of 11-bit binary counter, and input
clock which is supplied by oscillation circuit. Frequency

f

ex

PS1 PS2 PS3 PS4 PS5 PS6 PS7 PS8 PS9 PS10 PS11

ENPCK

PS0 PS1 PS2 PS3 PS4 PS5 PS6 PS7 PS8 PS9 PS10 PS11

Figure 10-4 Prescaler

divided by prescaler is used as a source clock for periphe­rial hardwares.

B.I.T

8

12

PERIPHERAL

36 November 2001 Ver 1.1

HMS81C4x60

Peripheral Clock supplied from prescaler can be stopped
by ENPCK. Peripheral clock is determined by CKCTLR

WWWWWW

CKCTLR

MSB LSB

Figure 10-5 Clock Control Register

BTS2BTCLENPCKWDTON--BTS0

Register.(However, PS11 cannot be stopped by ENPCK)

WW

BTS1

ADDRESS: 00F6
INITIAL VALUE: --00 0000

B.I.T input clock select

000 : PS4 (4
001 : PS5 (8
010 : PS6 (16
011 : PS7 (32
100 : PS8 (64
101 : PS9 (128
110 : PS10 (256
111 : PS11 (512

B.I.T clear (when write)

0 : B.I.T Free-run
1 : B.I.T clear (Auto reset when after 1 cycle)

Peripherial clock enable (when wri te)

0 : Peripherial clock stop
1 : Peripherial clock supply

WDT function control(when write)

0 : 6 bit TIMER
1 : WATCH-DOG TIMER

B.I.T value (when read)

data : 00h ~ FFh

H

b

S)

µ

S)

µ

S)

µ

S)

µ

S)

µ

S)

µ

S)

µ

S)

µ

November 2001 Ver 1.1 37

HMS81C4x60

11. INTERRUPTS

The HMS81C4x60 interrupt circuits consist of Interrupt
enable register (IENH, IENL), Interrupt request flags of
IRQH and IRQL, Priority circuit and Master enable flag
("I" flag of PSW). 16 interrupt sources are provided. The
configuration of interrupt circuit is shown in Figure 11-2.

Below table shows the Interrupt priority

Reset/Interrupt Symbol Priority

Hardware Reset
reserved
OSD Interrupt
External Interrupt 1
External Interrupt 2
Timer/Counter 0
Timer/Counter 2
Slicer Interrupt
VSync Interrupt
Timer/Counter 1
Timer/Counter 3
Interrupt interval measure
Watchdog Timer
Basic Interval Timer
reserved

2

C Interrupt

I

RESET

­OSD
INT1
INT2

Timer 0
Timer 2

Slicer

VSync
Timer 1
Timer 3

INTV(INT3/4)

WDT

BIT

-

I2C

­1
2
3
4
5
6
7
8
9

10
11
12
13
14
15

The External Interrupts can be transition-activated (1-to-0
or 0-to-1 transition).
When an external interrupt is generated, the flag that gen­erated it is cleared by the hardware when the service rou­tine is vectored to only if the interrupt was transitio n­activated.

The Timer/Counter Interrupts are generated by
TnIF(n=0~3), which is set by a matc h in their respect ive
timer/counter register.

The Basic Interval Timer Interrupt is generated by BITIF
which is set by a overflow in the timer register.

The interrupts are controlled by the interrupt master enable
flag I-flag (bit 2 of PSW), that is the interrupt enable reg­ister (IENH, IENL) and the interrupt request flags (in
IRQH,IRQL) except Power-on reset and software BRK in­terrupt.

Interrupt Mode Register

It controls interrupt priority. It takes only one specified in­terrupt.

Of course, interrupt’s priority is fixed by H/W, but some­times user want to get specified interrupt even if higher
priority interrupt was occured. Higher priority interrupt is
occured the next time.

It contains 2bit data to enable priority selection and 4bit
data to select specified interrupt.

Bit No. Name Value Function

00

Mode 0: H/W priority

01

5,4 IM1~0

3~0 IP3~0

Table 11-1 Bit function

Interrupt Mode Register

R/W R/W

R/W R/W

IMOD

Figure 11-1 Interrupt Mode Register

0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111

Mode 1: S/W priority

1X

Interrupt is disabled, even
if IE is set.

­OSD
INT1
INT2
Timer 0
Timer 2
Slicer
VSync
Timer 1
Timer 3
INTV(INT3/4)
WDT
BIT

­I2C
Not used

ADDRESS : 00F3
RESET VALUE : Undefined

R/W

R/W

IP3

M0

M1

R/W

IP2

IP1

H

R/W

IP0

38 November 2001 Ver 1.1

Internal bus line

HMS81C4x60

IFOSD

INT1

INT2

Timer 0
Timer 2

Slicer

IFVSync

Timer 1
Timer 3

Intr. interval

IFWDT

IFBIT

IFI2C

IRQH
[0F7

H

IRQL

[00F5H]

]

OSD

INT1

INT2

SLICE
VSync

INTV
WDT

BIT

I2C

T0
T2

T1
T3

IENH [00F6H]

-

Interrupt Enable
Register (Higher byte)

IMOD [00F3H]

Bit5

RESET

BRK

To CPU

I Flag

Interrupt Master

Priority Control

-

Enable Flag

I-flag is i n PSW, it is c le a re d b y " DI", s e t by
"EI" in s t ru c tio n . When it g o e s i n te rr u p t s erv ice,
I-flag is cleared by hardware, thus any other
interrup t are inhibited. W hen interrupt service is
co mp le ted by "RET I" in s tru c ti o n , I- fla g is s e t to
"1" by h a rd ware .

Interrupt

Vector

Address

Generator

IENL [00F4H]

Interrupt Enable
Register (Lower byte)

Internal bus line

Figure 11-2 Block Diagram of Interrupt

November 2001 Ver 1.1 39

HMS81C4x60

Interrupt request flag registers are shown in Figure 11-3.
Interrupt request is generated when suitab le bit is s et, and
suitable request flag of accepted interrup is clear when in­terrupt processing cycle. Suitable bit is set when interrupt

OSD

T3

R/W

R/W R/W
INT2

R/W

R/W

INTV

WDT

R/W R/W R/W

IRQH

IRQL

-

MSB LSB

R/W R/W R/W R/W R/W

T1

MSB

T0

R/W R/W

T2INT1

-

SLICE

I2CBIT

request is occured, but no accepted request flag is set to
hold when the interrupt is accepted. Also, interrupt req uest
flag register(IRQH, IRQL) is the register of read or write.
So, request flag can be changed by program.

VSync

-

ADDRESS: 00F7
INITIAL VALUE: 0000 0000

VSync interrupt request flag
Slicer interrupt request flag
Timer / Counter 2 interrupt request flag
Timer / Counter 0 interrupt request flag
External interrupt 2 interrupt request flag
External interrupt 1 interrupt request flag
On screen display interrupt request flag

ADDRESS: 00F5
INITIAL VALUE: 0000 000-

LSB

2

C interrupt request flag

I

H

b

H

b

Basic interval timer interrupt request flag
Watch-dog timer interrupt request flag
Interrupt interval measurement interrupt request flag (INT3/4)
Timer / Counter 3 interrupt request flag
Timer / Counter 1 interrupt request flag

Figure 11-3 Interrupt Request Flag Registers

40 November 2001 Ver 1.1

HMS81C4x60

Interrupt enable flag registers are shown in Figure 11 -4.
These registers are composed of interrupt enable flags of
each interrupt source , these flags determi nes whether an
interrupt will be accepted or not. When enable flag is "0",

OSD

T3

R/W

R/W R/W
INT2

R/W

R/W

INTV

WDT

R/W R/W R/W

IENH

IENL

-

MSB LSB

R/W R/W R/W R/W R/W

T1

MSB

T0

R/W R/W

T2INT1

-

SLICE

I2CBIT

a corresponding interrupt source is prohibited. Note that
PSW contains also a master enable bit, I-flag, which dis­ables all interrupts at once.

VSync

-

ADDRESS: 00F6
INITIAL VALUE: 0000 0000

VSync interrupt enable flag
Slicer interrupt enable flag
Timer / Counter 2 interrupt enable flag
Timer / Counter 0 interrupt enable flag
External interrupt 2 interrupt enable flag
External interrupt 1 interrupt enable flag
On screen display interrupt enable flag

ADDRESS: 00F4
INITIAL VALUE: 0000 000-

LSB

2

C interrupt enable flag

I

H

b

H

b

Basic interval timer interrupt enable flag
Watch-dog timer interrupt enable flag
Interrupt interval measurement interrupt enable flag (INT3/4)
Timer / Counter 3 interrupt enable flag
Timer / Counter 1 interrupt enable flag

Figure 11-4 Interrupt Enable Flag Regesters

November 2001 Ver 1.1 41

HMS81C4x60

11.1 Interrupt Sequence

An interrupt request is held until the interrupt is accepted
or the interrupt latch is cleared to "0" by a reset or an in­struction. Interrupt acceptance sequence requires 8 f
µs at f

=4MHz) after the completion of the curr ent in -

MAIN

(2

ex

struction execution. The interrupt service task terminates
upon execution of an interrupt return instruction [RETI].

Interrupt acceptance

1. The interrupt master enable flag (I-flag) is cleared to
"0" to temporarily disable the acceptance of any fol­lowing maskable interrupts. When a non-maskable in­terrupt is accepted, the acceptance of any following
interrupts is temporarily disabled.

System clock

Instruction Fetch

2. Interrupt request flag for the in ter rup t source accep ted
is cleared to "0".

3. The contents of the program counter (return address)
and the program status word are saved (pushed) onto
the stack area. The stack pointer decrements 3 times.

4. The entry address of the interrupt service program is
read from the vector table address, and the entry ad­dress is loaded to the program counter.

5. The instruction stored at the entry address of the inter­rupt service program is executed.

Address Bus

Data Bus

Internal Read

Internal Write

V.L. and V.H. are vector addresses.
ADL and ADH are start addresses of interrupt service routi ne as vector contents.

PC

Not used

SP SP-1

PCH PCL

Interrupt Processing Step Interrupt Service Task

SP-2 V.H. New PC

PSW ADL OP codeADH

Figure 11-5 Interrupt Service routine Entering Timing

V.L.

V.L.

42 November 2001 Ver 1.1

Basic Interval Timer
Vector Table Address

012

0FFE6

H

0FFE7

H

Correspondence between vector table address for BIT interrupt
and the entry address of the interrupt service program.

0E3

H

H

0E312
0E313

Entry Address

0E

H

2E

H

H
H

A maskable interrupt is not accepted until the I-flag is set
to "1" even if a maskable interrupt of higher priority than
that of the current interrupt being serviced.

HMS81C4x60

General-purpose register save/restore using push and pop
instructions;

main task

acceptance of
interrupt

interrupt return

interrupt
service task

saving
registers

restoring
registers

When nested interrupt service is necessary, the I-flag is set
to "1" in the interrupt service program. In this case, accept­able interrupt sources are selectively enabled by the indi­vidual interrupt enable flags.

Saving/Restoring General-purpose Register

During interrupt acceptance processing, the program
counter and the program status word are automatically
saved on the stack, but not the accumulator and other reg­isters. These registers are saved by the program if neces­sary. Also, when nesting multiple interrupt services, it is
necessary to avoid using the same data memor y area for
saving registers.

The following method is used to save/restore the general­purpose registers.

Example: Register save using push and pop instructions

INTxx: PUSH A

PUSH X
LDA DPGR

PUSH A

;SAVE ACC.
;SAVE X REG.
;SAVE DPGR
; Direct page
; accessable reg.
;

11.2 BRK Interrupt

Software interrupt can be invoked by BRK instruction,
which is the lowest priority order.

Interrupt vector address of BRK is shared with the vector
of TCALL 0 (Refer to Program Memory Section). When
BRK interrupt is generated, B-flag of PSW is set to distin­guish BRK from TCALL 0.

Each processing step is determined by B-flag as shown in
Figure 11-6.

=0

=1

TCALL0

ROUTINE

RET

BRK or

TCALL0

B-FLAG

BRK

INTERRUPT

ROUTINE

RETI

interrupt processing

:
:

Figure 11-6 Execution of BRK/TCALL0

POP A
STA DPGR
POP X
POP A
RETI

;RESTORE DPGR
;RESTORE X REG.
;RESTORE ACC.
;RETURN

November 2001 Ver 1.1 43

HMS81C4x60

11.3 Multi Interrupt

If two requests of different priority levels are received si­multaneously, the request of higher priority level is ser­viced. If requests of the same priority level are received
simultaneously, an internal polling sequence determines
by hardware which request is serviced.

Main Program
service

Occur
TIMER1 interrupt

Occur
INT0

TIMER 1
service

enable INT0
disable other

EI

enable INT0
enable other

INT0
service

However, multiple processing through software for special
features is possible. Generally when an interrupt is accept­ed, the I-flag is cleared to disable any further interru pt. But
as user set I-flag in interrupt routine, some further interrupt
can be serviced even if certain interrupt is in progress.

Example: Even though Timer1 interrupt is in progress,
INT0 interrupt serviced without any susp end.

TIMER1: PUSH A

PUSH X
PUSH Y

LDM IENH,#20H ;
LDM IENL,#0 ;
EI ;

:
:
:

:
:
:

LDM IENH,#FFH ;
LDM IENL,#FEH

POP Y
POP X
POP A
RETI

Enable INT1 only
Disable other
Enable Interrupt

Enable all interrupts

In this example, the INT0 interrupt can be serviced without any
pending, even TIMER1 is in progress.
Because of re-setting the interrupt enable registers IENH,IENL
and master enable "EI" in the TIMER1 routine.

Figure 11-7 Execution of Multi Interrupt

44 November 2001 Ver 1.1

11.4 External Interrupt

HMS81C4x60

The external interrupt on INT1, INT2... pins are edge trig­gered depending the edge selection register.

Refer to “6. PORT STRUCTURES” on page 12.
The edge detection of external interrupt has three transition

activated mode: rising edge, falling edge, both edge.

INT1 pin

INT2 pin

INT3 pin

[00F2

edge selection

IEDS

]

H

INT1IF

INT2IF

INT3IF

INT1 INTERRUPT

INT2 INTERRUPT

INT3 INTERRUPT

INT1, INT2 and INT3 are multiplexed with general I/O
ports. To use external interrupt pin, the bit of port function
register FUNC1 should be set to "1" correspondingly.

Response Time

The INT1, INT2 and INT3 edge are latched into INT1IF,
INT2IF and INT3IF at every machine cycle. The values
are not actually polled by the circui try until the next ma­chine cycle. If a request is active and conditions are right
for it to be acknowledged, a hardware subroutine call to the
requested service routine will be the next instruction to be
executed. For example, the DIV instruction takes twelve
machine cycles. Thus, a minimum of twelve complete ma­chine cycles elapse between activation of an external inter­rupt request and the beginning of execution of the first
instruction of the service routine

Figure 11-8 External Interrupt Block Diagram

System clock

Instruction Fetch

Last instruction execution (0~12cycle) Enter interrupt service routine (8cycle)

Interrupt request sampling

1cycle

Interrupt overhaed (9~21cycle)

Figure 11-9 Interrupt Response Timing Diagram ( Interrupt overhead )

November 2001 Ver 1.1 45

HMS81C4x60

12. TIMER

12.1 Basic Interval Timer

The HMS81C4x60 has one 8-bit Basic Interval Timer that
is free-run and can not be stopped. Block diagram is shown
in Figure 12-1.

The Basic Interval Timer generates the time base for
watchdog timer counting, and etc. It also provides a Basic
interval timer interrupt (BITIF). As the count overflow
from FF

to 00H, this overflow causes th e interrupt to be

H

4

f

2

PS4
PS5
PS6
PS7
PS8
PS9

PS10
PS11

Clock control register

ex

f

ex

f

ex

f

ex

f

ex

f

ex

f

ex

f

÷

ex

Select Input clock

[0D6H]

CKCTLR

÷

5

2

÷

6

2

÷

7

2

÷

8

2

÷

9

2

÷

10

2

÷

11

2

WDT

ON

source
clock

MUX

BITCK

3

ENPCK BTCL BTS2 BTS1 BTS0

8-bit up-counter

[0D6

Internal bus line

]

H

BITR

clear

BTCL

generated. The Basic Interval T imer is controlled by the
clock control register (CKCTLR) shown in Figure 12-2.

Source clock can be selected by lower 3 bits of CKCTLR.
BITR and CKCTLR are located at same address, and ad-

dress 00D6

overflow

is read as a BITR and written to CKCTLR..

H

BITIF

Basic Interval Timer Interrupt

Watchdog timer clock (WDTCK)

Caution

WWWWWW

CKCTLR

MSB LSB

:

Both register are in same address,
when write, to be a CKCTLR,
when read, to be a BITR.

RRRRRR

BITR

MSB LSB

Figure 12-2 BITR Basic Interval Timer Mode Register

Figure 12-1 Block Diagram of Basic Interval Timer

BTS2BTCLENPCKWDTON--BTS0

8-BIT BINARY COUNTER

WW

BTS1

RR

ADDRESS: 00D6
INITIAL VALUE: --00 0000

B.I.T Clock
B.I.T clear (when write)

0 : B.I.T Free-run
1 : B.I.T clear (Auto reset when after 1 cycle)

Peripherial clock enable (write time)

0 : Peripherial clock stop
1 : Peripherial clock supply

WDT function control

0 : 6 bit TIMER
1 : WATCH-DOG TIMER

B.I.T value (when read)

ADDRESS: 00D6
INITIAL VALUE: Undefined

H

b

H

46 November 2001 Ver 1.1

12.2 Timer 0, 1

HMS81C4x60

Timer 0, 1 consists of prescaler, multiplexer, 8-bit compare
data register, 8-bit count register, Control register, and
Comparator as shown in Figure 12-3 and Figure 12-4.

These Timers can run separated 8bit timer or combined
16bit timer. These timers are operated by internal clock.

The contents of TDR1 are compared with the contents of
up-counter T1. If a match is f ound, a t imer /coun ter 1 in ter­rupt (T1IF) is generated, an d the counter is cleared. C ount­ing up is resumed after the counter is cleared.

R/W R/W R/W R/W R/W R/W

TM0

MSB LSB

T0CNT0STT1SL0T1SL1T1ST-T0SL0

Note: You can read Timer 0, Timer 1 value from TDR0 or
TDR1. But if you write data to TDR0 or TDR1, it changes
Timer 0 or Timer 1 modulo data, not Timer value.

The content of TDR0, TDR1 must be initiali zed (by soft­ware) with the value between 01

and FFH,not to 00H.

H

Or not, Timer 0 or Timer 1 can not count up forever.
The control registers for Timer 0,1 are shown below.

R/W R/W

T0SL1

ADDRESS: 00D0
INITIAL VALUE: -000 0000

T0 input clock select(fex=4MHz)

00 : PS2(1µS)
01 : PS4(4
10 : PS6(16
11 : PS8(64

Timer 0 Continue/Hold control

0 : Count Hold
1 : Count Countinue

Timer 0 Start control

0 : Count Hold
1 : Count Clear and Start

Timer 1 input clock(f

00 : Timer 0 overflow (16bit mode)
01 : PS2(1
10 : PS4(4
11 : PS6(16

Timer 1Start/Hold control

0 : Count Hold
0 : Count Clear and Start

H

b

S)

µ

S)

µ

S)

µ

=4MHz)

ex

S)

µ

S)

µ

S)

µ

ADDRESS: 00D2

INITIAL VALUE: Undefined

R/W R/W R/W R/W R/W R/W

H

R/W R/W

TDR0

MSB LSB

ADDRESS: 00D3
INITIAL VALUE: Undefined

R/W R/W R/W R/W R/W R/W

H

R/W R/W

TDR1

MSB LSB

Figure 12-3 Timer / Event Count 0,1

(Example) TIMER0 1mS TIME INTERVAL INTERRUPT

:
:

TDR_CNT: LDM TDR0,#249

LDM TDR1,#0
LDM TM0,#0011_1101b ; 4uSEC PRESCALER FOR T0
:
:

November 2001 Ver 1.1 47

HMS81C4x60

.

TM0 TDR0

Internal bus line

TDR1

PS2
PS4
PS6
PS8

NC

PS2
PS4
PS6

TDR0

T0CN

Timer 0

MUX

Clock

T0ST

MUX

T1ST

8bit Comparator

T0IF

Figure 12-4 Simplified Block Diagram of 8bit Timer0, 1

disable

clear & start

stop

~

~

~

~

8bit Comparator

T1IF

Timer 1

ClockClear Clear

enable

up-count

TIME

Timer 0 (T0IF)
Interrupt

T0ST
Start & Stop

T0CN
Control count

Occur interrupt Occur interrupt

T0ST = 1

T0ST = 0

T0CN = 1

T0CN = 0

Figure 12-5 Count Example of Timer

48 November 2001 Ver 1.1

TM0 TDR0

00

T0CN

HMS81C4x60

Internal bus line

TDR1

16bit Comparator

T1IF

PS2
PS4
PS6
PS8

Timer 0

MUX

Clock

T0ST

Figure 12-6 Simplified Block Diagram of 16bit Timer0, 1

Timer 1

ClockClear Clear

November 2001 Ver 1.1 49

HMS81C4x60

12.3 Timer / Event Counter 2, 3

Timer 2, 3 consists of prescaler, multiplexer, 8-bit compare
data register, 8-bit count register, Control register, and
Comparator as shown in Figure 12-7 and Figure 12-8.

These Timers have two operating modes. One is the timer
mode which is operated by internal clock, other is event
counter mode which is opera ted by external cloc k from pin
R24/EC2, R25/EC3.

These Timers can run separated 8bit timer or combined
16bit timer.

R/W R/W R/W R/W R/W R/W

TM2

MSB LSB

T3CNT3STT3SL0T3SL1T3 ST-T3SL0

Note: You can read Timer 2, Timer 3 value from TDR2 or
TDR3. But if you write data to TDR2 or TDR3, it changes
Timer 2 or Timer 3 modulo data, not Timer value.

The content of TDR2, TDR3 must be initiali zed (by soft­ware) with the value between 01

and FFH,not to 00H.

H

Or not, Timer 2 or Timer 3 can not count up forever.
The control registers for Timer 2,3 are shown below

R/W R/W

T3SL1

ADDRESS: 00D1
INITIAL VALUE: -000 0000

T2 input clock select

00 : External EVENT input(EC2)
01 : PS2(1
10 : PS4(4
11 : PS6(16

Timer 2 Continue/Hold control

0 : Count Hold
1 : Count Countinue

Timer 2 Start/Hold control

0 : Count Hold
1 : Count Clear and Start

Timer 3 input cl ock

00 : Connected to T2(16bit mode)
01 : External EVENT input(EC3)
10 : PS2 (1
11 : PS6 (16

Timer 3 Start/Hold control

0 : Count Hold
0 : Count Clear and Start

H

b

S)

µ

S)

µ

S)

µ

S)

µ

S)

µ

TDR2

TDR3

FUNC

ADDRESS: 00D4

R/W R/W R/W R/W R/W R/W

MSB

R/W R/W R/W R/W R/W R/W

MSB

WWWWWW

MSB LSB

INITIAL VALUE: Undefined

TDR2TDR3TDR4TDR5TDR6TDR7 TDR0

ADDRESS: 00D5
INITIAL VALUE: Undefined

TDR2TDR3TDR4TDR5TDR6TDR7 TDR0

IN T2SIN T3SEC0SEC1S---

H

R/W R/W

TDR1

H

R/W R/W

TDR1

WW

INT 1 S

Figure 12-7 Timer / Event Count 2,3

LSB

LSB

ADDRESS: 00CE
INITIAL VALUE: 0000 000-

R24/EC2 Select

0 : R24
1 : EC2

R25/EC3 Select

0 : R25
1 : EC3

H

b

50 November 2001 Ver 1.1

HMS81C4x60

.

Internal bus line

TM2 TDR2

TDR3

EC2
PS2
PS4
PS6

NC

EC3
PS2
PS4

TDR2

T2CN

Timer 2

MUX

Clock

T2ST

MUX

T3ST

8bit Comparator

T2IF

Timer 3

ClockClear Clear

Figure 12-8 Simplified Block Diagram of 8bit Timer/Event Counter 2,3

disable

enable

8bit Comparator

T3IF

Timer 2 (T2IF)
Interrupt

T2ST
Start & Stop

T2CN
Control count

clear & start

stop

~

~

Occur interrupt Occur interrupt

T2ST = 1

T2ST = 0

~

~

up-

T2CN = 1

T2CN = 0

Figure 12-9 Count Example of Timer / Event counter

unt

co

TIME

November 2001 Ver 1.1 51

HMS81C4x60

TM2 TDR2

00

T0CN

Internal bus line

TDR3

16bit Comparator

T3IF

EC2
PS4
PS6
PS8

MUX

Timer 2

Clock

T0ST

Figure 12-10 Simplified Block Diagram of 16bit Timer/Event Counter 2,3

Timer Mode

In the timer mode, the internal clock is used for counting
up. Thus, you can think of it as counting internal clock in­put. The contents of TDRn (n=0~3) are compared with the
contents of up-counter, Tim er n. I f mat ch is fou nd , a t ime r

Start count

Source clock

Up-counter

TDRn (n=0~3)

TnIF (n=0~3) interrupt

0

12 3

N

Timer 3

ClockClear Clear

n interrupt (TnIF) is generated and the up-counter is
cleared to 0. Counting up is resumed after the up-counter
is cleared.

As the value of TDRn is changeable by software, time in­terval is set as you want

~

~

~

~

~

~

~

~

~

~

~

~

N-2

N-1

Match
Detect

N

U

1 4

0

Counter
Clear

2

3

Figure 12-11 Timer Mode Timing Chart

Event Counter Mode

In event timer mode, counting up is started by an external
trigger. This trigger means falling edge of the ECn (n=0~1
) pin input. Source clock is used as an internal clock select­ed with TM2. The contents of TDRn are comp ared with the
contents of the up-cou nter. If a match is fo und, an TnIF in­terrupt is generated, and t h e coun ter is cleared to 00

. The

H

counter is restarted by the falling edge of the ECn pin in-

put.
The maximum frequency applied to the ECn pin is f

ex

[Hz] in main clock mode.
In order to use event counter fun ction, the bit EC0S, EC 1S

of the Port Function Se lect Regist er FUNC(address 0CE

H

is required to be set to "1".
After reset, the value of TDRn is undefined, it should be

52 November 2001 Ver 1.1

/2

)

initialized to between 01H~FF

ECn (n=2~3) pin

Up-counter

TDRn (n=2~3)

S

not to 00HU

H

Start count

0

HMS81C4x60

~

~

~

~

1

N

2

~

~

~

~

~

~

N-1

0N

1

2

TnIF (n=2~3) interrupt

Figure 12-12 Event Counter Mode Timing Chart

The interval period of Timer is calculated as below eq ua­tion.

1

------

Prescaler× ratio

=

Period

TDR2

Timer 2 (T2IF)
Interrupt

f

ex

~

~

Occur interrupt Occur interrupt Occur interrupt

TDR× n

1

0

TDR2=n

up

3

2

coun

-

4

t

7

6

5

~

~

n

n-1

n-2

~

~

8

P

CP

Interrupt period
= P

x n

CP

~

~

TIME

Figure 12-13 Count Example of Timer / Event counter

November 2001 Ver 1.1 53

HMS81C4x60

TDR2

Timer 2 (T2IF)
Interrupt

T2ST
Start & Stop

T2CN
Control count

disable

clear & start

stop

~

~

Occur interrupt Occur interrupt

T2ST = 1

T2ST = 0

enable

~

~

T2CN = 1

T2CN = 0

Figure 12-14 Count Operation of Timer / Event counter

up-

unt

co

TIME

54 November 2001 Ver 1.1

13. A/D Converter

HMS81C4x60

The A/D converter circuit is shown in Figure 13-1.
The A/D converter circuit consists of the comparator and

control register AIPS(00EF
ADR(00F1

). The AIPS register select normal port or an-

H

Data Bus

ADCM [F0

]

H

AN0
AN1
AN2
AN3
AN4

), ADCM(00F0H),

H

5

ADEN ADS2 ADS1 ADS0 ADST ADSF

Control circuit

port
select

MUX

0

S/H

alog input. The ADCM registe r control A/D converter’s
activity. The ADR register stores A/D converted 8bit re­sult. The more details are shown Figure 13-2.

8

ADR [F1H]

Comparator

Vref

Register ladder

+

−

0 1 2 3 4 5 6 7

8

IFA

Succesive
Approximation
Circuit

8

Figure 13-1 Block Diagram of A/D convertor circuit

Control

The HMS81C4x60 contains a A/D converter module
which has six analog inputs.

1. First of all, you h ave to select an alog input pin by set the
ADCM and AIPS.

2. Set ADEN (A/D enable bit : ADCM bit5).

3. Set ADST (A/D start bit : ADCM bit1). We recommend
you do not set ADEN and ADST at once, it makes worse
A/D converted result.

4. ADST bit will be cleared 1 cycle automatically after you
set this.

[Example]

;Set AIPS, change ? to what you want
; 0 : digital port
; 1 : analog port
LDM AIPS,#0000_1000b
; Set ADEN, xxx is analog port number
LDM ADCM,#0010_1100b
; or “SET1 ADEN”
; Set ADST, xxx is analog port number
LDM ADCM,#0010_11110b

BBC ADCM.ADSF,$
LDA ADR
; or “SET1 ADST”
:
:

5. After A/D conversion is completed, ADSF bit and inter-

rupt flag IFA will be set. (A/D conversion takes 36 ma­chine cycle : 18uS when f

Note: Make sure AIPS bits, if you usin g a port which is set
digital input by AIPS, analog voltage will be flow into MCU
internal logic not A/D converter. Sometimes device or port
is damaged permanently.

=4MHz).

ex

November 2001 Ver 1.1 55

HMS81C4x60

R/W R/W R/W R/W R/W R/W

ADCM

MSB LSB

RRRRRR

ADS0ADS1ADS2ADEN--ADSF

ADDRESS: 00F1

INITIAL VALUE: Undefined

ADR

MSB LSB

ADDRESS: 00EF

WWWWWW

INITIAL VALUE: ---0 0000

AIPS

MSB LSB

R/W R

ADST

H

RR

TDR2TDR3TDR4TDR5TDR6TDR7 TDR0

TDR1

H

WW

AIPS2AIPS3AIPS4--- AIPS0

AIPS1

ADDRESS: 00F0
INITIAL VALUE: --01 1101

A/D Converter Status bit

0 : Busy
1 : A/D conversion completed

A/D Converter Start bit

0 : Ignore
1 : A/D start (‘0’ after 1 cycle)

Analog Port Select

000 : AN0 select
001 : AN1 select
010 : AN2 select
011 : AN3 select
100 : AN4 select
101 : Default
110 : Default
111 : Default

A/D Converter Enable bit

0 : Disable
1 : Enable

H

H

b

ADS2 ADS1 ADS0

W
W

01
0
10

0
0

W
X
W

1

X

W

Analog Input Select

0 : P1 input
1 : ADC Input

Figure 13-2 A/D convertor Registers

Function

R14/AN4 R13/AN3 R12/AN2 R11/AN1 R10/AN0

AN0 R14 R13 R12 R11
AN1 R14 R13 R12
AN2 R14 R13
AN3 R14
AN4

AN4

AN3

R13R12R11R10

Figure 13-3 A/D Conversion Data Register

PORT select

AN1

AN2

R11 R10

R12 R11 R10

AN0

R10

56 November 2001 Ver 1.1

HMS81C4x60

14. Pulse Width Modulation (PWM)

The PWM circuit is shown in Figure 14-1, . The PWM circuit consists of the counter, comparator, Data

register.

Example

=4MHz)

(f

ex

14bit PWM 8bit PWM

Resolution 14 bits 8 bits

Input Clock 2MHz 250KHz

Frame cycle 8,192uS 1,024uS

The PWM control registers are PWMR4~0, PWMCR2~1,
PWM5H, PWM5L.

The more details about registers are shown Figure 14-2 .

PS5

CNTB

PWMR5 [E5

PWMR4 [E4

PWMR3 [E3

PWMR2 [E2

PWMR1 [E1H]

PWMR0 [E0H]

8bit comparator

8bit counter

PWMCR2 [EBH]

210

3

CNTB

]

H

]

H

]

H

]

H

EN5

EN4

PWMCR1 [EAH]

EN5

EN4

EN3

EN3

EN2

EN1

EN0

EN2

EN1

EN0

PWM5
PWM4

PWM3
PWM2

PWM1

PWM0

IF1Frame

Figure 14-1 8bit register (PWM7~0) circuit

PS2

PWMCR2 [EBH]

Internal C ontrol

PWMR5H 8bit [E8H]

MSB LSB

14bit comparator

14bit counter

PWMR5L 6bit [E9H]

CNTB

CNT

PWMCR1 [EAH]

EN8

PWM8

Figure 14-2 14bit register (PWM8) circuit

November 2001 Ver 1.1 57

HMS81C4x60

8bit PWM Control

The HMS81C4x60 contains a one 14bit PWM and five
8bit PWM module.

1. 8bit PWM0~5 is wholy same internal circuit, but
PWM0~5 output port is CMOS bidirectional I/O pin.

2. Al l PWM polarity has the same by POL2’s value.

3. Calulate Frame cycle and Pulse width is as following.
PWM Frame Cycle = 2
PWM Width = (PWMRn+1) × 2

13

/ fex (Sec)

5

/ fex (n=0~5)

Pulse Duty (%) = (PWMRn +1) / 256 × 100(%) (n=0~5)

Positive Polarity (POL2=0)

1

2

1. Frame cycle

2. Pulse Width

Figure 14-3 Wave form example for 8bit PWM

Negative Polarity (POL2=1)

1

2

4. PWM output is enabled during ENn(n=0~5) bit (See
PWMCR1~2) contains 1.

Sub PWM Frame Cycle = Main Frame Cycle / 64.

4. Table 14-1, “PWM5L and Sub frame matching table,”

on page 58 show PWM5L function.

Bit value

Sub frame number which is

added 1 clock

if Bit0=1 32 1
if Bit1=1 16, 48 2
if Bit2=1 8, 24, 40, 56 4
if Bit3=1 4, 12, 20, 28, 36, 44, 52, 60 8

if Bit4=1

2, 6, 10, 14, 18, 22, 26, 30, 34,
38, 42, 46, 50, 54

1, 3, 5, 7, 9, 11, 13, 15, 17, 19,

if Bit5=1

21, 23, 25, 27, 29, 31, 33, 35, 37,
39, 41, 43, 45, 47, 49, 51, 53, 55,
57, 59, 61, 63

Table 14-1 PWM5L and Sub frame matching table

012 616263

Main PWM Frame

Pulse
count

16

32

.....

Sub PWM Frame

PWMR4~0

R/W R/W R/W R/W R/W R/W

PWM0D7

PWM 0D6 PW M0D 5 PW M0D4 PW M0D 3 PW M0D2 PWM 0D1 PW M0D0

MSB LSB

Each PWM Data Store

ADDRESS: 00E0

INITIAL VALUE: Undefined

~E4

H

R/W R/W

H

Figure 14-4 8bit PWM Registers

5. CNTB controls all PWM counter enable.
If CNTB=0, than Counter is disabled.

14bit PWM Control

1. 14bit PWM’s operation concept is not the same as 8bit
PWM.
1 PWM frame contains 64 sub PWMs.
PWM5H : Set sub PWM’s basic Pulse Width.
PWM5L : Number of sub PWM wh ich i s added 1 clock.

2. PWM polarity is selected by POL1’s value.
If POL1=0, Positive Polarity.

3. Calulate Frame cycle and Pulse width is as following.
Main PWM Frame Cycle = 2

16

/ fex (Sec).

Sub PWM Frame
which is added
1 clock

1 clock width : PS2

Figure 14-5 Wave form example for 14bit PWM

PWM 5H

R/W R/W R/W R/W R/W R/W

PWM5H7

PWM5H6 PWM5H5 PW M5H4 PWM5H3 PWM5H2 PW M5H1 PWM5H0

MSB LSB

PWM5L

R/W R/W R/W R/W R/W R/W

MSB LSB

ADDRESS: 00E8
INITIAL VALUE: Undefined

ADDRESS: 00E9
INITIAL VALUE: Undefined

H

R/W R/W

H

R/W R/W

PWM 5L0PWM 5L1PWM 5L3PWM5L4PW M5L5-- PWM 5L2

Figure 14-6 PWM5H, PWM5L Register

58 November 2001 Ver 1.1

HMS81C4x60

R/W R/W R/W R/W R/W R/W

PWMCR1

MSB LSB

EN2EN3EN4EN5BU ZTMR1 EN0

Figure 14-7 PWM Control Register 1

R/W R/W
EN1

ADDRESS: 00EA
INITIAL VALUE: 0000 0000

R30/PWM0 Select

0 : R30
1 : PWM0

R31/PWM1 Select

0 : R31
1 : PWM1

R32/PWM2 Select

0 : R32
1 : PWM2

R33/PWM3 Select

0 : R33
1 : PWM3

R34/PWM4 Select

0 : R34
1 : PWM4

R35/PWM5 Select

0 : R35
1 : PWM5

]

/Buzzer Select

R3

0 : R36
1 : Buzzer output

R37/TMR1 Select

0 : R37
1 : TMR1

H

b

R/W R/W R/W R/W R/W R/W

PWMCR2

MSB LSB

POL8----- CNTB

Figure 14-8 PWM Control Register 2

R/W R/W

POL14

ADDRESS: 00EB
INITIAL VALUE: 0000 0000

14Bit/8Bit PWM Count stop/start

0 : Count start
1 : Count stop

14Bit PWM Output Polarity

0 : Positive Polarity
1 : Negitive Polarity

8Bit PWM Output Polarity

0 : Positive Polarity
1 : Negative Polarity

H

b

November 2001 Ver 1.1 59

HMS81C4x60

15. Interrupt Interval Measurement Circuit

The Interrupt interval measurement circuit is shown in Fig­ure 15-1.

The Interrupt interval measurement circuit con sists of the
input multiplexer, sampling clock multiplexer, Edge detec-

Data Bus

7

I34L ISEL IDCK IDST

I34H

IDCR [F9H]

PS8

PS9

INT3

1
MUX

0

1
MUX

0

IMS

Edge detector

0
MUX

1

tor, 8bit counter, measured result storing register, FIFO (9
bit, 6 level) interrupt, Control register, etc.

The more details about registers are shown Figure 15-2 .

4

FEMPFCLR

INT34

Clear

IDFS [FAH]

8bit counter

FCLR

IDR [FBH]

DPOL FOE FFUL

Overflow 8 4

D6 D5 D4 D3 D2 D1 D0

D7

FIFO

(9bit, 6level)

Figure 15-1 Block Diagram of Interrupt interval measurement circuit

Control

The HMS81C4x60 contains a Interrupt interval measure­ment module.

1. Select interrupt input pin what you want to measure by
set the FUNC [00CE

2. Set IDCR [00F9

].

H

] : FIFO clear, interrupt mode select,

H

interrupt edge select, external interrupt INT3 select, sam­pling clock select, COUNT start/stop select.

3. Set IDCR [00F9

4. Counter value is stored to IDR [00FB

] : set IDST to start measuring.

H

] when selected

H

edge is detected. After data was written, timer is cleard au­tomatically and it counts continue.

5

. You can select interrupt occuring point by set Interrupt
Mode Select bit (IMS), every edge what you selected or
FIFO 4 level is filled.

6. If input signal’s interval is larger than maximum counter
value (0FF
again from 00

), counter occurring an interrupt and count

H

.

H

7. See Figure 15-7 FIFO operating mechanism.

[Example]
;Set INT3 for remote control pulse
reception

LDM FUNC,#0000_1001b;INT3 SET
LDM IDCR,#1001_0001b ;64uSec PCS
:
:

60 November 2001 Ver 1.1

HMS81C4x60

R/W R/W R/W R/W R/W R/W

IDC R

MSB LSB

ISEL-I34 LI3 4 HIMSFCLR IDST

Figure 15-2 Int. interval determination control register

R/W R/W

IDCK

ADDRESS: 00F9
INITIAL VALUE: 0001 -000

Counter control

0 : Stop
1 : Clear & Count

Sample Clock Select

0 : PS9(128uSec)
1 : PS8(64uSec)

External Interrupt Select

0 : INT3 fixed

External Interrupt Edge Select

00 : No Select
01 : Falling Edge
10 : Rising Edge
11 : Both Edge

Interrupt Mode

0 : Every Selected Edge by I34H/L
1 : Every FIFO 4Level is Filled

FIFO Clear

0 : Ignored
1 : Clear & Return to 0

H

b

R/W R/W R/W R/W R/W R/W

IDFS

MSB LSB

FOEDPOL FEMP

Figure 15-3 Port function select register

WWWWWW

FUNC

MSB LSB

R/W R/W

FFUL

WW

INT 2 SINT 3 SEC2SEC3S---

IN T1S

ADDRESS: 00FA
INITIAL VALUE: 0--- -001

FIFO Empty Flag

0 : Data Filled
1 : Empty

FIFO Full flag

0 : Not Full
1 : Full

FIFO Overrun Error Flag

0 : No Error
1 : Error Detected

Data Polarity

0 : Data is stored every falling edge
1 : Data is stored every rising edge

R24/INT3 Select

0 : R23
1 : INT3

H

b

ADDRESS: 00CE
INITIAL VALUE: --00 000-

H

b

Figure 15-4 Port function select register

November 2001 Ver 1.1 61

HMS81C4x60

Interrupt input

c

e

f

Item Symbol I34H I34L

c

1 0 Rising edge

Frame Cycle

d

e

01
1 1 Both edge

Pulse width

f

1 1 Both edge

Figure 15-5 Setting for measurement

1) FIFO storing mechanism
FEMP=1, FFUL=0 FEMP=0, FFUL=0 FEMP=0, FFUL=0 FEMP=0, FFUL=1 FEMP=0, FFUL=1

2) FIFO reading mechanism
Read out

FEMP=0

Data 1
Data 2

d

Detecting

edge

Falling

edge

Data 1 Data 1

Data in Data in Data in Data in

Read out

FEMP=0 FEMP=1

Data 2

Data 2

ID R

RRRRRR

MSB LSB

ADDRESS: 00FB
INITIAL VALUE: Undefined

D2D3D4D5D6D7 D0

H

RR

D1

Figure 15-6 INT. interval determination FIFO data

register

Data 1
Data 2
Data 3
Data 4

Data 5
Data 6

Data 1
Data 2
Data 3
Data 4

Data 5
Data 7

Data 6 will be erased.
FOE=1 (Over run error)

Figure 15-7 Example for FIFO operating mechanism

62 November 2001 Ver 1.1

16. Buzzer driver

HMS81C4x60

The Buzzer driver circuit is shown in Figure 16-1.
The Buzzer driver circuit consists of the 6bit counter, 6bit

comparator, Buzzer data register BUR(00EE

). The BUR

H

Data Bus

8

BUR [EEH]

PWMCR1

PS7
PS8
PS9
PS10

MUX

BUCK

10

BU5 BU4 B U3 BU2 BU1 BU0

6bit Comparator

00
01
10
11

TMR1 BUZ EN5 EN4 EN3 EN2 EN1 EN0

6bit counter

BUCK

Figure 16-1 Block Diagram of Buzzer driver circuit

Control

register controls source clock and output frequency.
The more details about registers are shown Figure 16-2 .

BUR write

6

Output

clear

6

clear

Generator

BUZZ

3. Set BUZ bit for output enable.

The HMS81C4x60 contains a Buzzer driver module.

1. Select an input clock among PS7~PS10 by set the
BUCK1~0 of BUR.

BUCK1 BUCK0 Clock source

0 0 PS7
0 1 PS8
1 0 PS9
1 1 PS10

2. Select output frequency by change the BU5~0.
Output frequency = 1 / (PSx × BUy × 2) Hz.
x=7~10, y=5~0
See example Table 16-1.

Note: Do not select 00

to BU5~0. It means counter stop.

H

4. Output waveform is rectag le cl ock which has 50 % dut y.

5. You can use this clock for the other purposes.

Buzzer data Register

W

WWW

BUR

PWM control Register 1

PWMCR1

BUCK1 BUCK0

Input select

RW RW RW RWRW

TMR1 BUZ EN5 EN4 EN3 EN2 EN1 EN0

BU5

RW RW RW

WWWW

Buzzer count data

R36/Buzz select
0: R36
1: Buzz output

Figure 16-2 Buzzer driver Registers

ADDRESS : 0EE
RESET VALUE : ???? ????

BU2BU3BU4 BU0

BU1

ADDRESS : 0EA
RESET VALUE : 0000 0000

H

H

b

b

November 2001 Ver 1.1 63

HMS81C4x60

BUR5~0 Output frequency (KHz)

Dec Hex

1

01

2

02

3

03

4

04

5

05

6

06

7

07

8

08

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63

09
0A
0B
0C
0D
0E

0F

10

11

12

13

14

15

16

17

18

19
1A
1B
1C
1D
1E

1F

20

21

22

23

24

25

26

27

28

29
2A
2B
2C
2D
2E

2F

30

31

32

33

34

35

36

37

38

39
3A
3B
3C
3D
3E

3F

PS7

(32µS)

31.25

15.625

10.436

7.813

6.25

5.208

4.464

3.907

3.472

3.125

2.841

2.604

2.404

2.242

2.083

1.953

1.838

1.736

1.644

1.562

1.438

1.420

1.359

1.302

1.25

1.202

1.158

1.116

1.078

1.042

1.008

0.976

0.947

0.919

0.893

0.868

0.845

0.822

0.801

0.781

0.762

0.744

0.727

0.710

0.694

0.679

0.665

0.651

0.638

0.625

0.613

0.601

0.590

0.579

0.568

0.558

0.548

0.539

0.530

0.521

0.512

0.504

0.496

PS8

(64µS)

62.50

31.25

20.872

15.626

12.50

10.416

8.928

8.814

6.942

6.25

5.682

5.208

4.808

4.484

4.166

3.906

3.676

3.472

3.288

3.124

2.876

2.840

2.718

2.604

2.50

2.404

2.316

2.232

2.156

2.084

2.016

1.952

1.894

1.838

1.786

1.736

1.690

1.644

1.602

1.562

1.524

1.488

1.454

1.420

1.388

1.358

1.33

1.302

1.276

1.25

1.226

1.202

1.18

1.158

1.136

1.116

1.096

1.078

1.06

1.042

1.024

1.008

0.992

PS9

(128µS)

125.0

62.5

41.744

31.252

25.0

20.832

17.858

17.628

13.884

12.5

12.364

10.416

9.616

8.968

8.332

7.812

7.342

6.944

6.576

6.248

5.752

5.680

5.436

5.208

5.0

4.808

4.632

4.464

4.302

4.168

4.032

3.904

3.788

3.676

3.552

3.472

3.380

3.288

3.204

3.124

3.048

2.978

2.908

2.840

2.776

2.706

2.66

2.604

2.542

2.5

2.452

2.404

2.36

2.316

2.272

2.232

2.192

2.156

2.12

2.084

2.048

2.016

1.984

PS10

(256µS)

250.0

125.0

83.488

62.504

50.0

41.664

35.716

35.256

27.768

25.0

24.728

20.832

19.232

17.936

16.664

15.624

14.684

13.888

13.152

12.496

11.504

11.360

10.872

10.416

10.0

9.616

9.262

8.928

8.604

8.336

8.064

7.808

7.576

7.352

7.104

6.944

6.760

6.576

6.408

6.248

6.096

5.956

5.816

5.680

5.552

5.412

5.320

5.208

5.184

5.0

4.904

4.808

4.720

4.632

4.544

4.464

4.384

4.312

4.24

4.168

4.096

4.032

3.968

Table 16-1 . Example for fex=4MHz

64 November 2001 Ver 1.1

17. On Screen Display (OSD)

HMS81C4x60

The HMS81C4x60 can support 512 OSD chacters and font
size is used 12×10, 12×12, 12×14, 12×16, 16×18. It can
support 48 character columns and 2 line buffers resp ective­ly and also support full screen OSD whe n use interrupt.
Each characters have bit plane of 24bit and support at­tribute with OSD line and full screen OSD respectively.

Line 1,2 Attribute,
Position register

L1ATTR [AF0H]
L1VPOS [AF1
L2ATTR [AF3H]
L2VPOS [AF4H]

OSD Control
Circuit

Line register

OSDLN [AE5H] OSDCON1 [AE0H] OSDCON2 [AE1H]

]

H

Horizontal position register

LHPOS [AE6H]

Full screen control
register

OSD circuit consists of the Position attribute register, Line
register, Full screen screen control register, I/O polarity
register, font ROM, VRAM, etc. On Screen Display block
diagram is shown in Fig ure 17-1 and the more detai ls about
display characters are shown in Figure 17-2.

Display On/Off Control
register

Field detection register

FDWSET [AE3H]

Edge color register

EDGECOL [AE4

]

H

I/O Porarity Rigister

OSDCON3 [AE2H]

DACColor Pallet

R
G
B

HSYNC
VSYNC

Font ROM

Synchronization
Circuit

VRAM

Output

OSD Generation Circuit

dot clock

Xin

PLL

Control
Circuit

Figure 17-1 Block Diagram of On Screen Display circuit

YS

YM

November 2001 Ver 1.1 65

HMS81C4x60

[12 × 10 Character Font]

[12 × 12 Character Font]

- italic (only 12 × 12 mode can be supported)

[12 × 14 Character Font]
Foreground Character

- 512 color (8 pallet)

- color selecting : VRAM n-character bit 19~16
Background

- 512 color (8 pallet)

- color selecting : VRAM n-character bit 23~20
Foreground Character outline

- setting by LnATTR register

- color selecting : EDGECOL register

[12 × 16 Character Font]
Character shadow

- setting by LnATTR register and VRAM n-character bit 9

- color selecting : EDGECOL register
Background shadow color

- setting by VRAM n-character bit 15~12

- color selecting : EDGECOL register

- 512 color (8 pallet)

[16 × 18 Character Font]
OSD background shadow

- Character flash

- background underline

Figure 17-2 OSD Character Font Example

66 November 2001 Ver 1.1

17.1 Feature of OSD

HMS81C4x60

The Feature of OSD shown in below.

- Font pixel matrix

: 12×10, 12×12, 12×14, 12× 16, 16× 18 dots

- The number of font pattern

: 512 fonts

- Display ability

: 48Character × n lines (multilined by OSD interrupt)

- 8 foreground pallet of 512 colors for each character

- 8 background pallet of 512 colors for each character

- Full screen 8 background color

17.2 OSD Registers

R/W R/W R/W R/W R/W R/W

OSDCON1

MSB LSB

DLINEPRSCNFSBC0FSBC1FSBC2FSBC3 STOCK

- Character size
: 3 fonts(2 times, 1.5 times, 1 times)

- Progressive scan line switch

- Attribute

: Outline, Shadow, Rounding

- RGB DAC

: 8 level each color

- Display clock frequency

: 12MHz ~ 64MHz

R/W R/W

DDCLK

ADDRESS: 0AE0
INITIAL VALUE: 0000 0000

Stop OSD clock

0 :Release OSD clock
1 : Stop OSD clock

Double dot clock mode

0 : Normal
1 : Double

Double scan line mode

0 : Normal
1 : Double

Progressive scan line mode

0 : Interace mode
1 : Progressive mode

Full screen background color register

0000 : Transparency
0001 : Half blank
0010 : white
0011 : Black
0111 ~ 0100 : Reserved
1000 : color 0
1001 : color 1
1010 : color 2
1011 : color 3
1100 : color 4
1101 : color 5
1110 : color 6
1111 : color 7

H

b

Figure 17-3 OSD Control Registers - 1

OSDCON1

bit 0: STOCK
It stop or start OSD clock. If oscillation is stoped, IC’s

power consumption is decreased.
bit 1: DDCLK

If you set this bit to 1, OSD input clock is divided by two ,
than it makes OSD horisontal image size as doubled.

bit 2: DLINE
If you set this bit to 1, OSD vertical scan co unter input

clock is doubled from normal state. It makes OSD vertical

November 2001 Ver 1.1 67

HMS81C4x60

image size as doubled.
bit 3: PRSCN
It control progressive scan line mode.
bit clear than interace mode and bit set than processive

mode.

R/W R/W R/W R/W R/W R/W

OSDCON2

MSB LSB

FS0FS1FS 2FS 3OBGWFLART OSDON

bit 7~4: FSBC3 ~ FSBC0
It controls full screen background color as figure shows.

NOTE:

Data slicer operate when OSDCON1.PRSCN(0AE0.3) bit of OSD register is
cleared. Namely, it operate interace scan display mode.

R/W R/W
OLN

ADDRESS: 0AE1
INITIAL VALUE: 0000 0000

On/off of all OSD

0 :Off
1 : On

On OSD line1 and line2

0 : Off OSD line
1 : On OSD line

Font size

0000 : 12 × 16
0001 : 12 × 14
0010 : 12 × 12
0011 : 12 × 10
0111 ~ 0100 : Reseved
1000 : 16 × 18
1111 ~ 1001 : Reserved

12/14 dot background width of 1 OSD character

0 : 12 dot
1 : 14 dot

Flash rate when closed caption decoder is used

0 : 32 Vsync is one period
1 : 64 Vsync is one period

H

b

Figure 17-4 OSD Control Register - 2

OSDCON2

bit 0: OSDON
It controls OSD, Full screen background at once. It does

not affect anything to Vsync interrupt and OSD interrupt,
etc.

bit 1: ONL
It controls OSD line1 and line2 on/off. If its value is 1,

OSD line is on.
bit 2 ~ 5: FS0 ~ FS3

It controls OSD font size.
bit 6: OBGW
It controls dot background width. Default width is 12dots.

If its value is set, 2 dot s (backgro und col or) are added both
left and right side of character.

bit 7: FLRAT
It controls OSD flash rate when closed caption decoder is

used. Bit clear than 32 Vsync is one period and bit set than
64 Vsync is one period.

68 November 2001 Ver 1.1

HMS81C4x60

WWWWWW

OSDCON3

SELCK1

MSB LSB

Figure 17-5 I/O Polarity(Initial) Register

OSDCON3

bit7~0 : SELCK1, SELCK0, ONDAC, POLRG, POLYM,
POLYS, POLHS, POLVS

WW

POLHS POLV SPOLYSPOLYMPO LRGONDACSELCK2

ADDRESS: 0AE2
INITIAL VALUE: 0000 0000

Vsync polarity

0 : Active low
1 : Active high

Hsync polarity

0 : Active low
1 : Active high

YS polarity

0 : Active low
1 : Active high

YM polarity

0 : Active low
1 : Active high

RGB pin polarity

0 : Active low
1 : Active high

On/Off of RGB DAC

0 : Off
1 : On

Select dot clock

00 : Clock from DLL
01 : Clock from LC OSC for EVA only
10 : Clock 1 for test
11 : Reserved

H

b

It controls Hsync/Vsync polarity, YS/YM polarity, RGB
polarity, RG B D AC on/off and select dot clock.

WWWWWW

FDWSET

MSB LSB

Field Detection Window:

( {1’b0, (FMIN2 ~ FMIN0)} < hptr[10:7] < (FMAX3 ~ FMAX0))

FMIN2DBFLGFMAX0FM AX1FMAX2FM AX3 FMIN0

FDWSET

FDWSET (Field Detection Window Setting) register de­tects the begin of Vsync(Vertical Sync.) signal and distin­guishs its current field is Even field or Odd field.

The region of FMIN[2:0] ~ FMAX[3:0] is field detection

WW

FMIN1

ADDRESS: 0AE3
INITIAL VALUE: 0111 1010

Field Detection Min. Pointer
Field Detection Polarity

0 : Masking between Min. and Max.
1 : Detect between Min. and Max.

Field Detection Max. Pointer

H

b

window.
FMAX[3:0] can divide the region between Hsync(Hori-

zontal Sync.) by 16 windows. You can assume there is 4
bit horizontal counter, for example HCOUNT[3:0](hptr[10
:7]) which count 0~15.

November 2001 Ver 1.1 69

HMS81C4x60

Ex1: VSync(Odd)

Ex2: VSync(Even)

HSync

FMIN

If the start of Vsync is detected at the window, next field is
even. Else if Vsync is d etected another r egion o f th e win­dow, next field is odd.

It means start of Vsync is detected during FMIN[2:0] <
HCOUNT[3:0] < FMAX[3:0] and DBFLG value is 0, it
distinguish odd field.

And, start of Vsync is detected during FM IN[2:0] <
HCOUNT[3:0] < FMAX[3:0] and DBFLG value is 1, it
distinguish even field.

FMAX

Figure 17-6 FDWSET detection region

R/W R/W R/W R/W R/W R/W

EDG2C3

EDGECOL

MSB LSB

EDG2C2 EDG2C1 EDG2C0 EDG1C3 EDG1C2 EDG1C1 EDG1C0

FMIN[2:0], FMAX[3:0] are compared with the horizontal
counter in OSD block.

R/W R/W

ADDRESS: 0AE4
INITIAL VALUE: 1000 0111

Edge 1 color of shadow, outline, edge

0000 : Transparency
0001 : Reserved
0010 : white
0011 : Black
0100 : Same as foreground character color
0111 ~ 0101 : Reserved
1000 : color 0
1001 : color 1
1010 : color 2
1011 : color 3
1100 : color 4
1101 : color 5
1110 : color 6
1111 : color 7

Edge 2 color of shadow, outline, edge

0000 : Transparency
0001 : Reserved
0010 : white
0011 : Black
0100 : Same as foreground character color
0111 ~ 0101 : Reserved
1000 : color 0
1001 : color 1
1010 : color 2
1011 : color 3
1100 : color 4
1101 : color 5
1110 : color 6
1111 : color 7

H

b

Figure 17-7 Character, Window color Register

EDGECOL

bit 7 ~ bit 0 : EDG1C0,EDG1C1,EDG1C2,EDG1C3
EDG2C0,EDG2C1,EDG2C2,EDG2C3

It control shadow color, outline color and edge color.
Low 4 bits controls edge 1 shadow, outline color and high

4 bits controls edge 2 shadow, outline color.

70 November 2001 Ver 1.1

HMS81C4x60

CHEDCL

WWWWWW

MSB LSB

WW

SHEC2SHEC3W INC0W INC1WINC2WINC3 SH EC0

SHEC1

Figure 17-8 Scroll window color Register

ADDRESS: 0AE5
INITIAL VALUE: Undefined

Foreground shadow, outline edge color

0000 : Transparency
0001 : Reserved
0010 : white
0011 : Black
0100 : Same as foreground character color
0111 ~ 0101 : Reserved
1000 : color 0
1001 : color 1
1010 : color 2
1011 : color 3
1100 : color 4
1101 : color 5
1110 : color 6
1111 : color 7

Scroll window background color

0000 : Transparency
0001 : Reserved
0010 : White
0011 : Black
0111 ~ 0100 : Reserved
1000 : Color 0
1001 : Color 1
1010 : Color 2
1011 : Color 3
1100 : Color 4
1101 : Color 5
1110 : Color 6
1111 : Color 7

H

CHEDCL

bit 7 ~ bit 0 : SHEC0,SHEC1,SHEC2,SHEC3
WINC0,WINC1,WINC2,WINC3
It controls foreground shadow and ou tline edge color and

RRRRRR

OSDLN

MSB LSB

Figure 17-9 OSD Line Register

OSDLN

bit 4 ~ bit 0 : VLR4 ~ VLR0
It shows current display OSD line from 1 to 31.

scroll window background color.
Low 4 bits controls scroll window background color and

high 4 bits controls foreground shadow outline edge color.

RR

VLR2VLR3VLR4---VLR0

VLR1

LHPOS

MSB LSB

ADDRESS: 0AE6
INITIAL VALUE: ---0 0000

OSD line being displayed

00000 : Not displayed any OSD line yet after Vsync
00001 : 1st line OSD being displayed

.......

.......

11111 : 31st line OSD being displayed

WWWWWW

OSD Line Horizontal Posi tio n 00H~ FF

H

H

ADDRESS: 0AE7
INITIAL VALUE: Undefined

LH2LH3LH4LH5LH6LH7 LH0

LH1

H

WW

H

November 2001 Ver 1.1 71

HMS81C4x60

Figure 17-10 OSD Line Horizontal Position Register

LHPOS

bit 7 ~ bit 0 : LH7 ~ LH0

WWWWWW

DLLMOD

MSB LSB

RRRRRR

DLLTST

MSB LSB

Figure 17-11 DLL mode Register

DLLMOD

bit 2 ~ 0 : If you set this bit to 1, the status is ch anged test
mode.

bit 7 ~ bit 3 : DCKF4 ~ DCKF0
It control dot clock frequency.
Dot clock frequency is as below.

Value

DCKF4 DCKF4 DCKF4 DCKF4 DCKF4

0 0 0 0 0 stop dll clock
00001reserved
00010reserved

0001164.00MHz

0010051.20MHz

0010142.67MHz

0011036.57MHz

0011132.00MHz

0100028.44MHz

0100125.60MHz

0101023.27MHz

Frequency

It control OSD line horizontal position. Position value
from 00h to FFh.

WW

-DCKF0DCKF1DCKF2DCKF3DCKF4 -

-

RR

-------

-

DCKF4 DCKF4 DCKF4 DCKF4 DCKF4

0101121.33MHz

0110019.69MHz

0110118.29MHz

0111017.07MHz

0111116.00MHz

1000015.05MHz

1000114.22MHz

1001013.47MHz

1001112.80MHz

1010012.19MHz

1010111.63MHz

1011011.13MHz

1011110.67MHz
11000reserved
11001reserved

ADDRESS: 0AE8
INITIAL VALUE: 0000 0000

1 : OSD test mode

1 : Dll test mode
1 : Reset clock count test mode

Dot clock frequency

ADDRESS: 0AE9
INITIAL VALUE: --00 0000

Value

H

H

H

H

Frequency

Table 17-1 Dot Clock Frequency (fex=4Mhz)

72 November 2001 Ver 1.1

HMS81C4x60

L1ATTR

bit 0 : L1V8

L1ATTR

WWWWWW

MSB LSB

WW

CSZ10CSZ11ENSH1ENOL1WDSL1OBGH1 L1V8

FSC1

Figure 17-12 OSD line 1 attribute register

bit 4: ENSH1
It enables line 1’s character(foreground) shadow.

ADDRESS: 0AEA
INITIAL VALUE: 0000 0000

OSD line 1 vertical position (bit 8)
Foreground sh adow or outline color select

0 : Edge 1 color
1 : Edge 2 color

Size of character

00 : Normal
01 : 1.5 times
10 : 2 times
11 : Reserv ed

Enable/disable of shadow

0 : Disable
1 : Enable

Enable/disable of outline

0 : Disable
1 : Enable

Width of shadow, outline

0 : 1 dot
1 : Proportional to character size

OSD chraracter background height

0 : font height
1 : font height + 2

H

H

It is equivalent to L1VPOS’s most significant bit(bit 8).
See more details in L1VPOS.

bit 1: FSC1
It selects character outline and shadow color. If it is 1, it se-

lect EDGE2 color of EDGECOL register. Or not, it select
EDGE1 color. According to EDGECOL register and this
bit character and shadow colors are selected simulteneous­ly

bit 3~2: CSZ11~CSZ10
It controls OSD ch aracter’s size ( norm al, 1.5 times, 2

times). You can use this register and DDCLK, DLINE bit,
horizontal / vertical size can be controlled (x1, x1.5, x2).

bit 5: ENOL1
It enables line 1’s character(foreground) outline.
bit 6: WDSL1
It shows thickness of lin e 1’s shadow an d outl ine.This bit

is set than one dot and bit clear is proportional to character
size. If only character size is 2 times, 2 times per vertically
and horizontally. In case 1 dot width would be enable.

bit 7: OBGH1
It controls character’s b ackground heig ht. Defaul t height is

16dots. If its value is set, 2 dots (background color) are
added both top and bottom side of character.

November 2001 Ver 1.1 73

HMS81C4x60

WWWWWW

L1EATR

MSB LSB

L1EATR

It shows OSD line 1 extend attribute register.

L1VPOS

WWWWWW

MSB LSB

OSD line 1 vertical position 000H~ 1FFH

ADDRESS: 0AEC
INITIAL VALUE: Undefined

WW

LIV2LIV3LIV4LIV5LIV6LIV7 LIV0

LIV1

WW

SEL1FLSEL1OWSEL1UL---SEL1SH

SEL1IT

ADDRESS: 0AEB
INITIAL VALUE: Undefined

Select shadow/round of line 1 each character when
VRAM.ENRND is set.

0 : round character
1 : shadow character

Select italic/upper edge of line 1 each character.
Italic character can be displayed only when character
size is 1, 1.5 times, and VRAM.BSU is set.

0 : Upper edge character
1 : Italic character

Select flash/left edge of line 1 character when
VRAM.BSL is set.

0 : Left edge character
1 : Flash

Select OSD/window when display. If this bit is 0,
background window would be displayed.

0 : Background window selected
1 : OSD line selected

Select underline /lower edge of line 1 each character

0 : Underline
1 : Lower edge line

H

L1ATTR.

L2EATR

H

WWWWWW

MSB LSB

ADDRESS: 0AEE
INITIAL VALUE: Undefined

SEL2FLSEL2OWSEL2UL--- SEL2SH

H

WW

SEL2IT

L2EA TR

L1VPOS

It shows OSD line 2’s extened attribute register.

It shows OSD line 1’s vertical position in 9bit format
(LIV8 + L1VPOS, 000 ~ 1FF

L2ATTR

WWWWWW

MSB LSB

).

H

ADDRESS: 0AED
INITIAL VALUE: Undefined

WW

CSZ21CSZ22ENSH2ENO L2WDSL2OBG H2 L2V2

FSC2

L2VPOS

WWWWWW

H

MSB LSB

ADDRESS: 0AEF
INITIAL VALUE: Undefined

L2V2L2V3L2V4L2V5L2V6L2V7 L2V0

H

WW

L2V1

L2VPOS

It shows OSD line 2’s vertical position. Its functio n is the
same as L1VPOS.

L2ATTR

It shows OSD line 2’s attributes. Its function is the same as

74 November 2001 Ver 1.1

HMS81C4x60

WINSH

WWWWWW

WINSH7

WINSH6 W INSH5 W INSH4 WINSH3 WINSH2 WINSH1 WINSH0

MSB LSB

OSD scroll window start horizontal position

ADDRESS: 0AF0
INITIAL VALUE: Undefined

H

WW

WINSH

It shows OSD scroll window start horiz ontal position.

WINSY

WWWWWW

WINSY7

WINSY6 WINSY5 WINSY4 WINSY3 WINSY2 WINSY1 WINSY0

MSB LSB

OSD scroll window start vertical position

ADDRESS: 0AF1
INITIAL VALUE: Undefined

H

WW

WINSY

It shows OSD scroll window start vertical position.

WINEH

WWWWWW

WINEH7

WINEH6 W INEH5 W INEH4 W INEH3 W INEH2 W INEH1 WINEH0

MSB LSB

OSD scroll window end horizontal position

ADDRESS: 0AF2
INITIAL VALUE: Undefined

H

WW

WINEH

It shows OSD scroll window end horizontal position.

WINEY

WWWWWW

WINEY7

WINEY6 WINEY5 WINEY4 WINEY3 WINEY2 WINEY1 WINEY0

MSB LSB

OSD scroll window end vertical position

ADDRESS: 0AF3
INITIAL VALUE: Undefined

H

WW

VCNT

RRRRRR

MSB LSB

Current scan line line vertical position [6:0]

ADDRESS: 0AF4
INITIAL VALUE: Undefined

VCNT6VCNT6VCNT6VCNT6VCNT6VCNT6 FLDID

Current display field

0 : Odd field
1 : Even field

H

RR

VCNT6

VCNT

It shows Vsync count register and counted by pixel clock.
VCNT counter clock start at Vsync start edge.

HCNT

RRRRRR

MSB LSB

Horizontal counter hptr[10:3]

ADDRESS: 0AF5
INITIAL VALUE: Undefined

HCNT2HCNT3HCNT4HCNT5HCNT6HCNT7 HCNT0

H

RR

HCNT1

HCNT

It shows Hsync count register and counted by pixel clock.
HCNT counter clock start at Hsync start edge.

CULTAD

WWWWWW

MSB LSB

Normal/Test mode select

00 : Normal mode
01 ~ 11 : Test mode

ADDRESS: 0AF9
INITIAL VALUE: Undefined

-------

1.5 times character mode

0 : line double mode 1.5 times
1 : field interleaving mode 1.5 times

H

WW

FIL15

CULTAD

It shows normal and test mode and 1.5 times mode.

WINEY

It shows OSD scroll window end vertical p os ition.

November 2001 Ver 1.1 75

HMS81C4x60

17.3 VRAM

VRAM contains a OSD li ne buffer, 48 character’s at­tributes.

Each character’s attribute is constructed with 3 bytes, it
contains color data for background, shadow, o utline, char ­acter and character number ( 000

~ 1FFH, 512 characters

H

), etc.

Line

00~08

Character

No.

No.

add. No.

1

46 AAD A6D A2D
47 AAE A6E A2E
48 AAF A6F A2F

2

46 BAD B6D B2D
47 BAE B6E B2E
48 BAF B6F B2F

Table 17-2 VRAM memory map

Bit

09 ENRND

0A BSCUL

Name Function

CG8

~CG0

Address (bit 47~0)

Hexa decimal

1A80A40A00
2A81A41A01
3A82A42A02

::::

1B80B40B00
2B81B41B01
3B82B42B02

::::

Character font code

1FFh ~ 000h

Round enable/disable

0 : disable

1 : enable

Edge color of upper and left

background shadow edge

0 : edge 1 color
1 : edge 2 color

Bit

No.

0B BSCDR

0C BSU

0D BSD

0E BSL

0F BSR

10~13

14~17

Name Function

FC3

~FC0

BC3

~BC0

Edge color of lower and right

background shadow edge

0 : edge 1 color
1 : edge 2 color

Background shadow upper eddge

control/italic depend on

LxEATR.SELxIT

0 : disable

1 : enable

if(LxEATR.SELxIT == 0) backgro und

shadow upper edge enable

else(LxEATR.SELxIT == 1) italic

enable

Background shadow lower edge

control/underline depend on

LxEATR.SELxUL

0 : disable

1 : enable

if(LxEATR.SELxUL == 0)

background shadow lower edge

enable

else(LxEATR.SELxUL ==

1)underline enable

Background shadoww left edge

control/flash(blInking) depend on

LxEATR.SELxFL

0 : disable

1 : enable

if(LxEATR.SELxFL == 0) background

shadow left edge enable

else(LxEATR.SELxFL == 1)

flash(flicking) enable

Background shadow right edge

control

0 : disable

1 : enable

Foreground color for character (11

colors)

Background color for character (12

colors)

Table 17-3 VRAM attribute

76 November 2001 Ver 1.1

HMS81C4x60

Composition of VRAM

LINE 1
(page A)

LINE 2
(page B)

CG8

0A80 0A40 0A00
0A81 0A41 0A01

0A82 0A42 0A02
: : :

0AAF 0A6F 0A2F

0B80 0B40 0B00
0B81 0B41 0B01

0B82 0B42 0B02
: : :

0BAF 0B6F 0B2F

CG2CG3CG 4CG5CG6CG7 CG0

BSCULBSCDRBSUBSDBSLBSR CG 8

Character 1 Attr.

Character 2 Attr.
Character 3 Attr.

Character 48 Attr.

Character 1 Attr.

Character 2 Attr.
Character 3 Attr.

Character 48 Attr.

CG1

ENRND

FC2FC3BC0BC1BC2BC3 FC0

FC1

RESET VALUE: Undefined

Character font address (512 fonts)

see table 17-3 VRAM attribute

Character color select (11 characters)

0000 : Transparency
0001 : Reserved
0010 : White
0011 : Black
0111 ~ 0100 : Reserved
1000 : Color 0
1001 : Color 1
1010 : Color 2
1011 : Color 3
1100 : Color 4
1101 : Color 5
1110 : Color 6
1111 : Color 7

Background color select (12 characters)

0000 : Transparency
0001 : Reserved
0010 : White
0011 : Black
0111 ~ 0100 : Reserved
1000 : Color 0
1001 : Color 1
1010 : Color 2
1011 : Color 3
1100 : Color 4
1101 : Color 5
1110 : Color 6
1111 : Color 7

November 2001 Ver 1.1 77

HMS81C4x60

17.4 Character ROM

The HMS81C4x60 Character ROM are used 512 types of
Font Dot Pattern data. As displayed one ch aracter, need 12
× 10 ~ 16 × 18bits Dot Pattern data.

1. Each horizontal data (12dots) needs 2bytes ROM.

2. One character is constructed with 16 horizontal data to
vertically. As a result, one character needs 32bytes (2 × 16
bytes).

3. HMS81C4x60 contains 512 characters. Total Font
ROM memory size is calculated as 16,384bytes ( 32bytes
/ character × 512 characters )

4. Font ROM memory is located from 10000

~ 17FFFH,

H

this memory can not be accessed by user program.

Charact

er code

000

H

001

H

002

H

Upper 8bit Lower 8bit

14000H ~ 14011
14020H ~ 14031
14040H ~ 14051

:: :

xyz

(14000H + xyz0H) ~

H

(14000H + 2*xyzFH)

:: :
1FD
1FE

1FF

17FA0H ~ 17FB1

H

17FC0H ~ 17FD1

H

17FE0H ~ 17FF1

H

Address range

10000H ~ 10011

H

10020H ~ 10031

H

10040H ~ 10051

H

(10000H + xyz0H) ~
(10000H + 2*xyzFH)

13FA0H ~ 13FD1

H

13FC0H ~ 13FD1

H

13FE0H ~ 13FF1

H

H

H
H

H

H

H

5. A character’s address and dot position in font ROM is
described in Figure 17-13.

12 × 1416 × 18

Left
address

14060

14061
14062
14063

14064

14065
14066
14067

14068

14069
1406A
1406B

1406C

1406D
1406E
1406F

14070

14071
14072
14073

14074

14075
14076
14077

14078

14079
1407A
1407B

1407C

1407D
1407E
1407F

Figure 17-13 Character Dot Pattern

Right
address

10060
10061
10062
10063
10064
10065
10066
10067
10068
10069
1006A
1006B
1006C
1006D
1006E
1006F
10070
10071
10072
10073
10074
10075
10076
10077
10078
10079
1007A
1007B
1007C
1007D
1007E
1007F

Table 17-4 Font ROM memory map

78 November 2001 Ver 1.1

17.5 Color Look Up Table

W

WWWW

7

RED0

<0AD0H>

RED1

>

<0AD1

H

RED2

>

<0AD2

H

GREEN0

>

<0AD3

H

GREEN1
<0AD4

>

H

GREEN2
<0AD5

>

H

BLUE0

<0AD6

>

H

BLUE1

<0AD7

>

H

BLUE2

<0AD8

>

H

Composition of color 7

Composition of color 6

Composition of color 5

Composition of color 4

6543

R60 R50 R40 R30 R20 R10 R00

R07

R62 R51 R41 R31 R21 R11 R01

R71

R62 R52 R42 R32 R22 R12 R02

R72

G60 G50 G40 G30 G20 G10 G00

G70

G61 G51 G41 G31 G21 G11 G01

G71

G62 G52 G42 G32 G22 G12 G02

G72

B60 B50 B40 B30 B20 B10 B00

B70

B71 B61 B51 B41 B31 B21 B11 B01

B62 B52 B42 B32 B22 B12 B02

B72

Composition of color 3
Red : {R02, R01,R00}
Green : {G02,G01,G00}
Blue : {B02,B01,B00}

RESET VALUE : Undefined

WWW

210

Composition of color 0

Composition of color 1

Composition of color 2

HMS81C4x60

[Example] Color data table

Color_example_table:
db 0000_0000b ;color 0 = Gray
db 0000_0011b ;color 1 = Red
db 0010_1011b ;color 2 = Green
;
db 0000_0000b ;color 3 = Yellow
db 0000_0101b ;color 4 = Blue
db 0100_1101b ;color 5 = Magenta
;
db 0000_0000b ;color 6 = Cyan
db 1001_0001b ;color 7 = half blue
db 1111_0001b

Figure 17-14 Color look up table

November 2001 Ver 1.1 79

HMS81C4x60

18. DATA SLICER

HMS81C4x60 supports Clos ed Caption decodi ng standard
with 0.5MHz data rate. Also it can capture 4 horizontal
lines information per frame, because it has 4 horozontal
lines capture memory. It is able to select even or odd field

18.1 Data Slicer Circuit

Figure 18-1 shown the data slicer circuit.

SCAP

560pF

CVBS

0.47uF

Figure 18-1 Data Slicer Circuit

HMS81C4x60

18.2 Configuration of Data Slicer

Figure 18-2 shows the block diagram of the Data Slicer.

at one field interval. Data Slicer captures caption informa­tion from line 21 in vertical blanking interval of CVBS,
and stores these data to buffer memory.

CVBS signal is en tere d to CVBS p in via 0 .47uF capacit or.
The black level of signal is about 2V. SCAP pin is connect­ed to external 560pF capacitor which adjust the referance
voltage of comparator. Its slicer level is adapted to input
signal.

Run-in key timing
Sync-tip timing

Data capture
timing

CVBS

Data
Filter

Reference
Voltage

Figure 18-2 Data Slicer Block Diagram

This data slicer block separates caption information from
CVBS signal. Data slicer composes high speed comparator
and on-chip low pass filter. The outp ut data of comparator

Timing
Controller

Memory
Interface
Controller

CPU control

Slicer
Memory

is stored in memory through the filter and m emory inter­face controller, which should be decoded to caption data
by software. Slicer memory addressed 600h ~ 6FFh.

80 November 2001 Ver 1.1

18.3 Slicer Registers

HMS81C4x60

Slicer Control Register

Slicer Control Register is the specific control register,

R/W R/W R/W R/W R/W R/W

SLCON

MSB LSB

DEME1--SELCKRIKTST-SLON

Figure 18-3 Slicer Control Register

Slicer Information Register 0

Slicer Information Register 0 selects even or odd field

which select operating freque ncy of the slicer, slicer de­coding method and switch slicer on/off.

R/W R/W

DEME0

ADDRESS: 0BE0
INITIAL VALUE: 0000 0000

Slicer On/Off

0 : Slicer Off
1 : Slicer On

Decoding Method

00 : Normal
01 : Reserved
10 : Reserved
11 : Reversed

Slicer Clock

0 : Normal clock
1 : Test clock

RIK slicer test mode

00 : Normal clock
01 : Reserved
10 : Reserved
11 : Reserved

H

b

buffer of line 0 and slicer line 0 position. Also it is used to
select line number in Vertical blanking interval.

WWWWWW

SLINF0

MSB LSB

SLPOS0

Figure 18-4 Slicer Information Register 0

Slicer Information Register 1

Slicer Information Register 1 selects even or odd field

WWWWWW

SLINF1

MSB LSB

SLPOS1

Figure 18-5 Slicer Information Register 1

WW

LFC0

LFC0

ADDRESS: 0BE1
INITIAL VALUE: 0000 0000

Line0 enable

00 : disable all line 0
01 : reserved
10 : reserved
11 : enable all line 0 (even and odd field)

Slicer line 0 position

H

b

buffer of line 1 and slicer line 1 position. Also it is used to
select line number in Vertical blanking interval.

WW

LFC1

LFC1

ADDRESS: 0BE2
INITIAL VALUE: 0000 0000

Line 1 Field

00 : disable all line 1
01 : reserved
10 : reserved
11 : enable all line 1 (even and odd field)

Slicer line 1 position

H

b

November 2001 Ver 1.1 81

HMS81C4x60

Run-in key Start/End position Register

RIKST points the start postion of run-in key, it is delayed
from start edge of Hsync. RIKED points the end position
of run-in key, it is also delayed from start edge of Hsync.

WWWWWW

RIKST

MSB LSB

RIKST2RIKST3RIKST4RIKST5RIKST6RIKST7 RIKST0

Figure 18-6 Run-in key Start Position Register

WWWWWW

RIKED

MSB LSB

RIKED2RIKED3RIKED4RIKED5RIKED 6RIKED7 RIKED0

Figure 18-7 Run-in key End Position Register

Sync Start/End Position Register

Sync Start and End position Register are used to make
Sync tip window. Both timmings are counted up by

Both timmings are counted up by 8MHz clock. The refer­ance voltage of comparator is charged by external signal
during this time interval. Figure 18-6 and Figure 18-7
shows the RIK register’s configure.

WW

RIKST1

WW

RIKED1

ADDRESS: 0BE3
INITIAL VALUE: XXXX XXXX

Run-in key window start position

ADDRESS: 0BE4
INITIAL VALUE: XXXX XXXX

Run-in key window end position

H

b

H

b

16MHz clock. Figure 18-8 and Figure 18-9 shows the
Sync-tip register’s configur e.

SNCST

SNCED

WWWWWW

SNCST7 SNCST6 SNCST5 SNCST4 SNCST3 SNCST2 SNCST1 SNCST0

MSB LSB

WW

Figure 18-8 Sync-tip start position register

WWWWWW

SNCED7 SNCED6 SNCED5 SNCED4 SNCED3 SNCED2 SNCED1 SNCED0

MSB LSB

WW

Figure 18-9 Sync-tip end position register

ADDRESS: 0BE7
INITIAL VALUE: XXXX XXXX

Sync-tip window start position

ADDRESS: 0BE8
INITIAL VALUE: XXXX XXXX

Sync-tip window end position

H

H

b

b

82 November 2001 Ver 1.1

18.4 Data Sampling

HMS81C4x60

Line 21 Closed Caption signal

Figure 18-10 shows the closed caption signal. The signal
composes color burst, clock run-in, start bit(001), 16bit
ASCII data with 2 parity bit. Sliced raw datas are sampled
by 4MHz frequency.

[ CAPTIO N D ATA ]

TWO (7 BIT + PARITY )
CHARACTERS
( D ATA )

33.76us

3.972us

51.26us

61.342us

program
color
burst

CLOCK RUN IN

START BIT(001)

12.91us

Figure 18-10 Closed caption signal

Address assign

Table 18-1 shows the map of assigned buffer memory.

Setting Address

Interrupt occurrence

The slicer interrupt is occured after writing the sliced two
lines data to memory buffer.

Signal timing

Figure 18-11 shows an example of variable signals, which
includes Vsync(vertical Sync.), Hsync(horizontal Sync.),
CVBS(composit video in), SCAP(slicer capacitor), Run-in
key and Sync tip. Line 21 closed caption sign al run after
Vsync interrupt. The signal’s black(base) level voltage is
charged on Sync-tip switch-on period, and the re ferance
voltage of comparator is charged on RIK switch-on perid.
Because RIK time is related to SCAP voltage(comparator
referance voltage or slicer level ) which is charged by cl ock
run-in signal, user can adjust the slicer level by RIK time.
The sliced data is stored to RAM buffer. (0600h~ 06FFh)

First Line

Secont Line

Even Field 0600h ~ 063Fh

Odd Field 0640h ~ 067Fh

Even Field 0680h ~ 06BFh

Odd Field 06C0h ~ 06FFh

Table 18-1 Address assign

November 2001 Ver 1.1 83

HMS81C4x60

Vsync

5V

1

Hsync

CVBS

SCAP

RIK

Sync_tip

2

1 Hsync cycle

5V

5V

5V

2.5V
2V

line 21 signal

2.2V

0.5V

Slicer capacitor charging level

5V

3

4

Run-in key start/stop timming

0V

5V

Sync-tip start/stop timming

0V

Figure 18-11 Signal timing

[Example]

Initializing slicer register.

CCD_INIT: LDM SLINF0,#0011_0011b ; slicer line 21

LDM SLINF1,#0000_0000b ; no field
LDM RIKST,#01 ; run-in key start : 1 -> 0.125uS(8MHz)
LDM RIKED,#8Ch ; run-in key end : 8ch -> 17.5uS(8MHz)
LDM SNCST,#01 ; sync tip start : 1 -> 0.0625uS(16MHz)
LDM SNCED,#58h ; sync tip end : 58h -> 5.5uS(16MHz)
LDM SLCON,#01h ; normal clock, 16MHz, slicer start

84 November 2001 Ver 1.1

19. I2C Bus Interface

HMS81C4x60

The I2C Bus interface circuit is shown in Figure 19-1.
The multi-master I

tions circuit, conforming to the Phlips I

2

C Bus interface is a serial communica-

2

C Bus data trans­fer format. This interface, offering both arbitration lost
detection and a synchronous functions, is useful for the
multi-master serial communications.

SDA5 SDA4 SDA3 SDA2 SDA1 SDA0 RWb

SAD6

D6 D5 D4 D3 D2 D1 D0

D7

BB
Circuit

AL
Circuit

SDA

SCL

Noise
Elimination
Circuit

Noise
Elimination
Circuit

ICAR [D8H]

ICDR [D9H]

Data
Control
Circuit

Clock
Control
Circuit

This multi-master I

2

I

C address register, the I2C data shift regi ster, the I2C

clock control register, the I

2

C Bus interface circuit consists of the

2

C control register, the I2C sta-

tus register and other control circuits.
The more details about registers are shown Figure 19-2~

Figure 19-5.

Address

ICSR [00DA

ICCR [00DB

comparator

MST TRX BB PIN AL AD0 ADRb LRB

]

H

BSEL1

]

H

ACKb CCR2 CCR1 CCR0

BSEL1

Interrupt
Generation
Circuit

CCR3ESO

Clock division

IFI2CR

Clock Source

Figure 19-1 Block Diagram of multi-master I2C circuit

Control

2

The HMS81C4x60 contains two I

C Bus interface mod­ules. It supports multi-master function, so it contains arbi­tration lost detection, synchronization function,etc.

ITEM Function

Format

Philips
7bit addressing format

standard

I2C

2

I

C address register

It contains slave address (7bit) which is used during slave
mode and Read/Write

bit.

Bit 7 ~ 1 : Slave address 6~0

Note: Bit 7~1 (SAD6~0) store slave address. Th e ad dre ss
data transmitted fro m the mast er is compa red w ith th e con ­tents of these bits.

Master transmitter

Communication

mode

Master receiver
Slave transmitter
Slave receiver

November 2001 Ver 1.1 85

HMS81C4x60

The more details about its bits are shown Table 19-1.

ICAR

ADDRESS : 00D8

RW RW RW

SDA5 SDA4 SDA3 SDA2 SDA1 SDA0 RWb

SAD6

Slave address

RESET VALUE : 0000 0000

RW RW RW R

RW

H

Read/Write Bit

b

Figure 19-2 I2C address Register

I2C data shift register [ICDR]

2

C data shift register is an 8bit shift register to store

The I
received data and write transmit data.

When transmit data is written int o this regi ster, it is trans­fered to the outside from bit7 in synchronization with the
SCL clock, and each time one-bi t data is outp ut, the data of
this register are shifted one bit to the left. When data is re­ceived, it is input to this register from bit0 in synchroniza­tion with the SCL clock, and each time one-bit data is
input, the data of this register are shifted one bit to the left.

2

The I

C data shift register is in a write enable status only
when the ESO bit of the I
00DC

) is “1”. The bit counter is reset by a write ins truc-

H

tion to the I

2

I

C data shift register is always enabled reg ardless of the

2

C data shift register. Reading data from the

2

C control register (address

ESO bit value.

ICDR

ADDRESS : 00D9

RW RW RW RW RW RW RW RW

D6 D5 D4 D3 D2 D1 D0

D7

Shift left 1-bit each SCL

RESET VALUE : 0000 0000

Figure 19-3 Data shift register

H

b

I2C status register

2

C status register controls the I2C Bus interface sta-

The I
tus. The low-order 4bits are read only bits and the high-or­der 4bits can be read out and written to.

Bit

Name Function

No.

00: Slave / Receiver mode
01: Slave / Transmitter mode
10: Master / Receiver mode
11: Master / Transmitter mode

MST is cleared when

- After reset.

- After the arbitration lost is occured and
1 byte data transmission is finished.

7

MST

6

TRX

- After stop condition is detected.

- When start condition is disabled by
start condition duplication preventation
function.

TRX is cleared when

- After reset.

- When arbitration los t or stop condition
is occured .

- When MST is ‘0’, and start condition
or ACK non-return mode is detected.

BB(Bus busy)bit is 1 during bus is bu sy.

5BB

This bit can be written by S/W. its value
is ‘1’ by start condition, and cleared by
stop condition.

PIN(Pending Interrupt Not)bit is inter­rupt request bit.

2

If I

C interrupt request is issued, its

value is 0.

PIN is cleared when

- After 1 byte trasmissio n / rec eive is fin ­ished.

4PIN

PIN is set when

- After reset.

- After write instruction is excuted into

2

C data shift register ICDR.

I

- When PIN bit low, the output of SCL is
pulled down, So if you want to release
SCL, you must perform write instruction
CDR.

3AL

Arbitration lost detection flag.
If arbitration lost is det ect ed, AL=1, or 0.

General call detection flag.
If general call is detected, AD0=1, or

2AD0

not 0.
* General call : If received address is all
‘0’ . it is called general call.

Address represent flag

1 ADRb

0 : current contents is address
1 : current contents is data

86 November 2001 Ver 1.1

Bit

Name Function

No.

Last received bit.

0LRB

it is used for receive confirmation. If
ACK is returned, LRB=0, or not 1.

Table 19-1 Bit function

ICSR

ADDRESS : 00DA

RW RW RW RW R R R R

TRX BB PIN AL AD0 ADRb LRB

MST

RESET VALUE : 0001 0000

H

b

Figure 19-4 I2C status Register

I2C control register

It controls communication data format.
It controls SCL mode, SCL frequency, etc.
It contains 8bit data to transmit to external device when tr-

asmitter mode, or received 8bit data from external device
when receive mode.

ICCR

ADDRESS : 00DB

RW

RW RW RW

BSEL1

BSEL0

RW

ACKb

RESET VALUE : 0000 0000

RW RW RW

ESO CCR3 CCR2

CCR1 CCR0

Figure 19-5 I2C control Register

H

b

Bit

Name Function

No.

2

C connection control.

I

76BSEL1

BSEL0

00: No connection
01: SCL0, SDA0
10: SCL1, SDA1
11: SCL0, SDA0, SCL1, SDA1

5ACK

4 ESO

If acknowlege clock is r eturned, this bit
is 0, or not 1.

2

I

C Bus interface use enable flag
0: Disabled
1: Enabled

SCL Frequency selection

SCL frequency = f

Value

0000
0001
0010
0011

3

CCR3

2

CCR2

1

CCR1

0

CCR0

0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111

Not allowed
Not allowed

333.3KHz

222.2KHz

166.6KHz

133.3KHz

111.1KHz

95.2KHz

83.3KHz

74.1KHz

66.6KHz

60.6KHz

55.5KHz

51.3KHz

47.6KHz

44.4KHz

HMS81C4x60

/ (12 * CCR)

ex

f

= 4MHz

ex

Table 19-2 Bit function

SCL

PIN

2

C Request

I

Figure 19-6 Interrupt request signal generation timing

November 2001 Ver 1.1 87

HMS81C4x60

STAR T condition generation

2

When the ESO bit of the I
“1”, writing to the I

2

C status register will generate START

C control register (00DBH) is

condition. Refer to Figure 19-7 for the START condition
generation t i ming diagram .

ICSR write signal
(I2C status reg.)

SCL

SDA

BB (Bus busy) flag

Figure 19-7 START condition generation timing

t

SETUP

t

HOLD

t

BB

t

SETUPtHOLD

t

BB

: Setup time
: Hold time
: Set time for BB

STOP condition generation

Writing ‘C0h’ to ICSR will generate a stop condition,
w h e n E S O ( I C C R b i t 3 ) i s ‘ 1 ’

ICSR write signal
(I2C status reg.)

SCL

SDA

BB (Bus busy) flag

t

SETUP

t

HOLD

t

BB

t

SETUPtHOLD

t

: Setup time
: Hold time
: Set time for BB

BB

Figure 19-8 STOP conditio n ge nerati ng ti ming dia gram

START / STOP condition generation time is shown Table
19-3.

RESTART condition generation

RESTART condition’s setting sequence is as follo wings.

1. Write 020

2. Write slave address to I
00D9

H

3. Write 0F0

to I2C status register (ICSR, 00DAH)

H

2

C data shift registe r (ICDR,

)

to I2C status register (ICSR, 00DAH)

H

ITEM Timing SPEC.

Setup time

( t

SETUP

)

Hold time

( t

)

HOLD

Set/Reset time f or

BB flag ( t

BB

)

3.3uS (n=20cycles)

3.3uS (n=20cycles)

3.0uS (n=18cycles)

Table 19-3 Example time ( f

=4MHz )

ex

88 November 2001 Ver 1.1

HMS81C4x60

START / STOP condition detect

START / STOP condition is detected when Table 19-3 is
satisfied.

SCL release time

SCL

SDA (START)

SDA (STOP)

Master -> Slave (with 7bit address)

START

Slave addr.

7bit

R/W
(“0”)

t

SETUP

t

HOLD

ACK

t

SETUPtHOLD

: Setup time
: Hold time

ACK

Data

Data

ACK
/ACK

STOP

Figure 19-9 START / STOP condition detection timing

START / STOP detection time is showed Table 19-4.

ITEM Timing SPEC.

SCL release time > 2.0uS (n=12cycles)

Setup time > 1.0uS (n=6cycles)

Hold time > 1.0uS (n=6cycles)

Table 19-4 Example time ( f

=4MHz )

ex

Address data communication

The first transmitted data from master is compared with

2

C address register (ICAR, 00D8H). At this time R/W is

I
not compared but it determines next data opera tion. i.e,
transmitting or receiving data

Slave -> Master (with 7bit address)

START

Slave addr.

7bit

R/W
(“1”)

ACK

Data

ACK

Data

ACK

STOP

Figure 19-10 Address data communication format

Data block from master to slave
Data block from slave to master

November 2001 Ver 1.1 89

HMS81C4x60

20. WATCHDOG TIMER

The watchdog timer rapidly detects the CPU malfunction
such as endless looping caused by noise or the like, and re­sumes the CPU to the normal state.
The watchdog timer signal for detecting malfunction can
be selected either a reset CPU or a interrupt request.

Clock source
(BIT overflow : IFBIT)

[00D7

6-bit up- counter

WDT

clear

6-bit compare data

comparator

6

WDTCL[bit6]

WDTR[bit5~0]

WDTR

Watchdog Timer Register

]

H

Figure 20-1 Block Diagram of Watchdog Timer

Watchdog Timer Control

When the watchdog tim er is not being us ed for malfunc­tion detection, it can be used as a tim er to generate an in­terrupt at fixed intervals.

[00D6

IFWDT

enable

WDTON[bit5]

CKCTLR

Clock control Register

]

H

Watchdog Timer interrupt

to reset CPU

Figure 20-2 shows the watchdog timer control register.
The watchdog timer is automatically disab led aft e r reset.

The CPU malfunction is detected as setting the detection
time, selecting output, and clearing the binary counter. Re­peatedly clearing the binary count er with in th e settin g de­tection time.

If the malfunction occurs for any cause, the watchdog tim­er output will become active at the rising overflow from
the binary counters unless the binary counter are cleared.
At this time, when WDTON=1 a reset is generated, which
drives the RESET

pin low to reset the intern al hardware.
When WDTON=0, a watchdog timer interr upt (IFWDT) is
generated.

ADDRESS : 00D6
RESET VALUE : 0000 0000

WWWR

BTCL BTS2 BTS1 BTS0

ADDRESS : 00D7
RESET VALUE : -011 1111

Slave address

CKCTLR

WDTR

W

W

WDT ENP

ON CK

Watchdog timer On/Off control
0: Normal 6bit timer, Watchdog off
1: Watchdog timer

WWWWWWW

WDT

WDTR5 ~ 0

CL

Watchdog timer Clear
0: Watchdog timer free run
1: Watchdog timer clear and free run

Automatically cleared this bit after 1cycle

Figure 20-2 Watchdog timer register

H

H

b

b

90 November 2001 Ver 1.1

Example: Sets the watchdog timer detection time

HMS81C4x60

LDM WDTR,#01??????b ;

LDM CKCTLR,#00111???b ;

Within WDT
detection time

Within WDT
detection time

LDM WDTR,#01??????b ;
:
:
:
:
LDM WDTR,#01??????b ;
:
:
:
:
LDM WDTR,#01??????b ;

Enable and Disable Watchdog

Watchdog timer is enabled by setting WDTON (bit 5 in
CKTCLR) to "1". WDTON is initialized to "0" during re­set, WDTON should be set to "1" to operate after reset is
released.

Example: Enables watchdog timer reset

:
LDM CKTCLR,#001?????b ;WDTON←1
:
:

The watchdog timer is disabled by clearing bit 5 (WD­TON) of CKTCLR.

Watchdog Timer Interrupt

The watchdog timer can also be u sed as a simple 6-bit tim­er by clearing bit 5 (WDTON) of CKTCLR. The interval
of watchdog timer interrupt is decided by Basic Interval
Timer.

Interval equation is shown as below.

T WDTR Interval of BIT×=

Clear Counter and set value(??????b)
You have to set WDTR first, for prevent unpredictable interrupt

;

when you set WDTON bit.

;

Select clock source(???b)
Clear counter

Clear counter

Clear counter

and WDTON=1

Example: 6-bit timer interrupt setting up.

LDX #03FH
TXSP ;SP ← 3F
LDM CKTCLR,#000?????b ;WDTON←0
LDM WDTR,#01??????b ;WDTCL←0
:
:

Refer table and see BIT timer ().

CKCTLR

BTS2~0

000

b

001

b

010

b

011

b

100

b

101

b

110

b

111

b

BIT input

clock

PS4 (4uS) 1,024uS 32,256uS

PS5 (8uS) 2,028uS 64,512uS
PS6 (16uS) 4,096uS 129,024uS
PS7 (32uS) 8,192uS 258,048uS
PS8 (64uS) 16,384uS 516,096uS

PS9 (128uS) 32,768uS 1,032,192uS
PS10 (256uS) 65,536uS 2,064,384uS
PS11 (512uS) 131,072uS 4,128,768uS

Watchdog

timer input

clock

IFWDT cycle

The stack pointer (SP) should be initialized before using

Table 20-1 Watchdog timer MAX. cycle (Ex:fex=4MHz)

the watchdog timer output as an interrupt source.

November 2001 Ver 1.1 91

HMS81C4x60

Source clock
BIT overflow

Binary-counter

WDTR

IFWDT interrupt

WDT reset reset

1

2

n

3

Figure 20-3 Watchdog timer Timing

Minimizing Current Consumption

It should be set properly that current flow through port
doesn't exist.

First conseider the setting to input mode. Be sure that there
is no current flow after considering its relationship wi th
external circuit. In input mode, the pin impedance viewing
from external MCU is very high that the cur rent doesn’t
flow.

But input voltage level should be V

or VDD. Be careful

SS

10

3

WDTR ← "0100_0011b"

that if unspecified voltage, i.e. if unfirmed v oltage level is
applied to input pin, there can b e litt le current (max . 1mA
at around 2V) flow.

If it is not appropriate to set as an input m ode, then set to
output mode considering th ere is no current flow. Settin g
to High or Low is decided considering its relationship with
external circuit. For example, if there is external pull-u p re­sistor then it is set to output mode, i.e. to High, and if there
is external pull-down register, it is set to low. See Figure
20-4.

2

30

Counter
Clear

Match
Detect

92 November 2001 Ver 1.1

HMS81C4x60

INPUT PIN

V

DD

i

GND

X

Weak pull-up current flows

INPUT PIN

OPEN

i

Very weak current flows

X

internal
pull-up

V

DD

V

DD

O

V

DD

OPEN

O

V

DD

i=0

O

i=0

GND

O

OUTPUT PIN

ON

ON

OFF

i

GND

X

In the left case, much current flows from port to GND.

OUTPUT PIN

V

DD

ON

OFF

i

L

GND

X

In the left case, Tr. base current flows from port to GND.
To avoid power consumption, low output to the port .

OFF

ON

OFF

OFF

ON

O

i=0

O

O

OPEN

V

DD

GND

V

DD

L

When port is configured as an input, input level should
be closed to 0V or 5V to avoid power consumption.

Figure 20-4 Application example of Port under Power Consumption

November 2001 Ver 1.1 93

HMS81C4x60

21. OSCILLATOR CIRCUIT

The HMS81C4x60 has two oscillation circuits internally.
X

and X

IN

are input and output for main frequency and

OUT

OSC1 and OSC2 are input and output for OSD(On Screen

C1

C2

External Clock

fc (MHz)

X

OUT

X

IN

V

SS

Crystal Oscillator

Open

X

OUT

X

IN

Figure 21-1 Oscillation Circuit

display) frequency, respectively, of a inverting amplifier
which can be configured fo r use as an on-chip oscillator, as
shown in Figure 21-1 .

Recommend

fc (MHz)4C1 & C2 (pF)

15

External Oscillator

Oscillation components have their own characteristics, so
user should consult the component manufacturers for ap­propriate values of external components.

In addition, see Figure 21-2 for the layout of the crystal.

Note: Minimize the wiring length. Do not allow wiring to in­tersect with other signal conductors. Do not allow wiring to
come near changing high current. Set the potential of the
grounding position of the oscillator capacitor to that of V
Do not ground to any ground pattern where high current is
present. Do not fetch signals from the oscillator.

SS

X

OUT

X

IN

.

Figure 21-2 Layout example of Oscillator PCB circuit

94 November 2001 Ver 1.1

22. RESET

HMS81C4x60

The HMS81C4x60 have two types of reset generatio n pro­cedures; one is an external reset input, other is a watch-dog

timer reset. Table 22-1 show s on-chip hardware initializa­tion by reset action.

On-chip Hardware Initial Value On-chip Hardware Initial Value

Program counter PC
RAM page register DPGR

(FFFFH) - (FFFEH)

00

H

Peripheral clock Off
Watchdog timer Disable

G-flag of PSW G 0 Control registers Refer to Table 8-1 on page 22

Table 22-1 Initializing Internal Status by Reset Action

22.1 External Reset Input

The reset input is the RESET pin, which is the inpu t to a
Schmitt Trigger. A reset in accomplished by holding the
RESET pin low for at least 8 oscillator periods, within the
operating voltage range and oscillation stable, a reset is ap­plied and the internal state is initialized. After reset, 64ms
(at 4 MHz) add with 7 oscillator periods are required to
start execution as shown in Figure 22-2 .

Internal RAM is not affected by reset. When V

is turned

DD

on, the RAM content is indeterminate. Therefore, this
RAM should be initialized before reading or testing it.

When the RESET

pin input goes high, the reset operation
is released and the program execution starts at the vector
address stored at addresses FFFE

- FFFFH.

H

A connecting for simple p ower-on-reset is shown in Figure
22-1 .

V

DD

RESET

+

−

GND

Figure 22-1 Simple Power-on-Reset Circuit

MCU

Oscillator

(X

pin)

IN

RESET

Fetch

ADDRESS

BUS

DATA

BUS

~

~

~

~

~

~

?

?

Stabilization Time

t

ST

~

~

~

~

~

~

= 62.5mS at 4.19MHz

1 2 3 4 5 6 7

~

~

?

??

??

RESET Process Step

t

=

ST

f

MAIN

1

÷1024

Figure 22-2 Timing Diagram after RESET

FFFE FFFF

FE?ADL

x 256

ADH

Start

OP

MAIN PROGRAM

November 2001 Ver 1.1 95

HMS81C4x60

22.2 Watchdog Timer Reset

Refer to “20. WATCHDOG TIMER” on page 90.

96 November 2001 Ver 1.1

23. OTP Programming

23.1 HMS87C4x60 OTP Programming

HMS81C4x60

User can burn out HMS87C4x60 OTP th rough the general
Gang programmer using special ROM writer. In Devleop­ment tool package auxiliary, HMS87C4x60 has ROM
writer socket. HMS87C4x60 have two ROM memory ar­eas. One is Program ROM memory and the other is Font
ROM memory. Program ROM area is from 1000h to
FFFFh Font ROM area is from 10000h to 17FFFh .

Blank Che ck

Figure 23-1 HMS87C4x60 OTP Memory Map

1000H

FFFFH

17FFFH

Program
Memory

OSD Font
Memory

Program Writing

There are two kind of OTP file. One is program OTP
file(***.OTP) and the other is font OTP file(***.FNT).
You can make each file through ASMLINKER.exe and
OSDFONT.exe respectively. All OTP file is Motolora S­format. You can burn the program file and font file respec­tively or together. To burn progra m file and font file re­spectively, refer following procedure

1. Make program OTP file and font OTP file repec­tively.

2. Burn program OTP file(Set chip target address
1000h ~ FFFFh)

3. Burn font OTP file(Set chip target address 10000h
~17FFFh)

To burn program file and font f ile together , refer fol lowing
procedure

1. Add program OTP file and font OTP file

2. Burn OTP file(Set chip target addres s 1000h ~
17FFFh)

About other details, refer ROM wirter manual.

November 2001 Ver 1.1 97

HMS81C4x60

23.2 .Device Configuration Data

OM1
OM2
OM3

PGMB

DIO<4>

DIO<0>
DIO<1>
DIO<2>

DIO<3>

OEB

CEB

AHB

ALB

32SDIP

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

HMS87C4260

HYNIX

52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27

DIO<6>
DIO<5>

VPP

A16

DIO<7>

Figure 23-2 Figure Pin Configuration in OTP Programming Mode

HMS87C4x60

Mode VPP CEB OEB PGMB

Program 11.25 Low High Low

Verify 11.25 Low Low High

Optional Verify 5 Low Low X

Gang Write 11.25 Low High Low

Gang Verify 11.25, 5 Low Low X

Figure 23-3 Figure Mode Table

98 November 2001 Ver 1.1