Datasheet HM9270C, HM9270D, HM9270DM Datasheet (ELAN)

DTMF RECEIVER

HM 9270C/D

- 1 -

General Description

The HM 9270C/D is a complete DTMF receiver integrating both the bandsplit filter and digital decoder
functions. The filter section uses switched capacitor techniques for high- and low-group filters and dial-tone
rejection. Digital counting techniques are employed in the decoder to detect and decode all 16 DTMF tone­pairs into a 4-bit code. External component count is minimized by on-chip provision of a differential input
amplifier, clock-oscillator and latched 3-state bus interface.

Features

• Complete receiver in an 18-pin package.

• Excellent performance.

• CMOS, single 5 volt operation.

• Minimum board area.

• Central office quality.

• Low power consumption.

• Power-Down mode (HM9270D only).

• Inhibit-mode (HM9270D only).

Pin Configurations

* Connect to V

SS

HM9270C

IN+

IN

GS
IC*

IC*

OSC1

OSC2

V

DD

V

REF

ESt
StD
Q4

Q3
Q2

Q1
TOE

St/GT

V

SS

1
2
3
4
5
6
7
8
9

18
17
16
15
14
13
12
11
10

HM9270D

IN+

IN

GS

INH

PWDN

OSC1

OSC2

V

DD

V

REF

ESt
StD
Q4

Q3
Q2

Q1
TOE

St/GT

V

SS

1
2
3
4
5
6
7
8
9

18
17
16
15
14
13
12
11
10

DTMF RECEIVER

HM 9270C/D

- 2 -

Block Diagram (Figure 1)

Pin Sym.

1 IN+
2 IN-

3GS

4V

REF

5 INH

6 PWDN

7 OSC1
8 OSC2

9V

SS

10 TOE

Non-Inverting input
Invering Input

Gain select. Gives access to output of front-end differential amplifier for connection of
feedback resistor.

Reference voltage output,nominally VDD/2. May be used to bias the inputs at midrail (see
application diagram).

Inhibit (input) logic high inhibit the detection of 1633Hz internal built-in pull down resistor.
(HM9270D only).

Power down (input). Active high power down the device and inhibit the oscillator internal
built-in pull down resistor. (HM9270D only).

Clock Input Clock
Output

Negative power supply, normally connected to 0V.

3-state data output enable (input). Logic high enables the outputs Q1-Q4. Internal pull-up.

Connections to the front-end differential amplifier.

Function

Pin Description

3.579545 MHz crystal connected between these pins completes
internal oscillator.

Q1

Q2

Q3

Q4

OSC1

OSC2

GS

IN

IN+

+

-

CHIP
CLOCKS

CHIP
POWER

CHIP
BIAS

CHIP
REF

DIAL

TONE

FILTER

HIGH

GROUP

FILTER

LOW

GROUP

FILTER

BIAS

CIRCUIT

+

-

ZERO

CROSSING

DETECTORS

DIGITAL

DETECTION

ALGORITHM

CODE

CONVERTER

AND

LATCH

STEERING

LOGIC

TOE

StDVDDV

SS

V

REF

St/

GT

ESt

INH

PWDN

DTMF RECEIVER

HM 9270C/D

- 3 -

Pin Sym.

Function

11 Q1
12 Q2
13 Q3
14 Q4

15 StD

16 ESt

17 St/GT

18 V

DD

3-state data outputs. When enabled by TOE, provide the code corresponding to the last valid
tone-pair received (see code table).

Delayed steering output. Presents a logic high when a received tone-pair has been registered
and the output latch updated; returns to logic low when the voltage on St/GT falls below
V

TSt

.

Early steering output. Presents a logic high immediately when the digital algorithm detects a
recognizable tone-pair (signal condition). Any momentary loss of signal condition will cause
ESt to return to a logic low.

Steering input/guard time output (bi-directional). A voltage greater than V

TSt

detected at St
causes the device to register the detected tone-pair and update the output latch. A voltage
less than V

TSt

frees the device to accept a new tone-pair. The GT output acts to reset the
external steering time-constant; its state is a function of ESt and the voltage on St (see truth
table).

Positive power supply, +5Volts.

DC Electrical Characteristics

Parameter Description

SUPPLY:

V

DD

Operating Supply Voltage

I

cc

Operating Supply Current

P

o

Power Consumption

I

S

Standby Current

INPUTS:

V

IL

Low Level Input Voltage

V

IH

High Level Input Voltage

IIH/I

IL

Input Leakage Current

I

so

Pull Up (Source) Current

R

IN

Input Signal
Impedance Inputs 1,2

V

TSt

Steering Threshold Voltage

Test Conditions Min. Typ. Max. Units

4.75 5.25 V

3.0 7 mA
f=3.579MHz; VDD=5V 15 35 mW
PWDN pin = V

DD

- - 100 µA

1.5 V

3.5 V

VIN=Vss or V

DD

0.1 uA
TOE (Pin 10)=OV 7.5 15 uA
@ 1kHz 10 MΩ

2.35 V

Parameters Min. Max. Units

Power Supply Voltage, VDD - V

SS

6V
Voltage on any pin VSS - 0.3 VDD+ 0.3 V
Current at any pin 10 mA
Operating temperature -40 +85

o

C

Storage temperature -65 +150

o

C

Package power dissipation 500 mW

Note 1. Absolute maximum ratings are those values beyond which damage to the device may

occur.

2. Unless otherwise specified, all voltages are referenced to ground.

3. Power dissipation temperature derating: -12 mV/oC from 65oC to 85oC

Absolute Maximum Ratings (Notes 1, 2 and 3)

DTMF RECEIVER

HM 9270C/D

- 4 -

Test Conditions Min. Typ. Max. Units

No Load 0.03 V
No Load 4.97 V
V

OUT

=0.4V 1.0 2.5 mA

V

OUT

=4.6V 0.4 0.8 mA

No Load 2.4 2.7 V

10 KΩ

OUTPUTS:
V

OL

Low Level Output Voltage

V

OH

High Level Output Voltage

I

OL

Output Low (Sink) Current

I

OH

Output High (Source) Current

V

REF

Output Voltage V

REF

R

OR

Output Resistance

Operating Characteristics
Gain Setting Amplifier

I

IN

Input Leakage Current VSS < VIN < V

DD

±100 nA

R

IN

Input Resistance 10 M Ω

V

OS

Input Offset Voltage ±25 mV
PSRR Power Supply Rejection 1kHz 60 dB
CMRR Common Mode Rejection -3.0V <VIN< 3.0V 60 dB
A

VOL

DC Open Loop Voltage Gain 65 dB
f

C

Open Loop Unity Gain Bandwidth 1.5 MHz
V

O

Output Voltage Swing RL³100KΩ to V

SS

4.5 V

PP

C

L

Tolerable capacitive load(GS) 100 pF
R

L

Tolerable resistive load(GS) 50 KΩ
V

CM

Common Mode Range No Load 3.0 V

PP

SIGNAL COITIONS:

Valid Input Signal level (each
tone signal):MIN

MAX

Twist Accept Limit: Positive

Negative

Freq. Deviation Accept Limit
Freq. Deviation Reject Limit
Third Tone Tolerance
Noise Tolerance
Dial Tone Tolerance

-40 dBm 1,2,3,5,6,9,11

7.75 mV

RMS

1,2,3,5,6,9,11
+1 dBm
883 mV

RMS

10 dB 2,3,6,9,11
10 dB

±1.5%±2 Hz Nom. 2,3,5,9,11

±3.5% Nom. 2,3,5,11

-16 2,3,4,5,9,10,11

-12 dB 2,3,4,5,7,9,10,11
+18 dB 2,3,4,5,8,9,10,11

Min. Typ. Max. Units Notes

AC Characteristics

All voltages referenced to V

SS

unless otherwise noted. VDD=5.0V, VSS=0V, TA = 25OC, F

CLK

=3.579545 MNz, using

test circuit of figure 2.

Notes : 1.All voltages referenced to VDD unless otherwise noted.

2.VDD= 5.0V, VSS = 0V, TA = 25oC .

Parameter Description

1,2,3,5,6,9,11

Parameter Description

Parameter Description Test Conditions Min. Typ. Max. Units

DTMF RECEIVER

HM 9270C/D

- 5 -

Parameter Description

Min. Typ. Max. Units Notes

TIMING:

t

DP

Tone Present Detection Time

t

DA

Tone Absent Detection Time

t

REC

Tone Duration Accept

t

REC

Tone Duration Reject

t

ID

Interdigit Pause Accept

t

DO

Interdigit Pause Reject

OUTPUTS:

t

PQ

Propagation Delay (St to Q)

t

PSED

Propagation Delay (St to StD)

t

QSED

Output Data Set Up (Q to Std)

t

PTE

Propagation ENABLE

t

PTD

Delay (TOE to Q) DISABLE

CLOCK:

f

CLK

Crystal/Clock Frequency

C

LO

Clock Output Capacitive
(OSC2) Load

5 14 16 ms Refer to Fig. 4

(User Adjustable)

Function Description

Notes: 1.dBm = decibels above or below a reference power of 1mW into a 600 Ohm load.

2.Digit sequences consists of all 16 DTMF tones.

3.Tone duration = 40mS Tone pause = 40mS.

4.Nominal DTMF frequencies are used.

5.Both tones in the composite signal have an equal amplitude.

6.Tone pair is deviated by ±1.5% ±2Hz.

7.Bandwidth limited (3kHz) Gaussian Noise.

8.The precise dial tone frequencies are (350Hz and 440Hz) ±2%.

9.For an error rate of less than 1 in 10,000.

10.Referenced to the lowest level frequency component in DTMF signal.

11.Added A 0.1µf capacitor between VDD and VSS.

FIGURE 2. SINGLE ENDED INPUT CONFIGURATION

0.5 4 8.5 ms
40 ms

20 ms

40 ms Refer to "Guard Time 20

ms Adjustment"

8 11 µ s TOE= V

DD

12 µs

4.5 µs
50 60 ns RL=10kΩ
300 ns CL=50pf

3.5759 3.5795 3.581 MHz
30 pf

HM9270C

300

IN+
IN
GS

IC

IC

OSC1
OSC2

TOE

StD

V

SS

St/GT

KΩ

100

NF

Q4
Q3

Q2
Q1

V

DD

ESt

V

REF

100

NF

100

100

3.58
MHz

KΩ

KΩ

5V

0.1µf

DTMF RECEIVER

HM 9270C/D

- 6 -

The HM9270C/D monolithic DTMF receiver offers small size, low power consumption and high performance. Its
architecture consists of a bandsplit filter section, which separates the high and low tones of receiver pair, followed by
a digital counting section which verifies the frequency and duration of the received tones before passing the
corresponding code to the output bus.

FILTER SECTION

Separation of the low-group and high-group tones is achieved by applying the dual tone signal to the inputs of two
filters a sixth order for the high group and an eighth order for the low group. The bandwidths of which correspond
to the bands enclosing the low-group and high-group tones (see Fig. 4). The filter section also in corporates
notches at 350Hz and 440 Hz for exceptional dial-tone rejection. Each filter output is followed by a second-order
switched-capacitor section which smooths the signals prior to limiting. Limiting is performed by high-gain com­parators which are provided with hysteresis to prevent detection of unwanted low-level signals and noise; the
outputs of the comparators provide full-rail logic swings at the frequencies of the incoming tones.

Flow Fhigh KEY TOE Q4 Q3 Q2 Q1
697 1209 1 H 0 0 0 1
697 1336 2 H 0 0 1 0
697 1477 3 H 0 0 1 1
770 1209 4 H 0 1 0 0
770 1336 5 H 0 1 0 1
770 1477 6 H 0 1 1 0
852 1209 7 H 0 1 1 1
852 1336 8 H 1 0 0 0
852 1477 9 H 1 0 0 1
941 1336 0 H 1 0 1 0
941 1209 * H 1 0 1 1
941 1477 # H 1 1 0 0
697 1633 A H 1 1 0 1
770 1633 B H 1 1 1 0
852 1633 C H 1 1 1 1
941 1633 D H 0 0 0 0

- - ANY L Z Z Z Z
L = LOGIC LOW , H = LOGIC HIGH, Z = HIGH

IMPEDANCE

FIGURE 4. LOGIC TABLE

FIGURE 3. SINGLE ENDED INPUT CONFIGURATION

Decoder Section

The decoder used digital counting techniques to
determine the frequencies of the limited tones and to
verify that they correspond to standard DTMF
frequencies. A complex averaging algorithm(protects)
against tone simulation by extraneous signals, such as
voice, while providing tolerance to smalll frequency
deviations and variations. This averaging algorithm has
been developed to ensure an optimum combination of
immunity to "talk-off" and tolerance to the presence of
interfering signals ("third tones") and noise. When the
detector recognizes the simultaneous presence of two
valid tones (referred to as "signal condition" in some
industry specifications), it raises the "early steering"
flag (ESt). Any subsequent loss of signal condition will
cause ESt to fall.

HM9270D

300

IN+
IN
GS

INH

PWDN

OSC1
OSC2

TOE

StD

V

SS

St/GT

KΩ

100

NF

Q4
Q3

Q2
Q1

V

DD

ESt

V

REF

100

NF

100

100

3.58
MHz

KΩ

KΩ

5V

0.1µf

Vin

5V

DTMF RECEIVER

HM 9270C/D

- 7 -

FIGURE 5. TIMING DIAGRAM

A. Short tone bursts: detected. Tone duration is invalid.
B. Tone #n is detected. Tone duration is valid. Decoded

to outputs.
C. End of tone #n is dectected and validated.
D. 3 State outputs disabled (high impedance).
E. Tone #n + 1 is detected. Tone duration is valid. De
coded to outputs.
F. Tristate outputs are enabled. Acceptable drop out of
tone #n + 1 does not negister at outputs.
G. End of tone #n + 1 is detected and validated.

FIGURE 5. TIMING DIAGRAM

the GT output is activated and drives VC to VDD. GT continues to drive high as long as ESt remains high. Finally
after a short delay to allow the output latch to settle, the "delayed-steering" output flag, StD, goes high, signaling
that a recieved tone-pair has been registered. The contents of the output lacth are made available on the 4-bit
output bus by raising the 3-state control input (TOE) to a logic high. The steering circuit works in reverse to
validate the interdigit paues between signals. Thus, as well as rejecting signals too short to be considered valid, the
receiver will tolerate signal interruptions ("drop-out") too short to be considered a valid pause. The facility, together
with the capability of selecting the steering time-constants externally, allows the designer to tailor performance to
meet a wide variety of system requiremetns.

FIGURE 6. TYPICAL FILTER

CHARACTERISTIC

Before registration of a decoded tone-pair, the receiver checks
for a valid signal duration (referred to as "character-recogni­tion-condition"). This check is per­formed by an external RC time-constant driven by ESt.
A logic high on ESt causes VC (see Fig. 5) to rise as the
capacitor discharges. Provided signal-condition is main­tained (ESt remains high) for the validation period (t

GTP

), Vc

reaches the threshold (V

TSt

) of the steering logic to register the
tone-pair, latching its corresponding 4-bit code (see Fig. 3)
into the output latch. At this point,

STEERING CIRCUIT

D

ABC EF G

t

REC

t

REC

INTERDIGIT
PAUSE

t

ID

TONE DROPOUT t

DO

TONE # n TONE #n+1 TONE#n+1

t

DP

DA

t

GTP

t

PQ

t

t

GTA

V

Ts t

DECODE TONE n-1

DECODED
TONE#n

DECODED TONE # n + 1

HIGH

IMPEDANCEt

PStD

t

PTE

PTD

t

EVENTS

ESt

DATA
OUTPUTS

Q1-Q4

TOE

St/GT

StD
OUTPUT

0

10
20
30

40
50
60
70
80

0

1K

2K

DTMF RECEIVER

HM 9270C/D

- 8 -

C

V

C

R

V

DD

V

DD

St/GT

ESt

S

tD

V

DD

t

GTP

GTA

t

=(RC) ln (

V

V

DD

=(RC) ln (

V

V

DD

-

)

)

TST

TST

0.1µf

V

DD

S

t

GT

/

ES

t

C

R2

R1

V

DD

S

t

GT/

ES

t

C

R2R1

FIGURE 7. BASIC STEERING CIRCUIT

Guard Time Adjustment

In many situations not requiring independent selection of receive and pause, the simple steering circuit of Fig. 7 is
applicable. Component values are chosen according to the following formulae:

t

REC

= tDP + t

GTP

tID = tDA + t

GTA

The value of tDP is a parameter of the device (see table) and t

REC

is the minimum signal duration to be recognized by
the receiver. A value for C of 0.1 µF is recommended for most applications, leaving R to be selected by the
designer. For example, a suitable value of R for a t

REC

of 40mS would be 300k.

Different steering arrangements may be used to select independently the guard-times for tone-present (t

GTP

) and

tone-absent (t

GTA

). This may be necessary to meet system specifications which place both accept and reject limits on
both tone duration and interdigital pause.
Guard-time adjustment also allows the designer to tailor system parameters such as talk off and noise immunity.
Increasing t

REC

improves talk-off performance, since it reduces the probability that tones simulated by speech will

maintain signal condition for long enough to be registered. On the other hand, a relatively short t

REC

with a long t

DO

would be appropriate for extremely noisy environments where fast acquisition time and immunity to drop - outs
would be required. Design information for guard-time adjustment is shown in Fig. 8.

tGTP=(Rp C) In (

tGTP=(Rp C) In (

tGTA=(R1 C) In (

Rp=

tGTA=(R1 C) In (

Rp=

VDD - V

TST

VDD

VDD - V

TST

VDD

)

V

TST

VDD

)

)

V

TST

VDD

)

R1+R2

R1R2

R1+R2

R1R2

a) Decreasing t

GTP

(t

GTP

< t

GTA

) b) Decreasing t

GTP

(t

GTP

> t

GTA

)

FIGURE 8. GUARD TIME ADJUSTMENT

DTMF RECEIVER

HM 9270C/D

- 9 -

fLow Fhigh Key TOE Q4 Q3 Q2 Q1

697 1209 1 H LLLH
697 1336 2 H L L H L
697 1477 3 H L L H H
770 1209 4 H L H L L
770 1336 5 H L H L H
770 1477 6 H L H H L
852 1209 7 H L H H H
852 1336 8 H H L L L
852 1477 9 H H L L H
941 1336 0 H H L H L
941 1209 * H H L H H
941 1477 # HHHLL

697 1633 A H

770 1633 B H
852 1633 C H
941 1633 D H

-- ANYLZZZZ

Input Configuration

The input arrangement of the HM9270C/D provides a differential-input operational amplifier as well as a
bias source (V

REF

) which is used to bias the inputs at mid-rail.
Provision is made for connection of a feedback resistor to the op-amp output (GS) for adjustment of gain.
In a single-ended configuration, the input pins are connected as shown in Fig. 2 with the op-amp connected
for unity gain and V

REF

biasing the input at 1/2VDD.
Fig. 9 shows the differential configuration, which permits the adjustment of gain with the feedback resistor
R5.

FIGURE 9. DIFFERENTIAL INPUT CONFIGURATION

Power - down and inhibit mode

A logic high applied to pin 6 (PWDN) will power the device to minimize the power consumption in a standby
mode. It stops the oscillator and the functions of the filters.
Inhibit mode is enabled by a logic high input to the pin 5 (INH). It inhibits the detection of 1633 Hz. The output
code will remain the same as the previous detected code (see table 1).

fLow Fhigh Key TO E Q4 Q3 Q2 Q1

697 1209 1 H LLLH
697 1336 2 H L L H L
697 1477 3 H L L H H
770 1209 4 H L H L L
770 1336 5 H L H L H
770 1477 6 H L H H L
852 1209 7 H L H H H
852 1336 8 H H L L L
852 1477 9 H H L L H
941 1336 0 H H L H L
941 1209 * H H L H H
941 1477 # HHHLL

697 1633 A HHHLH

770 1633 B HHHHL
852 1633 C HHHHH
941 1633 D H LLLL

-- ANYLZZZZ

PREVIOUS DATA

Table 1: Truth table

INH =V

SS

(Z: high impedance) INH=V

DD

C1

R1

C2

R4

R5

GS

R2

R3

V

REF

+

-

HM9270C/D

DTMF RECEIVER

HM 9270C/D

- 10 -

SPECIAL PACKAGE PIN CONFIGURATIONS

1
2
3
4
5
6
7
8
9

10

20
19
18
17
16
15
14
13
12
11

IN+

IN-

GS

VREF

INH

PWDN

OSC1
OSC2

V

SS

V

DD

St/GT
EST
StD
Q

4

Q

3

Q

2

Q

1

TOE

HM9270DM

NC

NC