Datasheet HM62W16255HCJP-10, HM62W16255HCLJP-10, HM62W16255HCLTT-10, HM62W16255HCTT-10 Datasheet (HIT)
Page 1
HM62W16255HC Series
4M High Speed SRAM (256-kword × 16-bit)
ADE-203-1200 (Z)
Preliminary
Rev. 0.0
Sep. 1, 2000
Description
The HM62W16255HC is a 4-Mbit high speed static RAM organized 256-kword × 16-bit. It has realized high
speed access time by employing CMOS process (6-transistor memory cell) and high speed circuit designing
technology. It is most appropriate for the application which requires high speed, high density memory and
wide bit width configuration, such as cache and buffer memory in system. The HM62W16255HC is
packaged in 400-mil 44-pin SOJ and 400-mil 44-pin plastic TSOPII for high density surface mounting.
Features
• Single 3.3 V supply: 3.3 V ± 0.3 V
• Access time: 10 ns (max)
• Completely static memory
No clock or timing strobe required
• Equal access and cycle times
• Directly TTL compatible
All inputs and outputs
• Operating current: 145 mA (max)
• TTL standby current: 40 mA (max)
• CMOS standby current: 5 mA (max)
: 1 mA (max) (L-version)
• Data retention current: 0.6 mA (max) (L-version)
• Data retention voltage: 2.0 V (min) (L-version)
• Center VCC and VSS type pinout
Preliminary: The specification of this device are subject to change without notice. Please contact your nearest
Hitachi’s Sales Dept. regarding specification.
Page 2
HM62W16255HC Series
Ordering Information
Type No. Access time Package
HM62W16255HCJP-10 10 ns 400-mil 44-pin plastic SOJ (CP-44D)
HM62W16255HCLJP-10 10 ns
HM62W16255HCTT-10 10 ns 400-mil 44-pin plastic TSOPII (TTP-44DE)
HM62W16255HCLTT-10 10 ns
2
Page 3
Pin Arrangement
HM62W16255HC Series
I/O1
I/O2
I/O3
I/O4
V
V
I/O5
I/O6
I/O7
I/O8
WE
Pin Description
A0
A1
A2
A3
A4
CS
CC
SS
A5
A6
A7
A8
A9
44-pin SOJ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
(Top View)
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A17
A16
A15
OE
UB
LB
I/O16
I/O15
I/O14
I/O13
V
SS
V
CC
I/O12
I/O11
I/O10
I/O9
NC
A14
A13
A12
A11
A10
I/O1
I/O2
I/O3
I/O4
V
V
I/O5
I/O6
I/O7
I/O8
WE
A0
A1
A2
A3
A4
CS
CC
SS
A5
A6
A7
A8
A9
44-pin TSOP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
(Top View)
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A17
A16
A15
OE
UB
LB
I/O16
I/O15
I/O14
I/O13
V
SS
V
CC
I/O12
I/O11
I/O10
I/O9
NC
A14
A13
A12
A11
A10
Pin name Function
A0 to A17 Address input
I/O1 to I/O16 Data input/output
CS Chip select
OE Output enable
WE Write enable
UB Upper byte select
LB Lower byte select
V
CC
V
SS
Power supply
Ground
NC No connection
3
Page 4
HM62W16255HC Series
Block Diagram
(LSB)
A14
A13
A12
A5
A6
A7
A11
A10
A3
A1
(MSB)
I/O1
.
.
.
I/O8
I/O9
.
.
.
I/O16
WE
CS
LB
Row
decoder
CS
Input
data
control
Memory matrix
1024 rows × 32 columns ×
8 blocks × 16 bit
(4,194,304 bits)
Column I/O
Column decoder
A8 A9 A17 A15 A16 A0 A2 A4
(LSB)
(MSB)
CS
V
CC
V
SS
UB
OE
CS
4
Page 5
HM62W16255HC Series
Operation Table
CS OE WE LB UB Mode VCC current I/O1–I/O8 I/O9–I/O16 Ref. cycle
H ××××Standby I
LHH××Output disable I
L L H L L Read I
L L H L H Lower byte read I
L L H H L Upper byte read I
L LHHH— I
L × L L L Write I
L × L L H Lower byte write I
L × L H L Upper byte write I
L × L HH— I
, I
SB
CC
CC
CC
CC
CC
CC
CC
CC
CC
Note: ×: H or L
Absolute Maximum Ratings
SB1
High-Z High-Z —
High-Z High-Z —
Output Output Read cycle
Output High-Z Read cycle
High-Z Output Read cycle
High-Z High-Z —
Input Input Write cycle
Input High-Z Write cycle
High-Z Input Write cycle
High-Z High-Z —
Parameter Symbol Value Unit
Supply voltage relative to V
Voltage on any pin relative to V
SS
SS
Power dissipation P
V
CC
V
T
T
–0.5 to +4.6 V
–0.5*1 to VCC + 0.5*
2
V
1.0 W
Operating temperature Topr 0 to +70 °C
Storage temperature Tstg –55 to +125 °C
Storage temperature under bias Tbias –10 to +85 °C
Notes: 1. VT (min) = –2.0 V for pulse width (under shoot) ≤ 6 ns
2. V
(max) = VCC + 2.0 V for pulse width (over shoot) ≤ 6 ns
T
5
Page 6
HM62W16255HC Series
Recommended DC Operating Conditions (Ta = 0 to +70°C)
Parameter Symbol Min Typ Max Unit
3
Supply voltage V
Input voltage V
CC
VSS*
IH
V
IL
*
4
Notes: 1. VIL (min) = –2.0 V for pulse width (under shoot) ≤ 6 ns
2. V
(max) = VCC + 2.0 V for pulse width (over shoot) ≤ 6 ns
IH
3. The supply voltage with all V
4. The supply voltage with all V
pins must be on the same level.
CC
pins must be on the same level.
SS
DC Characteristics (Ta = 0 to +70°C, VCC = 3.3 V ± 0.3 V, VSS = 0 V)
3.0 3.3 3.6 V
000V
2.0 — VCC + 0.5*2V
1
–0.5*
— 0.8 V
Parameter Symbol Min Typ*
Input leakage current |I
|——2 µA Vin = VSS to V
LI
1
Max Unit Test conditions
Output leakage current |ILO|——2 µA Vin = VSS to V
Operating power supply current I
CC
— — 145 mA Min cycle
CS = V
IL
, Iout = 0 mA
Other inputs = V
Standby power supply current I
SB
— — 40 mA Min cycle, CS = VIH,
Other inputs = V
I
SB1
— TBD 5 mA f = 0 MHz
V
≥ CS ≥ VCC – 0.2 V,
CC
(1) 0 V ≤ Vin ≤ 0.2 V or
Output voltage V
(2) V
2
—*
OL
V
OH
— — 0.4 V IOL = 8 mA
2.4 — — V IOH = –4 mA
TBD*21.0*
2
≥ Vin ≥ VCC – 0.2 V
CC
Notes: 1. Typical values are at VCC = 3.3 V, Ta = +25°C and not guaranteed.
2. This characteristics is guaranteed only for L-version.
CC
CC
IH/VIL
IH/VIL
6
Page 7
HM62W16255HC Series
Capacitance (Ta = +25°C, f = 1.0 MHz)
Parameter Symbol Min Typ Max Unit Test conditions
Input capacitance*
Input/output capacitance*
1
1
Note: 1. This parameter is sampled and not 100% tested.
Cin — — 6 pF Vin = 0 V
C
I/O
——8 pFV
= 0 V
I/O
7
Page 8
HM62W16255HC Series
AC Characteristics (Ta = 0 to +70°C, VCC = 3.3 V ± 0.3 V, unless otherwise noted.)
Test Conditions
• Input pulse levels: 3.0 V/0.0 V
• Input rise and fall time: 3 ns
• Input and output timing reference levels: 1.5 V
• Output load: See figures (Including scope and jig)
1.5 V
3.3 V
319 Ω
Dout
Zo=50 Ω
RL=50 Ω
Output load (A)
30 pF
Dout
(for t
353Ω
Output load (B)
, t
CLZ
OLZ
t
, t
LBHZ
, t
UBHZ
LBLZ
, t
, t
UBLZ
, and tOW)
WHZ
5 pF
, t
CHZ
, t
,
OHZ
Read Cycle
HM62W16255HC
-10
Parameter Symbol Min Max Unit Notes
Read cycle time t
Address access time t
Chip select access time t
Output enable to output valid t
RC
AA
ACS
OE
Byte select to output valid tLB, t
Output hold from address change t
Chip select to output in low-Z t
Output enable to output in low-Z t
Byte select to output in low-Z t
Chip deselect to output in high-Z t
Output disable to output in high-Z t
Byte deselect to output in high-Z t
OH
CLZ
OLZ
LBLZ
CHZ
OHZ
LBHZ
UB
, t
UBLZ
, t
UBHZ
10 — ns
—10ns
—10ns
—5 ns
—5 ns
3—ns
3 — ns 1
0 — ns 1
0 — ns 1
— 5 ns 1
— 5 ns 1
— 5 ns 1
8
Page 9
HM62W16255HC Series
Write Cycle
HM62W16255HC
-10
Parameter Symbol Min Max Unit Notes
Write cycle time t
Address valid to end of write t
Chip select to end of write t
Write pulse width t
Byte select to end of write t
Address setup time t
Write recovery time t
Data to write time overlap t
Data hold from write time t
Write disable to output in low-Z t
Output disable to output in high-Z t
Write enable to output in high-Z t
WC
AW
CW
WP
LBW
AS
WR
DW
DH
OW
OHZ
WHZ
, t
UBW
Notes: 1. Transition is measured ±200 mV from steady voltage with Load (B). This parameter is sampled
and not 100% tested.
2. If the CS or LB or UB low transition occurs simultaneously with the WE low transition or after the
WE transition, output remains a high impedance state.
3. WE and/or CS must be high during address transition time.
4. If CS, OE, LB and UB are low during this period, I/O pins are in the output state. Then the data
input signals of opposite phase to the outputs must not be applied to them.
5. t
is measured from the latest address transition to the latest of CS, WE, LB or UB going low.
AS
6. t
is measured from the earliest of CS, WE, LB or UB going high to the first address transition.
WR
7. A write occurs during the overlap of low CS, low WE and low LB or low UB.
is measured from the later of CS going low to the end of write.
8. t
CW
9. t
is measured from the later of LB going low to the end of write.
LBW
10.t
is measured from the later of UB going low to the end of write.
UBW
10 — ns
7—ns
7 — ns 8
7 — ns 7
7 — ns 9, 10
0 — ns 5
0 — ns 6
5—ns
0—ns
3 — ns 1
— 5 ns 1
— 5 ns 1
9
Page 10
HM62W16255HC Series
Timing Waveforms
Read Timing Waveform (1) (WE = VIH)
t
RC
Address
CS
OE
LB
UB
Dout
(Lower byte)
t
AA
High Impedance
Valid address
t
ACS
t
OE
t
LB
t
UB
t
LBLZ
4
*
t
UBLZ
t
OLZ
1
*
t
CHZ
1
t
*
OHZ
1
t
*
LBHZ
1
t
1
*
Valid data
1
*
1
*
UBHZ
t
OH
*
4
*
Dout
(Upper byte)
10
High Impedance
1
t
*
CLZ
4
*
Valid data
4
*
Page 11
Read Timing Waveform (2) (WE = VIH, LB = VIL, UB, = VIL)
t
RC
HM62W16255HC Series
Address
CS
OE
Dout
(Lower/Upper
byte)
High Impedance
Valid address
t
AA
t
ACS
t
t
CLZ
4
*
t
OLZ
OE
t
OH
1
t
*
CHZ
1
t
*
OHZ
1
*
1
*
4
Valid data
*
11
Page 12
HM62W16255HC Series
Write Timing Waveform (1) (LB, UB Controlled)
t
WC
Address
3
WE*
3
CS*
OE
LB
UB
Valid address
t
AW
t
AS
t
WP
t
CW
t
LBW
t
UBW
t
WHZ
t
WR
t
OLZ
Dout
(Lower byte)
Dout
(Upper byte)
Din
(Lower byte)
Din
(Upper byte)
12
t
OHZ
High impedance
High impedance
t
DW
t
DW
Valid data
Valid data
t
DH
t
OW
t
DH
Page 13
Write Timing Waveform (2) (WE Controlled)
t
HM62W16255HC Series
WC
Address
3
WE*
3
CS*
OE
LB, UB
Dout
(Lower/Upper
byte)
Valid address
t
AW
t
AS
t
OHZ
t
WHZ
t
LBW
t
CW
t
WP
t
UBW
t
WR
t
t
OW
OLZ
High impedance
2
*
t
DW
t
DH
Din
(Lower/Upper
byte)
Valid data
13
Page 14
HM62W16255HC Series
Write Timing Waveform (3) (CS Controlled)
t
WC
Address
3
WE
*
3
CS *
OE
LB, UB
Dout
(Lower/Upper
byte)
Valid address
t
AW
t
AS
t
WHZ
t
OHZ
t
LBW
t
WP
t
t
UBW
CW
High impedance
2
*
t
DW
t
WR
t
OLZ
t
OW
4
*
t
DH
Din
(Lower/Upper
byte)
14
Valid data
Page 15
HM62W16255HC Series
Low VCC Data Retention Characteristics (Ta = 0 to +70°C)
This characteristics is guaranteed only for L-version.
Parameter Symbol Min Typ*1Max Unit Test conditions
for data retention V
V
CC
Data retention current I
Chip deselect to data retention time t
Operation recovery time t
DR
CCDR
CDR
R
Note: 1. Typical values are at VCC = 3.0 V, Ta = +25˚C, and not guaranteed.
Low VCC Data Retention Timing Waveform
2.0 — — V VCC ≥ CS ≥ VCC – 0.2 V,
(1) 0 V ≤ Vin ≤ 0.2 V or
(2) V
≥ Vin ≥ VCC – 0.2 V
CC
— TBD 600 µAVCC = 3 V
V
≥ CS ≥ VCC – 0.2 V,
CC
(1) 0 V ≤ Vin ≤ 0.2 V or
(2) V
≥ Vin ≥ VCC – 0.2 V
CC
0 — — ns See retention waveform
5 ——ms
V
CC
3.0 V
V
DR
2.0 V
CS
0 V
t
CDR
Data retention mode
VCC ≥ CS ≥ VCC – 0.2 V
t
R
15
Page 16
HM62W16255HC Series
Package Dimensions
HM62W16255HCJP/HCLJP Series (CP-44D)
28.33
28.90 Max
44 23
10.16 ± 0.13
Unit: mm
11.18 ± 0.13
122
0.74
1.30 Max
*0.43 ± 0.10
0.41 ± 0.08
0.10
*Dimension including the plating thickness
Base material dimension
1.27
3.50 ± 0.26
+0.25
–0.17
0.80
Hitachi Code
JEDEC
EIAJ
Mass
(reference value)
2.65 ± 0.12
9.40 ± 0.25
CP-44D
Conforms
—
1.8 g
16
Page 17
HM62W16255HCTT/HCLTT Series (TTP-44DE)
18.41
18.81 Max
44 23
10.16
HM62W16255HC Series
Unit: mm
122
*0.27 ± 0.07
0.25 ± 0.05
0.80
0.13
M
1.005 Max
0.10
1.20 Max
*Dimension including the plating thickness
Base material dimension
0.125 ± 0.04
*0.145 ± 0.05
11.76 ± 0.20
0.13 ± 0.05
0° – 5°
Hitachi Code
JEDEC
EIAJ
Mass
(reference value)
0.80
0.50 ± 0.10
TTP-44DE
—
—
0.43 g
0.68
17
Page 18
HM62W16255HC Series
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent,
copyright, trademark, or other intellectual property rights for information contained in this document.
Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual
property rights, in connection with use of the information contained in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you have
received the latest product standards or specifications before final design, purchase or use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,
contact Hitachi’s sales office before using the product in an application that demands especially high
quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of
bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic,
safety equipment or medical equipment for life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for
maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and
other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the
guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or
failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the
equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage
due to operation of the Hitachi product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without
written approval from Hitachi.
7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor
products.
Hitachi, Ltd.
Semiconductor & Integrated Circuits.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109
URL NorthAmerica : http://semiconductor.hitachi.com/
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For further information write to:
Hitachi Semiconductor
(America) Inc.
179 East Tasman Drive,
San Jose,CA 95134
Tel: <1> (408) 433-1990
Fax: <1>(408) 433-0223
Hitachi Europe GmbH
Electronic Components Group
Dornacher Straße 3
D-85622 Feldkirchen, Munich
Germany
Tel: <49> (89) 9 9180-0
Fax: <49> (89) 9 29 30 00
Hitachi Europe Ltd.
Electronic Components Group.
Whitebrook Park
Lower Cookham Road
Maidenhead
Berkshire SL6 8YA, United Kingdom
Tel: <44> (1628) 585000
Fax: <44> (1628) 585160
Hitachi Asia Ltd.
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Hitachi Tower
Singapore 049318
Tel: 535-2100
Fax: 535-1533
Hitachi Asia Ltd.
Taipei Branch Office
3rd Flr, Hung Kuo Building, No.167,
Tun Hwa North Road, Taipei (105)
Taiwan
Tel: <886> (2) 2718-3666
Fax: <886> (2) 2718-8180
Telex: 23222 HAS-TP
18
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7th Flr, North Tower, World Finance Centre,
Harbour City, Canton Road, Tsim Sha Tsui,
Kowloon, Hong Kong
Tel: <852> (2) 735 9218
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Telex: 40815 HITEC HX
Copyright © Hitachi, Ltd., 2000. All rights reserved. Printed in Japan.
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