Datasheet HM62V8512CLTTI-7 Datasheet (HIT)

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Page 1

HM62V8512CI Series

Wide Temperature Range Version

4 M SRAM (512-kword × 8-bit)

ADE-203-1215A (Z)

Rev. 1.0

Feb. 6, 2001

Description

The Hitachi HM62V8512CI is a 4-Mbit static RAM organized 512-kword × 8-bit. HM62V8512CI Series has realized higher density, higher performance and low power consumption by employing CMOS process technology (6-transistor memory cell). The HM62V8512CI Series offers low power standby power dissipation; therefore, it is suitable for battery backup systems. It is packaged in standard 32-pin TSOP II.

Features

• Single 3.0 V supply: 2.7 V to 3.6 V

• Access time: 70 ns (max)

• Power dissipation  Active: 6.0 mW/MHz (typ)  Standby: 2.4 µW (typ)

• Completely static memory. No clock or timing strobe required

• Equal access and cycle times

• Common data input and output: Three state output

• Directly LV-TTL compatible: All inputs and outputs

• Battery backup operation

• Operating temperature: –40 to +85˚C

Ordering Information

Type No. Access time Package

HM62V8512CLTTI-7 70 ns 400-mil 32-pin plastic TSOP II (TTP-32D)

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HM62V8512CI Series

Pin Arrangement

32-pin TSOP

A18 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 V

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Pin Description

Pin name Function

A0 to A18 Address input I/O0 to I/O7 Data input/output

CS Chip select OE Output enable WE Write enable

Power supply Ground

(Top view)

32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17

A15 A17

A13 A8 A9 A11

A10

I/O7 I/O6 I/O5 I/O4 I/O3

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Block Diagram

HM62V8512CI Series

LSB

MSB

A11

A8 A15 A18 A10 A13 A17 A16 A14 A12

I/O0

I/O7

Row Decoder

Input Data Control

•

LSB

Memory Matrix 2,048 2,048

Column Decoder

A3A2A1A0 A6A5

•

Column I/O

A4 A7

MSB

•

Timing Pulse Generator

Read/Write Control

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HM62V8512CI Series

Function Table

WE CS OE Mode VCC current Dout pin Ref. cycle

× H × Not selected I H L H Output disable I H L L Read I L L H Write I L L L Write I

, I

SB1

Note: ×: H or L

Absolute Maximum Ratings

Parameter Symbol Value Unit

Power supply voltage V Voltage on any pin relative to V

Power dissipation P

Operating temperature Topr –40 to +85 °C Storage temperature Tstg –55 to +125 °C Storage temperature under bias Tbias –40 to +85 °C

Notes: 1. VT min: –3.0 V for pulse half-width ≤ 30 ns.

2. Maximum voltage is 4.6 V.

–0.5 to +4.6 V –0.5*1 to VCC + 0.5*

1.0 W

High-Z — High-Z — Dout Read cycle Din Write cycle (1) Din Write cycle (2)

Recommended DC Operating Conditions (Ta = –40 to +85°C)

Parameter Symbol Min Typ Max Unit

Supply voltage V

Input high voltage V Input low voltage V

Note: 1. VIL min: –3.0 V for pulse half-width ≤ 30 ns.

2.7 3.0 3.6 V 000V

2.4 — VCC + 0.3 V

–0.3

— 0.6 V

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HM62V8512CI Series

DC Characteristics

Parameter Symbol Min Typ*1Max Unit Test conditions

Input leakage current |I Output leakage current |ILO|— — 1 µACS = VIH or OE = VIH or

Operating power supply current: DC

Operating power supply current I

Operating power supply current

Standby power supply current: DC

Standby power supply current (1): DC

Output low voltage V

Output high voltage V

Notes: 1. Typical values are at VCC = 3.0 V, Ta = +25°C and specified loading, and not guaranteed.

2. This characteristics is guaranteed only for L-version.

| — — 1 µA Vin = VSS to V

WE = V

— 5 10 mA CS = VIL,

others = V

CC1

— 15 30 mA Min cycle, duty = 100%

CS = V I

= 0 mA

I/O

CC2

— 2 10 mA Cycle time = 1 µs,

duty = 100% I

= 0 mA, CS ≤ 0.2 V

I/O

≥ VCC – 0.2 V,

≤ 0.2 V

SB1

— 0.1 0.3 mA CS = V

— 0.8*

20*

µA Vin ≥ 0 V,

CS ≥ V

— — 0.4 V IOL = 2.0 mA — — 0.2 V IOL = 100 µA

VCC – 0.2 — — V IOH = –100 µA

2.4 — — V IOH = –1.0 mA

, V

= VSS to V

I/O

, I

IH/VIL

, others = VIH/V

– 0.2 V

= 0 mA

I/O

Capacitance (Ta = +25°C, f = 1 MHz)

Parameter Symbol Typ Max Unit Test conditions

Input capacitance*

Input/output capacitance*1C Note: 1. This parameter is sampled and not 100% tested.

Cin — 8 pF Vin = 0 V

I/O

—10pFV

= 0 V

I/O

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HM62V8512CI Series

AC Characteristics (Ta = –40 to +85°C, VCC = 2.7 V to 3.6 V, unless otherwise noted.)

Test Conditions

• Input pulse levels: 0.4 V to 2.4 V

• Input rise and fall time: 5 ns

• Input timing reference levels: 1.4 V

• Output timing reference level: 0.8 V/2.0 V

• Output load (Including scope & jig)

Ω

Dout

500

50 pF

1.4 V

Read Cycle

HM62V8512CI

-7

Parameter Symbol Min Max Unit Notes

Read cycle time t Address access time t Chip select access time t Output enable to output valid t Chip selection to output in low-Z t Output enable to output in low-Z t Chip deselection to output in high-Z t Output disable to output in high-Z t Output hold from address change t

OLZ

OHZ

70 — ns —70ns —70ns —35ns 10 — ns 2 5 — ns 2 0 30 ns 1, 2 0 30 ns 1, 2 10 — ns

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HM62V8512CI Series

Write Cycle

HM62V8512CI

-7

Parameter Symbol Min Max Unit Notes

Write cycle time t Chip selection to end of write t Address setup time t Address valid to end of write t Write pulse width t Write recovery time t WE to output in high-Z t Data to write time overlap t Data hold from write time t Output active from output in high-Z t Output disable to output in high-Z t

Notes: 1. tHZ, t

OHZ

and t

are defined as the time at which the outputs achieve the open circuit conditions and

WHZ

are not referred to output voltage levels.

2. This parameter is sampled and not 100% tested.

3. A write occurs during the overlap (t

transition of CS going low or WE going low. A write ends at the earlier transition of CS going high or WE going high. t

4. t

is measured from CS going low to the end of write.

5. t

is measured from the address valid to the beginning of write.

6. t

is measured from the earlier of WE or CS going high to the end of write cycle.

is measured from the beginning of write to the end of write.

7. During this period, I/O pins are in the output state so that the input signals of the opposite phase to the outputs must not be applied.

8. If the CS low transition occurs simultaneously with the WE low transition or after the WE transition, the output remain in a high impedance state.

9. Dout is the same phase of the write data of this write cycle.

10.Dout is the read data of next address.

11.If CS is low during this period, I/O pins are in the output state. Therefore, the input signals of the opposite phase to the outputs must not be applied to them.

12.In the write cycle with OE low fixed, t data bus contention. t

tDW min + t

WHZ

OHZ

) of a low CS and a low WE. A write begins at the later

must satisfy the following equation to avoid a problem of

max

WHZ

70 — ns 60 — ns 4 0 — ns 5 60 — ns 50 — ns 3, 12 0 — ns 6 0 30 ns 1, 2, 7 30 — ns 0—ns 5 — ns 2 0 30 ns 1, 2, 7

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HM62V8512CI Series

Timing Waveforms

Read Timing Waveform (WE = VIH)

Address

OLZ

OHZ

Dout

Valid Data

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Write Timing Waveform (1) (OE Clock)

Address

HM62V8512CI Series

Dout

Din

OHZ

Valid Data

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HM62V8512CI Series

Write Timing Waveform (2) (OE Low Fixed)

Address

Dout

Din

WHZ

*11

*10

Valid Data

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Low VCC Data Retention Characteristics (Ta = –40 to +85°C)

HM62V8512CI Series

Parameter Symbol Min Typ Max Unit Test conditions*

VCC for data retention V Data retention current I

Chip deselect to data retention time t Operation recovery time t

CCDR

CDR

2——V CS ≥ VCC – 0.2 V, Vin ≥ 0 V — 0.8*320*1µA VCC = 3.0 V, Vin ≥ 0 V

CS ≥ V

– 0.2 V

0 — — ns See retention waveform tRC*4—— ns

Notes: 1. For L-version and 10 µA (max.) at Ta = –40 to +40°C.

2. CS controls address buffer, WE buffer, OE buffer, and Din buffer. In data retention mode, Vin levels (address, WE, OE, I/O) can be in the high impedance state.

3. Typical values are at V

4. t

= read cycle time.

= 3.0 V, Ta = +25°C and specified loading, and not guaranteed.

Low VCC Data Retention Timing Waveform (CS Controlled)

2.7 V

CDR

Data retention mode

2.4 V V

0 V

CS ≥ VCC – 0.2 V

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HM62V8512CI Series

Package Dimensions

HM62V8512CLTTI Series (TTP-32D)

20.95

21.35 Max

Unit: mm

10.16

*0.42 ± 0.08

0.40 ± 0.06

1.15 Max

1.20 Max

*Dimension including the plating thickness

Base material dimension

0.21

0.10

1.27

*0.17 ± 0.05

0.125 ± 0.04

11.76 ± 0.20

0.13 ± 0.05

Hitachi Code JEDEC EIAJ Mass

(reference value)

0° – 5°

0.80

0.50 ± 0.10

TTP-32D Conforms —

0.51 g

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HM62V8512CI Series

Cautions

1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document.

2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use.

3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However, contact Hitachi’s sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support.

4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product.

5. This product is not designed to be radiation resistant.

6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi.

7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor products.

Hitachi, Ltd.

Semiconductor & Integrated Circuits. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109

URL NorthAmerica : http://semiconductor.hitachi.com/

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For further information write to:

Hitachi Semiconductor (America) Inc. 179 East Tasman Drive, San Jose,CA 95134 Tel: <1> (408) 433-1990 Fax: <1>(408) 433-0223

Hitachi Europe GmbH Electronic Components Group Dornacher Straße 3 D-85622 Feldkirchen, Munich Germany Tel: <49> (89) 9 9180-0 Fax: <49> (89) 9 29 30 00

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URL : http://www.hitachi.com.sg Hitachi Asia Ltd.

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