Datasheet HM62V16256CLTT-5, HM62V16256CLTT-5SL, HM62V16256CLTT-7, HM62V16256CLTT-7SL Datasheet (HIT)

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HM62V16256C Series
4 M SRAM (256-kword × 16-bit)
ADE-203-1099D (Z)
Rev. 1.0
Jan. 31, 2001
Description
The Hitachi HM62V16256C Series is 4-Mbit static RAM organized 262,144-word × 16-bit. HM62V16256C Series has realized higher density, higher performance and low power consumption by employing CMOS process technology (6-transistor memory cell). It offers low power standby power dissipation; therefore, it is suitable for battery backup systems. It is packaged in standard 44-pin plastic TSOPII.
Features
Single 2.5 V and 3.0 V supply: 2.2 V to 3.6 V
Fast access time: 55 ns/70 ns (max)
Power dissipation:
Active: 5.0 mW/MHz (typ)(VCC = 2.5 V)
: 6.0 mW/MHz (typ) (VCC = 3.0 V)
Standby: 2 µW (typ) (VCC = 2.5 V)
: 2.4 µW (typ) (VCC = 3.0 V)
Completely static memory. No clock or timing strobe required
Equal access and cycle times
Common data input and output.
Three state output
Battery backup operation.
2 chip selection for battery backup
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HM62V16256C Series
Ordering Information
Type No. Access time Package
HM62V16256CLTT-5 HM62V16256CLTT-7
HM62V16256CLTT-5SL HM62V16256CLTT-7SL
55 ns 70 ns
55 ns 70 ns
400-mil 44-pin plastic TSOPII (normal-bend type) (TTP-44DB)
2
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Pin Arrangement
HM62V16256C Series
44-pin TSOP
A4 A3 A2 A1 A0
CS1
I/O0 I/O1 I/O2 I/O3 V
CC
V
SS
I/O4 I/O5 I/O6 I/O7 WE A17 A16 A15 A14 A13
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
(Top view)
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
A5 A6 A7
OE UB LB
I/O15 I/O14 I/O13 I/O12 V
SS
V
CC
I/O11 I/O10 I/O9 I/O8 CS2 A8 A9 A10 A11 A12
Pin Description
Pin name Function
A0 to A17 Address input I/O0 to I/O15 Data input/output CS1 Chip select 1 CS2 Chip select 2
WE Write enable OE Output enable LB Lower byte select UB Upper byte select
V
CC
V
SS
Power supply Ground
3
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HM62V16256C Series
Block Diagram
LSB
MSB
A12 A11 A10
A9
A8 A13 A14 A15 A16 A17
A7
I/O0
I/O15
Row decoder
Input data control
V
CC
V
SS
Memory matrix 2,048 x 2,048
Column I/O
Column decoder
CS2
CS1
LB
UB
WE
OE
Control logic
LSB
A4
A3
A2
A1
A5
A6
A0
MSB
4
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HM62V16256C Series
Operation Table
CS1 CS2 WE OE UB LB I/O0 to I/O7 I/O8 to I/O15 Operation
H ЧЧЧЧЧHigh-Z High-Z Standby × L ××××High-Z High-Z Standby ××××H H High-Z High-Z Standby
L H H L L L Dout Dout Read L H H L H L Dout High-Z Lower byte read L H H L L H High-Z Dout Upper byte read LHL×L L Din Din Write LHL×H L Din High-Z Lower byte write LHL×L H High-Z Din Upper byte write LHHH××High-Z High-Z Output disable
Note: H: VIH, L: VIL, ×: VIH or V
Absolute Maximum Ratings
IL
Parameter Symbol Value Unit
Power supply voltage relative to V Terminal voltage on any pin relative to V
SS
SS
Power dissipation P
V
CC
V
T
T
–0.5 to + 4.6 V –0.5*1 to VCC + 0.3*
2
V
1.0 W Storage temperature range Tstg –55 to +125 °C Storage temperature range under bias Tbias –20 to +85 °C
Notes: 1. VT min: –3.0 V for pulse half-width 30 ns.
2. Maximum voltage is +4.6 V.
DC Operating Conditions
Parameter Symbol Min Typ Max Unit Note
Supply voltage V
Input high voltage VCC = 2.2 V to 2.7 V V
VCC = 2.7 V to 3.6 V V
Input low voltage VCC = 2.2 V to 2.7 V V
VCC = 2.7 V to 3.6 V V
CC
V
SS
IH
IH
IL
IL
Ambient temperature range Ta –20 70 °C Note: 1. VIL min: –3.0 V for pulse half-width 30 ns.
2.2 2.5/3.0 3.6 V 000V
2.0 VCC + 0.3 V
2.0 VCC + 0.3 V –0.2 0.4 V 1 –0.3 0.6 V 1
5
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HM62V16256C Series
DC Characteristics
Parameter Symbol Min Typ*1Max Unit Test conditions Input leakage current |I Output leakage current |ILO|— —1 µACS1 = VIH or CS2 = VIL or
Operating current I
Average
HM62V16256C-5 I operating current
HM62V16256C-7 I
Standby current I Standby current I
Output high
VCC =2.2 V to 2.7 V V
voltage
VCC =2.7 V to 3.6 V V VCC =2.2 V to 3.6 V V
Output low
VCC =2.2 V to 2.7 V V
voltage
VCC =2.7 V to 3.6 V V VCC =2.2 V to 3.6 V V
Notes: 1. Typical values are at VCC = 2.5 V/3.0 V, Ta = +25°C and not guaranteed.
2. This characteristic is guaranteed only for L-version.
3. This characteristic is guaranteed only for L-SL version.
|——1 µA Vin = VSS to V
LI
OE = V L B = UB = V
CC
5 20 mA CS1 = VIL, CS2 = VIH,
Others = V
CC1
18 35 mA Min. cycle, duty = 100%,
I
= 0 mA, CS1 = VIL, CS2 = VIH,
I/O
Others = V
CC1
I
CC2
— 1530mA
2 5 mA Cycle time = 1 µs, duty = 100%,
I
= 0 mA, CS1 0.2 V,
I/O
CS2 V V
VCC – 0.2 V, VIL 0.2 V
IH
SB
SB1
0.01 0.3 mA CS2 = V
2
*
0.8 20 µA 0 V Vin
(1) 0 V CS2 0.2 V or (2) CS1 V
CS2 V
(3) LB = UB V
CS2 V CS1 0.2 V
3
I
*
SB1
OH
OH
OH
OL
OL
OL
0.8 10 µA
2.0 V IOH = –0.5 mA
2.4 V IOH = –1 mA VCC – 0.2— V IOH = –100 µA — 0.4 V IOL = 0.5 mA
0.4 V IOL = 2 mA — 0.2 V IOL = 100 µA
CC
or WE = VIL or
IH
, V
IH
I/O
, I
IH/VIL
I/O
IH/VIL
– 0.2 V
CC
IL
– 0.2 V,
CC
– 0.2 V or
CC
– 0.2 V
CC
– 0.2 V
CC
= VSS to V
= 0 mA
CC
6
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HM62V16256C Series
Capacitance (Ta = +25°C, f = 1.0 MHz)
Parameter Symbol Min Typ Max Unit Test conditions Note
Input capacitance Cin 8 pF Vin = 0 V 1 Input/output capacitance C
Note: 1. This parameter is sampled and not 100% tested.
I/O
10 pF V
= 0 V 1
I/O
7
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HM62V16256C Series
AC Characteristics (Ta = –20 to +70°C, VCC = 2.2 V to 3.6 V, unless otherwise noted.)
Test Conditions
Input pulse levels: VIL = 0.4 V, VIH = 2.0 V (VCC = 2.2 V to 2.7 V)
VIL = 0.4 V, VIH = 2.2 V (VCC = 2.7 V to 3.6 V)
Input rise and fall time: 5 ns
Input timing reference levels: 1.1 V (VCC = 2.2 V to 2.7 V)
Output timing reference levels: 1.1 V (VCC = 2.2 V to 2.7 V)
Input timing reference levels: 1.4 V (VCC = 2.7 V to 3.6 V)
Output timing reference levels: 1.4 V (HM62V16256C–5, VCC = 2.7 V to 3.6 V)
: 2.0 V/0.8 V (HM62V16256C–7, VCC = 2.7 V to 3.6 V)
Output load: See figures (Including scope and jig)
V
TM
Dout
30pF
Output load (A)
(VCC = 2.2 V to 2.7 V)
R1
R2
R1 = 3070 R2 = 3150
VTM = 2.3 V
1.4 V
RL=500
Dout
50pF
Output load (B)
(VCC = 2.7 V to 3.6 V)
8
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HM62V16256C Series
Read Cycle
HM62V16256C
-5 -7
Parameter Symbol Min Max Min Max Unit Notes
Read cycle time t Address access time t Chip select access time t
Output enable to output valid t Output hold from address change t LB, UB access time t Chip select to output in low-Z t
LB, UB enable to low-z t Output enable to output in low-Z t Chip deselect to output in high-Z t
LB, UB disable to high-Z t Output disable to output in high-Z t
t
t
t
RC
AA
ACS1
ACS2
OE
OH
BA
CLZ1
CLZ2
BLZ
OLZ
CHZ1
CHZ2
BHZ
OHZ
55 70 ns — 55 70 ns — 55 70 ns — 55 70 ns — 35 40 ns 10 10 ns — 55 70 ns 10 10 ns 2, 3 10 10 ns 2, 3 5 5 ns 2, 3 5 5 ns 2, 3 0 20 0 25 ns 1, 2, 3 0 20 0 25 ns 1, 2, 3 0 20 0 25 ns 1, 2, 3 0 20 0 25 ns 1, 2, 3
9
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HM62V16256C Series
Write Cycle
HM62V16256C
-5 -7
Parameter Symbol Min Max Min Max Unit Notes
Write cycle time t Address valid to end of write t Chip selection to end of write t Write pulse width t LB, UB valid to end of write t Address setup time t Write recovery time t Data to write time overlap t Data hold from write time t Output active from end of write t Output disable to output in High-Z t Write to output in high-Z t
Notes: 1. t
CHZ
, t
, t
OHZ
WHZ
and t
are defined as the time at which the outputs achieve the open circuit
BHZ
conditions and are not referred to output voltage levels.
2. This parameter is sampled and not 100% tested.
3. At any given temperature and voltage condition, t and from device to device.
4. A write occures during the overlap of a low CS1, a high CS2, a low WE and a low LB or a low UB . A write begins at the latest transition among CS1 going low, CS2 going high, WE going low and LB going low or UB going low. A write ends at the earliest transition among CS1 going high, CS2 going low, WE going high and LB going high or UB going high. t of write to the end of write.
5. t
is measured from the later of CS1 going low or CS2 going high to the end of write.
CW
6. t
is measured from the address valid to the beginning of write.
AS
7. t
is measured from the earliest of CS1 or WE going high or CS2 going low to the end of write
WR
cycle.
WC
AW
CW
WP
BW
AS
WR
DW
DH
OW
OHZ
WHZ
55 70 ns 50 60 ns 50 60 ns 5 40 50 ns 4 50 55 ns 0—0—ns6 0—0—ns7 25 30 ns 0—0—ns 5—5—ns2 0 20 0 25 ns 1, 2 0 20 0 25 ns 1, 2
max is less than tLZ min both for a given device
HZ
is measured from the beginning
WP
10
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Timing Waveform
Read Cycle
HM62V16256C Series
t
RC
Address
CS1
CS2
LB, UB
OE
Dout
t
AA
High impedance
Valid address
t
ACS1
2, 3
t
*
CLZ1
t
ACS2
2, 3
t
*
CLZ2
t
BA
2, 3
t
*
BLZ
t
OLZ
*
t
OE
2, 3
Valid data
t
CHZ1
t
CHZ2
t
BHZ
t
OHZ
1, 2, 3
*
*
1, 2, 3
*
1, 2, 3
*
t
OH
1, 2, 3
11
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HM62V16256C Series
Write Cycle (1) (WE Clock)
t
WC
Address
CS1
CS2
LB, UB
WE
Din
Dout
tAS*
Valid address
7
5
tCW*
5
tCW*
t
BW
t
AW
4
tWP*
6
t
DW
tWR*
t
DH
Valid data
1, 2
*
t
WHZ
tOW*
2
High impedance
12
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Write Cycle (2) (CS Clock, OE = VIH)
t
HM62V16256C Series
WC
Address
CS1
CS2
LB, UB
WE
Din
tAS*
Valid address
t
6
AW
t
BW
tCW*
tCW*
tWP*
5
5
4
t
DW
tWR*
t
DH
7
Valid data
Dout
High impedance
13
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HM62V16256C Series
Write Cycle (3) (LB, UB Clock, OE = VIH)
t
WC
Address
CS1
CS2
LB, UB
WE
Din
tAS*
Valid address
t
AW
6
tCW*
tCW*
t
BW
5
5
tWP*
7
tWR*
4
t
DW
t
DH
Valid data
14
Dout
High impedance
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Low VCC Data Retention Characteristics (Ta = –20 to +70°C)
HM62V16256C Series
Parameter Symbol Min Typ*4Max Unit Test conditions* VCC for data retention V
DR
2.0 3.6 V Vin 0V (1) 0 V CS2 0.2 V or (2) CS2 V
CS1 V
– 0.2 V
CC
– 0.2 V or
CC
(3) LB = UB V
CS2 V
– 0.2 V,
CC
CS1 0.2 V
Data retention current I
CCDR
1
*
0.8 20 µAV
= 3.0 V, Vin 0V
CC
(1) 0 V CS2 0.2 V or (2) CS2 V
CS1 V
– 0.2 V,
CC
– 0.2 V or
CC
(3) LB = UB V
CS2 V
– 0.2 V,
CC
CS1 0.2 V
2
I
Chip deselect to data
t
CCDR
CDR
*
0.8 10 µA 0 ns See retention waveform
retention time Operation recovery time t
R
tRC*
5
——ns
Notes: 1. This characteristic is guaranteed only for L-version, 10 µA max. at Ta = –20 to +40°C.
2. This characteristic is guaranteed only for L-SL version, 5 µA max. at Ta = –20 to +40°C.
3. CS2 controls address buffer, WE buffer, CS1 buffer, OE buffer, LB, UB buffer and Din buffer. If CS2 controls data retention mode, Vin levels (address, WE, OE, CS1, LB, UB, I/O) can be in the high impedance state. If CS1 controls data retention mode, CS2 must be CS2 V
– 0.2 V or 0 V
CC
≤ CS2 ≤ 0.2 V. The other input levels (address, WE, OE, LB, UB, I/O) can be in the high impedance state.
4. Typical values are at V
5. t
= read cycle time.
RC
= 3.0 V, Ta = +25˚C and not guaranteed.
CC
3
– 0.2 V,
CC
– 0.2 V,
CC
15
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HM62V16256C Series
Low VCC Data Retention Timing Waveform (1) (CS1 Controlled)
t
CDR
V
CC
Data retention mode
2.2 V
V
DR
2.0 V
CS1
0 V
CS1 V – 0.2 V
CC
Low VCC Data Retention Timing Waveform (2) (CS2 Controlled)
Data retention modet
< <
0 V CS2 0.2 V
V
CC
2.2 V
CS2
V
DR
0.4 V
0 V
CDR
t
R
t
R
Low VCC Data Retention Timing Waveform (3) (LB, UB Controlled)
Data retention mode
LB, UB V – 0.2 V
CC
LB, UB
16
V
CC
2.2 V
V
DR
2.0 V
0 V
t
CDR
t
R
Page 17
Package Dimensions
HM62V16256CLTT Series (TTP-44DB)
18.41
18.81 Max
44 23
HM62V16256C Series
Unit: mm
10.16
122
*0.30 ± 0.10
0.25 ± 0.05
1.005 Max
1.20 Max
*Dimension including the plating thickness
Base material dimension
0.80
0.13
0.10
M
*0.17 ± 0.05
0.125 ± 0.04
11.76 ± 0.20
0.13 ± 0.05
Hitachi Code JEDEC EIAJ Mass
0° – 5°
(reference value)
0.80
0.50 ± 0.10
TTP-44DB — —
0.43 g
17
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HM62V16256C Series
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However, contact Hitachi’s sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi.
7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor products.
Hitachi, Ltd.
Semiconductor & Integrated Circuits. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109
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For further information write to:
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URL : http://www.hitachi.com.sg Hitachi Asia Ltd.
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18
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Copyright © Hitachi, Ltd., 2000. All rights reserved. Printed in Japan.
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