Datasheet HM628512BFP-5, HM628512BFP-7 Datasheet (HIT)

HM628512BFP Series

4 M SRAM (512-kword × 8-bit)

ADE-203-1078B (Z)

Rev. 2.0

Nov. 23, 1999

Description

The Hitachi HM628512BFP is a 4-Mbit static RAM organized 512-kword × 8-bit. It realizes higher density,
higher performance and low power consumption by employing Hi-CMOS process technology. It is packaged
in standard 32-pin SOP.

Features

• Single 5 V supply

• Access time: 55/70 ns (max)

• Power dissipation
 Active: 50 mW/MHz (typ)
 Standby: 2 mW (max)

• Completely static memory. No clock or timing strobe required

• Equal access and cycle times

• Common data input and output: Three state output

• Directly TTL compatible: All inputs and outputs

Ordering Information

Type No. Access time Package

HM628512BFP-5
HM628512BFP-7

55 ns
70 ns

525-mil 32-pin plastic SOP (FP-32D)

HM628512BFP Series

Pin Arrangement

32-pin SOP

A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
V

SS

Pin Description

Pin name Function

A0 to A18 Address input
I/O0 to I/O7 Data input/output

CS Chip select
OE Output enable
WE Write enable

V

CC

V

SS

Power supply
Ground

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

(Top view)

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

V

CC

A15
A17

WE

A13
A8
A9
A11

OE

A10

CS

I/O7
I/O6
I/O5
I/O4
I/O3

2

Block Diagram

A18
A16

A1
A0

A2
A12
A14

A3

A7

A6

Row
Decoder

HM628512BFP Series

V

CC

V

SS

•

•

•

•

•

Memory Matrix

×

1,024 4,096

I/O0

I/O7

CS

WE

OE

•

•

Input
Data
Control

Timing Pulse Generator

Read/Write Control

Column I/O

Column Decoder

A17

A13

A15

A9

A8

•

•

•

•

A10A11

A4

A5

3

HM628512BFP Series

Function Table

WE CS OE Mode VCC current Dout pin Ref. cycle

× H × Not selected I
H L H Output disable I
H L L Read I
L L H Write I
L L L Write I

, I

SB

SB1

CC

CC

CC

CC

Note: ×: H or L

Absolute Maximum Ratings

Parameter Symbol Value Unit

Power supply voltage V
Voltage on any pin relative to V

SS

Power dissipation P

CC

V

T

T

Operating temperature Topr –20 to +70 °C
Storage temperature Tstg –55 to +125 °C
Storage temperature under bias Tbias –20 to +85 °C

Notes: 1. –3.0 V for pulse half-width ≤ 30 ns

2. Maximum voltage is 7.0 V

–0.5 to +7.0 V
–0.5*1 to VCC + 0.3*

1.0 W

High-Z —
High-Z —
Dout Read cycle
Din Write cycle (1)
Din Write cycle (2)

2

V

Recommended DC Operating Conditions (Ta = –20 to +70°C)

Parameter Symbol Min Typ Max Unit

Supply voltage V

Input high voltage V
Input low voltage V

CC

V

SS

IH

IL

Note: 1. –3.0 V for pulse half-width ≤ 30 ns

4

4.5 5.0 5.5 V
000V

2.2 — VCC + 0.3 V

*1

–0.3

— 0.8 V

HM628512BFP Series

DC Characteristics (Ta = –20 to +70°C, VCC = 5 V ±10% , VSS = 0 V)

Parameter Symbol Min Typ*1Max Unit Test conditions

Input leakage current |I
Output leakage current |ILO|——1µA CS = VIH or OE = VIH or

Operating power supply current: DC I

Operating power supply current I

Operating power supply current I

Standby power supply current: DC I
Standby power supply current (1): DC I
Output low voltage V
Output high voltage V

Note: 1. Typical values are at VCC = 5.0 V, Ta = +25°C and specified loading, and not guaranteed.

|——1µA Vin = VSS to V

LI

WE = V

CC

— 8 15 mA CS = VIL,

IL

others = V

CC1

CC2

— 40 60 mA Min cycle, duty = 100%

CS = V
I

I/O

, others = VIH/V

IL

= 0 mA

— 10 20 mA Cycle time = 1 µs,

duty = 100%
I

= 0 mA, CS ≤ 0.2 V

I/O

V

≥ VCC – 0.2 V, VIL ≤ 0.2 V

IH

SB

SB1

OL

OH

—1 3 mACS = V

IH

— 300 400 µA Vin ≥ 0 V, CS ≥ VCC – 0.2 V
— — 0.4 V IOL = 2.1 mA

2.4 — — V IOH = –1.0 mA

, V

I/O

IH/VIL

CC

= VSS to V

, I

= 0 mA

I/O

CC

IL

Capacitance (Ta = +25°C, f = 1 MHz)

Parameter Symbol Typ Max Unit Test conditions

Input capacitance*

1

Input/output capacitance*1C
Note: 1. This parameter is sampled and not 100% tested.

Cin — 8 pF Vin = 0 V

I/O

—10pFV

= 0 V

I/O

5

HM628512BFP Series

AC Characteristics (Ta = –20 to +70°C, VCC = 5 V ± 10%, unless otherwise noted.)

Test Conditions

• Input pulse levels: 0.8 V to 2.4 V

• Input rise and fall time: 5 ns

• Input and output timing reference levels: 1.5 V

• Output load: 1 TTL Gate + CL (50 pF) (HM628512BFP-5) (Including scope & jig)

1 TTL Gate + CL (100 pF) (HM628512BFP-7) (Including scope & jig)

Read Cycle

HM628512BFP

-5 -7

Parameter Symbol Min Max Min Max Unit Notes

Read cycle time t
Address access time t
Chip select access time t
Output enable to output valid t
Chip selection to output in low-Z t
Output enable to output in low-Z t
Chip deselection to output in high-Z t
Output disable to output in high-Z t
Output hold from address change t

RC

AA

CO

OE

LZ

OLZ

HZ

OHZ

OH

55 — 70 — ns
— 55 — 70 ns
— 55 — 70 ns
— 25 — 35 ns
10 — 10 — ns 2
5 — 5 — ns 2
0 20 0 25 ns 1, 2
0 20 0 25 ns 1, 2
10 — 10 — ns

6

HM628512BFP Series

Write Cycle

HM628512BFP

-5 -7

Parameter Symbol Min Max Min Max Unit Notes

Write cycle time t
Chip selection to end of write t
Address setup time t
Address valid to end of write t
Write pulse width t
Write recovery time t
WE to output in high-Z t
Data to write time overlap t
Data hold from write time t
Output active from output in high-Z t
Output disable to output in high-Z t

Notes: 1. tHZ, t

OHZ

and t

are defined as the time at which the outputs achieve the open circuit conditions and

WHZ

are not referred to output voltage levels.

2. This parameter is sampled and not 100% tested.

3. A write occurs during the overlap (t
transition of CS going low or WE going low. A write ends at the earlier transition of CS going high
or WE going high. t

4. t

is measured from CS going low to the end of write.

CW

5. t

is measured from the address valid to the beginning of write.

AS

6. t

is measured from the earlier of WE or CS going high to the end of write cycle.

WR

is measured from the beginning of write to the end of write.

WP

7. During this period, I/O pins are in the output state so that the input signals of the opposite phase to
the outputs must not be applied.

8. If the CS low transition occurs simultaneously with the WE low transition or after the WE transition,
the output remain in a high impedance state.

9. Dout is the same phase of the write data of this write cycle.

10.Dout is the read data of next address.

11.If CS is low during this period, I/O pins are in the output state. Therefore, the input signals of the
opposite phase to the outputs must not be applied to them.

12.In the write cycle with OE low fixed, t
data bus contention. t

≥ tDW min + t

WP

WC

CW

AS

AW

WP

WR

WHZ

DW

DH

OW

OHZ

55 — 70 — ns
50 — 60 — ns 4
0 — 0 — ns 5
50 — 60 — ns
40 — 50 — ns 3, 12
0 — 0 — ns 6
0 20 0 25 ns 1, 2, 7
25 — 30 — ns
0—0—ns
5 — 5 — ns 2
0 20 0 25 ns 1, 2, 7

) of a low CS and a low WE. A write begins at the later

WP

must satisfy the following equation to avoid a problem of

WP

max

WHZ

7

HM628512BFP Series

Timing Waveforms

Read Timing Waveform (WE = VIH)

Address

CS

OE

t

RC

t

AA

t

CO

t

LZ

t

OE

t

OLZ

t

HZ

t

OHZ

Dout

Valid Data

t

OH

8

Write Timing Waveform (1) (OE Clock)

Address

t

HM628512BFP Series

WC

OE

CS

WE

Dout

Din

t

AW

t

CW

*8

t

AS

t

OHZ

t

WP

t

DW

t

WR

t

DH

Valid Data

9

HM628512BFP Series

Write Timing Waveform (2) (OE Low Fixed)

Address

t

WC

CS

WE

Dout

Din

t

CW

*8

t

AW

t

WP

t

AS

t

WHZ

t

DW

t

t

DH

WR

t

OW

t

OH

*9

*11

*10

Valid Data

10

Package Dimensions

HM628512BFP Series (FP-32D)

20.45

20.95 Max

32

HM628512BFP Series

Unit: mm

17

11.30

1

1.00 Max

0.15

0.10

M

1.27

*0.40 ± 0.08

0.38 ± 0.06

*Dimension including the plating thickness

Base material dimension

16

+ 0.12

– 0.10

0.15

3.00 Max

0.20 ± 0.04

*0.22 ± 0.05

Hitachi Code
JEDEC
EIAJ
Weight

(reference value)

14.14 ± 0.30

1.42

0° – 8°

0.80 ± 0.20

FP-32D
Conforms
—

1.3 g

11

HM628512BFP Series

Cautions

1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent,
copyright, trademark, or other intellectual property rights for information contained in this document.
Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual
property rights, in connection with use of the information contained in this document.

2. Products and product specifications may be subject to change without notice. Confirm that you have
received the latest product standards or specifications before final design, purchase or use.

3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,
contact Hitachi’s sales office before using the product in an application that demands especially high
quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of
bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic,
safety equipment or medical equipment for life support.

4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for
maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and
other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the
guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or
failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the
equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage
due to operation of the Hitachi product.

5. This product is not designed to be radiation resistant.

6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without
written approval from Hitachi.

7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor
products.

Hitachi, Ltd.

Semiconductor & Integrated Circuits.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Tel: Tokyo [phone] Fax: [phone]

URL NorthAmerica : http:semiconductor.hitachi.com/

For further information write to:

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Fax: <1>[phone]

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12

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Tel: <852> (2) 735 9218
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Copyright © Hitachi, Ltd., 1998. All rights reserved. Printed in Japan.

HM628512BFP Series

Revision Record

Rev. Date Contents of Modification Drawn by Approved by

1.0 Jun. 29, 1999 Initial issue S. Kunito K. Imato

2.0 Nov. 23, 1999 Addition of HM628512BFP-5 Series

13