Datasheet HM6264BLFPI-10T, HM6264BLFPI-12T, HM6264BLPI-10, HM6264BLPI-12 Datasheet (HIT)

HM6264BI Series

64k SRAM (8-kword × 8-bit)

Wide Temperature Range version

ADE-203-492C (Z)

Rev. 3.0

May. 8, 2000

Description

The Hitachi HM6264BI is 64k-bit static RAM organized 8-kword × 8-bit. It realizes higher performance and
low power consumption by 1.5 µm CMOS process technology. The device, packaged in 450 mil SOP (foot
print pitch width), 600 mil plastic DIP, is available for high density mounting.

Features

• Single 5 V supply: 5 V ± 10%

• Access time: 100/120 ns (max)

• Power dissipation:
 Standby: 10 µW (typ)
 Operation: 15 mW (typ) (f = 1 MHz)

• Completely static memory
 No clock or timing strobe required

• Equal access and cycle times

• Common data input and output
 Three state output

• Directly TTL compatible
 All inputs and outputs

• Battery backup operation capability

• Operating temperature range: –40˚C to +85˚C

HM6264BI Series

Ordering Information

Type No. Access time Package

HM6264BLPI-10
HM6264BLPI-12

HM6264BLFPI-10T
HM6264BLFPI-12T

Pin Arrangement

100 ns
120 ns

100 ns
120 ns

600-mil, 28-pin plastic DIP (DP-28)

450-mil, 28-pin plastic SOP(FP-28DA)

HM6264BLPI/BLFPI Series

1

NC

A12

A7
A6

A4

A0
I/O1
I/O2

I/O3

V

SS

2
3

4
5A5
6
7A3
8A2
9A1
10
11
12
13
14

28
27

24
23
22
21
20
19
18

V

CC

WE

CS226
A825
A9
A11

OE

A10

CS1

I/O8
I/O7
I/O617
I/O516
I/O415

(Top view)

2

Pin Description

Pin name Function

A0 to A12 Address input
I/O1 to I/O8 Data input/output
CS1 Chip select 1
CS2 Chip select 2

WE Write enable
OE Output enable

NC No connection
V

CC

V

SS

Power supply
Ground

Block Diagram

A11

A8
A9

A7

A12

A5
A6

A4

Row

decoder

Memory array

256 × 256

HM6264BI Series

V

CC

V

SS

I/O1

I/O8

CS2

CS1

WE

OE

Column I/O

Input

data

Column decoder

control

A1 A3

A2 A0 A10

Timing pulse generator

Read, Write control

3

HM6264BI Series

Function Table

WE CS1 CS2 OE Mode VCC current I/O pin Ref. cycle

× H ××Not selected (power down) I
××L × Not selected (power down) ISB, I

H L H H Output disable I
H L H L Read I
L L H H Write I
L L H L Write I

, I

SB

SB1

SB1

CC

CC

CC

CC

Note: ×: H or L

Absolute Maximum Ratings

Parameter Symbol Value Unit

Power supply voltage*
Terminal voltage*

1

1

Power dissipation P
Operating temperature Topr –40 to +85 °C
Storage temperature Tstg –55 to +125 °C
Storage temperature under bias Tbias –40 to +85 °C

Notes: 1. Relative to V

SS

2. VT min: –3.0 V for pulse half-width ≤ 50 ns

3. Maximum voltage is 7.0 V

V

CC

V

T

T

–0.5 to +7.0 V
–0.5*2 to VCC + 0.3*3V

1.0 W

High-Z —
High-Z —
High-Z —
Dout Read cycle (1)–(3)
Din Write cycle (1)
Din Write cycle (2)

Recommended DC Operating Conditions (Ta = –40 to +85°C)

Parameter Symbol Min Typ Max Unit

Supply voltage V

Input high voltage V
Input low voltage V

CC

V

SS

IH

IL

Note: 1. VIL min: –3.0 V for pulse half-width ≤ 50 ns

4

4.5 5.0 5.5 V
000V

2.4 — VCC + 0.3 V

1

–0.3*

— 0.6 V

HM6264BI Series

DC Characteristics (Ta = –40 to +85°C, VCC = 5 V ±10%, VSS = 0 V)

Parameter Symbol Min Typ*1Max Unit Test conditions

Input leakage current |I
Output leakage current |ILO| ——2 µA CS1 = VIH or CS2 = VIL or OE = VIH or

Operating power supply
current

Average operating power
supply current

Standby power supply
current

Output low voltage V
Output high voltage V

Notes: 1. Typical values are at VCC = 5.0 V, Ta = +25°C and not guaranteed.

2. V

min = –0.3V

IL

| ——2 µA Vin = VSS to V

LI

WE = V

I

CCDC

— 7 20 mA CS1 = VIL, CS2 = VIH, I

others = V

I

CC1

— 30 50 mA Min cycle, duty = 100%,

CS1 = V
others = V

I

CC2

— 3 8 mA Cycle time = 1 µs, duty = 100%, I

CS1 ≤ 0.2 V, CS2 ≥ V
V

≥ VCC – 0.2 V, VIL ≤ 0.2 V

IH

I

SB

I

SB1

—13mACS1 = VIH, CS2 = V

2

*

— 2 200 µA CS1 ≥ VCC – 0.2 V, CS2 ≥ VCC – 0.2 V or

0 V ≤ CS2 ≤ 0.2 V, 0 V ≤ Vin

OL

OH

— — 0.4 V IOL = 2.1 mA

2.4 — — V IOH = –1.0 mA

CC

, V

= V

IL

I/O

IH/VIL

, CS2 = VIH, I

IL

IH/VIL

SS

to V

CC

IL

CC

= 0 mA

I/O

= 0 mA

I/O

– 0.2 V,

= 0 mA

I/O

Capacitance (Ta = 25°C, f = 1.0 MHz)

Parameter Symbol Min Typ Max Unit Test conditions

Input capacitance*
Input/output capacitance*

1

1

Note: 1. This parameter is sampled and not 100% tested.

Cin — — 5 pF Vin = 0 V
C

I/O

——7 pFV

= 0 V

I/O

5

HM6264BI Series

AC Characteristics (Ta = –40 to +85°C, VCC = 5 V ± 10%, unless otherwise noted.)

Test Conditions

• Input pulse levels: 0.6 V to 2.4 V

• Input and output timing reference level: 1.5 V

• Input rise and fall time: 10 ns

• Output load: 1 TTL Gate + CL (100 pF) (Including scope & jig)

Read Cycle

HM6264BI-10 HM6264BI-12

Parameter Symbol Min Max Min Max Unit Notes

Read cycle time t
Address access time t
Chip select access time CS1 t

CS2 t
Output enable to output valid t
Chip selection to output in low-Z CS1 t

CS2 t
Output enable to output in low-Z t
Chip deselection in to output in high-Z CS1 t

CS2 t
Output disable to output in high-Z t
Output hold from address change t

RC

AA

CO1

CO2

OE

LZ1

LZ2

OLZ

HZ1

HZ2

OHZ

OH

Notes: 1. tHZ is defined as the time at which the outputs achieve the open circuit conditions and are not

referred to output voltage levels.

2. At any given temperature and voltage condition, t
given device and from device to device.

3. Address must be valid prior to or simultaneously with CS1 going low or CS2 going high.

100 — 120 — ns
— 100 — 120 ns
— 100 — 120 ns
— 100 — 120 ns
— 50 — 60 ns
10 — 10 — ns 2
10 — 10 — ns 2
5—5—ns2
0 35 0 40 ns 1, 2
0 35 0 40 ns 1, 2
0 35 0 40 ns 1, 2
10 — 10 — ns

maximum is less than tLZ minimum both for a

HZ

6

Read Timing Waveform (1) (WE = VIH)

HM6264BI Series

t

RC

Address

Valid address

t

AA

t

CO1

CS1

t

LZ1

t

CO2

CS2

t

LZ2

OE

Dout

High Impedance

Read Timing Waveform (2) (WE = VIH, OE = VIL)

Address

t

OH

Valid address

t

AA

t

OLZ

t

HZ1

t

OE

t

HZ2

t

OHZ

Valid data

t

OH

t

OH

Dout

Valid data

7

HM6264BI Series

Read Timing Waveform (3) (WE = VIH, OE = VIL)*

t

CS1

CS2

Dout

CO1

t

LZ1

t

CO2

t

LZ2

3

t

HZ1

t

HZ2

Valid data

8

HM6264BI Series

Write Cycle

HM6264BI-10 HM6264BI-12

Parameter Symbol Min Max Min Max Unit Notes

Write cycle time t
Chip selection to end of write t
Address setup time t
Address valid to end of write t
Write pulse width t
Write recovery time t
WE to output in high-Z t
Data to write time overlap t
Data hold from write time t
Output active from end of write t
Output disable to output in high-Z t

WC

CW

AS

AW

WP

WR

WHZ

DW

DH

OW

OHZ

Notes: 1. A write occurs during the overlap of a low CS1, and high CS2, and a high WE. A write begins at

the latest transition among CS1 going low,CS2 going high and WE going low. A write ends at the
earliest transition among CS1 going high CS2 going low and WE going high. Time t
from the beginning of write to the end of write.

2. t

is measured from the later of CS1 going low or CS2 going high to the end of write.

CW

3. t

is measured from the address valid to the beginning of write.

AS

4. t

is measured from the earliest of CS1 or WE going high or CS2 going low to the end of write

WR

cycle.

5. During this period, I/O pins are in the output state, therefore the input signals of the opposite phase
to the outputs must not be applied.

6. If CS1 goes low simultaneously with WE going low after WE goes low, the outputs remain in high
impedance state.

7. Dout is the same phase of the written data in this write cycle.

8. Dout is the read data of the next address

9. In the write cycle with OE low fixed, t

must satisfy the following equation to avoid a problem of

WP

data bus contention
t

≥ t

WP

max + tDW min.

WHZ

100 — 120 — ns
80 — 85 — ns 2
0—0—ns3
80 — 85 — ns
60 — 70 — ns 1, 9
0—0—ns4
0 35 0 40 ns 5
40 — 40 — ns
0—0—ns
5—5—ns
0 35 0 40 ns 5

is measured

WP

9

HM6264BI Series

Write Timing Waveform (1) (OE Clock)

t

WC

Address

OE

CS1

CS2

WE

Dout

Din

t

AS

High Impedance

Valid address

t

*1

t

AW

t

OHZ

CW

t

WP

t

DW

t

WR

High Impedance

t

DH

Valid data

10

Write Timing Waveform (2) (OE Low Fixed) (OE = VIL)

t

WC

HM6264BI Series

Address

CS1

CS2

WE

Dout

Din

*1

t

AS

High Impedance

Valid address

t

AW

t

CW

t

WP

t

WHZ

t

DW

Valid data

t

WR

t

t

DH

OW

t

OH

*2

*4

*3

11

HM6264BI Series

Low VCC Data Retention Characteristics (Ta = –40 to +85°C)

Parameter Symbol Min Typ*1Max Unit Test conditions*

VCC for data retention V

DR

2.0 — — V CS1 ≥ VCC –0.2 V,
CS2 ≥ V

–0.2 V or CS2 ≤ 0.2 V

CC

Vin ≥ 0 V

Data retention current I

CCDR

—1*1100*2µAVCC = 3.0 V, 0 V ≤ Vin ≤ V

CS1 ≥ VCC –0.2 V, CS2 ≥ VCC –0.2 V
or 0 V ≤ CS2 ≤ 0.2 V

Chip deselect to data

t

CDR

0 — — ns See retention waveform

retention time
Operation recovery time t

R

5 ——ms

Notes: 1. Reference data at Ta = 25°C.

2. 10 µA max at Ta = –40 to + 40°C.

3. CS2 controls address buffer, WE buffer, CS1 buffer, OE buffer, and Din buffer. If CS2 controls
data retention mode, Vin levels (address, WE, OE, CS1, I/O) can be in the high impedance state. If
CS1 controls data retention mode, CS2 must be CS2 ≥ V

– 0.2 V or 0 V ≤ CS2 ≤ 0.2 V. The

CC

other input levels (address, WE, OE, I/O) can be in the high impedance state.

3

CC

12

Low VCC Data Retention Timing Waveform (1) (CS1 Controlled)

HM6264BI Series

t

CDR

V

CC

Data retention mode

4.5 V

2.4 V
V

DR

CS1

CS1 ≥ VCC – 0.2 V

0 V

Low VCC Data Retention Timing Waveform (2) (CS2 Controlled)

Data retention mode

0 V ≤ CS2 ≤ 0.2 V

V

CC

4.5 V
CS2

V

DR

0.6 V
0 V

t

CDR

t

R

t

R

13

HM6264BI Series

Package Dimensions

HM6264BLPI Series (DP-28)

28

1

1.9 Max

2.54 ± 0.25

1.2

35.6

36.5 Max

0.48 ± 0.10

15

14

13.4

14.6 Max

5.70 Max

2.54 Min

0.51 Min

Hitachi Code
JEDEC
EIAJ
Weight

(reference value)

0° – 15°

15.24

0.25

DP-28
—
Conforms

4.6 g

+ 0.11
– 0.05

Unit: mm

14

Package Dimensions (cont.)

HM6264BLFPI Series (FP-28DA)

18.00

18.75 Max

HM6264BI Series

Unit: mm

28

1

1.12 Max

1.27

*0.40 ± 0.08

0.38 ± 0.06

*Dimension including the plating thickness

Base material dimension

0.20

0.15

15

8.40

14

3.00 Max

± 0.04

0.15

*0.17 ± 0.05

11.80 ± 0.30

1.70

0° – 8°

+ 0.15

– 0.10

0.20

M

Hitachi Code
JEDEC
EIAJ
Weight

1.00 ± 0.20

(reference value)

FP-28DA
Conforms
Conforms

0.82 g

15

HM6264BI Series

Cautions

1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent,
copyright, trademark, or other intellectual property rights for information contained in this document.
Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual
property rights, in connection with use of the information contained in this document.

2. Products and product specifications may be subject to change without notice. Confirm that you have
received the latest product standards or specifications before final design, purchase or use.

3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,
contact Hitachi’s sales office before using the product in an application that demands especially high
quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of
bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic,
safety equipment or medical equipment for life support.

4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for
maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and
other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the
guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or
failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the
equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage
due to operation of the Hitachi product.

5. This product is not designed to be radiation resistant.

6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without
written approval from Hitachi.

7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor
products.

Hitachi, Ltd.

Semiconductor & Integrated Circuits.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Tel: Tokyo [phone] Fax: [phone]

URL NorthAmerica : http:semiconductor.hitachi.com/

For further information write to:

Hitachi Semiconductor
(America) Inc.
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Tel: <1> [phone]
Fax: <1>[phone]

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Asia (Taiwan) : http://www.hitachi.com.tw/E/Product/SICD_Frame.htm
Asia (HongKong) : http://www.hitachi.com.hk/eng/bo/grp3/index.htm
Japan : http://www.hitachi.co.jp/Sicd/index.htm

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Electronic components Group
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Germany
Tel: <49> (89) 9 9180-0
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Tel: <44> (1628) 585000
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Tel: [phone]
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Taipei Branch Office
3F, Hung Kuo Building. No.167,
Tun-Hwa North Road, Taipei (105)
Tel: <886> (2) 2718-3666
Fax: <886> (2) 2718-8180

16

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Group III (Electronic Components)
7/F., North Tower, World Finance Centre,
Harbour City, Canton Road, Tsim Sha Tsui,
Kowloon, Hong Kong
Tel: <852> (2) 735 9218
Fax: <852> (2) 730 0281
Telex: 40815 HITEC HX

Copyright © Hitachi, Ltd., 1998. All rights reserved. Printed in Japan.

HM6264BI Series

Revision Record

Rev. Date Contents of Modification Drawn by Approved by

0.0 Dec. 1, 1995 Initial issue I. Ogiwara K. Yoshizaki

1.0 Sep. 5, 1996 Deletion of Preliminary I. Ogiwara K. Imato

2.0 Feb. 9, 1998 Change of subtitle

Change of FP-28DA

3.0 May. 8, 2000 Low VCC Data Retention Characteristics

Note 2: V

min = −0.3 V to

IL

10 µA max at Ta = –40 to + 40°C

I. Ogiwara K. Imato

17