Datasheet HM624100HCJP-10, HM624100HCLJP-10 Datasheet (HIT)

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Page 1

HM624100HC Series

4M High Speed SRAM (1-Mword × 4-bit)

ADE-203-1198 (Z)

Preliminary

Rev. 0.0

Nov. 30, 2000

Description

The HM624100HC is a 4-Mbit high speed static RAM organized 1-Mword × 4-bit. It has realized high speed access time by employing CMOS process (6-transistor memory cell) and high speed circuit designing technology. It is most appropriate for the application which requires high speed and high density memory, such as cache and buffer memory in system. The HM624100HC is packaged in 400-mil 32-pin SOJ for high density surface mounting.

Features

• Single 5.0 V supply : 5.0 V ± 10 %

• Access time 10 ns (max)

• Completely static memory  No clock or timing strobe required

• Equal access and cycle times

• Directly TTL compatible  All inputs and outputs

• Operating current : 140 mA (max)

• TTL standby current : 40 mA (max)

• CMOS standby ccurrent : 5 mA (max)

: 1.2 mA (max) (L-version)

• Data retension current : 0.8 mA (max) (L-version)

• Data retension voltage : 2.0 V (min) (L-version)

• Center VCC and VSS type pinout

Preliminary: The specification of this device are subject to change without notice. Please contact your nearest Hitachi’s Sales Dept. regarding specification.

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HM624100HC Series

Ordering Information

Type No. Access time Package

HM624100HCJP-10 10 ns 400-mil 32-pin plastic SOJ (CP-32DB) HM624100HCLJP-10 10 ns

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Pin Arrangement

HM624100HC Series

32-pin SOJ

A0 A1 A2 A3 A4

CS

I/O1

I/O2

WE

A5 A6 A7 A8 A9

Pin Description

Pin name Function

A0 to A19 Address input I/O1 to I/O4 Data input/output

CS Chip select OE Output enable WE Write enable

NC No connection

Power supply Ground

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

(Top view)

32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17

A19 A18 A17 A16 A15

I/O4 V

I/O3 A14 A13 A12 A11 A10 NC

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HM624100HC Series

Block Diagram

(LSB) A14 A13 A12

A5 A6

A7 A11 A10

(MSB)

Row

decoder

1024-row × 64-column ×

16-block × 4-bit (4,194,304 bits)

Internal voltage

generater

I/O1

. . .

I/O4

Input

data

control

Column I/O

Column decoder

A8 A9 A19 A17 A18 A15 A0 A2 A4 A16

(LSB)

(MSB)

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HM624100HC Series

Operation Table

CS OE WE Mode VCC current I/O Ref. cycle

H ××Standby I L H H Output disable I L L H Read I L H L Write I L L L Write I

, I

SB1

Note: ×: H or L

Absolute Maximum Ratings

Parameter Symbol Value Unit

Supply voltage relative to V Voltage on any pin relative to V

Power dissipation P Operating temperature Topr 0 to +70 °C Storage temperature Tstg –55 to +125 °C Storage temperature under bias Tbias –10 to +85 °C

Notes: 1. VT (min) = –2.0 V for pulse width (under shoot) 6 ns.

2. V

(max) = VCC + 2.0 V for pulse width (over shoot) 6 ns.

High-Z — High-Z — Dout Read cycle (1) to (3) Din Write cycle (1) Din Write cycle (2)

–0.5 to +7.0 V –0.5*1 to VCC+0.5*

1.0 W

Recommended DC Operating Conditions (Ta = 0 to +70°C)

Parameter Symbol Min Typ Max Unit

Supply voltage V

Input voltage V

VSS*

Notes: 1. VIL (min) = –2.0 V for pulse width (under shoot) 6 ns.

2. V

(max) = VCC + 2.0 V for pulse width (over shoot) 6 ns.

3. The supply voltage with all V

4. The supply voltage with all V

4.5 5.0 5.5 V 000V

2.2 — VCC + 0.5*

–0.5*

pins must be on the same level.

— 0.8 V

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HM624100HC Series

DC Characteristics (Ta = 0 to +70°C, VCC = 5.0 V ± 10 %, VSS = 0V)

Parameter Symbol Min Typ*

Input leakage current II

I — — 2 µA Vin = VSS to V

Max Unit Test conditions

Output leakage current IILOI — — 2 µA Vin = VSS to V Operation power supply current I

— — 140 mA Min cycle

CS = V

, lout = 0 mA

Other inputs = V

Standby power supply current I

— — 40 mA Min cycle, CS = VIH,

Other inputs = V

SB1

— TBD 5 mA f = 0 MHz

CS VCC - 0.2 V,

(1) 0 V Vin 0.2 V or (2) V

Vin VCC - 0.2 V

Output voltage V

—*

— — 0.4 V IOL = 8 mA

2.4 — — V IOH = –4 mA

TBD*21.2*

Notes: 1. Typical values are at VCC = 5.0 V, Ta = +25°C and not guaranteed.

2. This characteristics is guaranteed only for L-version.

Capacitance (Ta = +25°C, f = 1.0 MHz)

IH/VIL

Parameter Symbol Min Typ Max Unit Test conditions

Input capacitance*

Input/output capacitance*

Cin — — 6 pF Vin = 0 V

I/O

——8 pFV

= 0 V

I/O

Note: 1. This parameter is sampled and not 100% tested.

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HM624100HC Series

AC Characteristics (Ta = 0 to +70°C, VCC = 5.0 V ± 10 %, unless otherwise noted.)

Test Conditions

• Input pulse levels: 3.0 V/0.0 V

• Input rise and fall time: 3 ns

• Input and output timing reference levels: 1.5 V

• Output load: See figures (Including scope and jig)

CHZ

5 V

480Ω

5 pF

, t

WHZ

, and tOW)

OHZ

Dout

Zo=50 Ω

Output load (A)

1.5 V

RL=50 Ω

30 pF

(for t

Dout

CLZ

255Ω

Output load (B)

, t

OLZ

Read Cycle

HM624100HC

-10

Parameter Symbol Min Max Unit Notes

Read cycle time t Address access time t Chip select access time t Output enable to outpput valid t Output hold from address change t Chip select to output in low-Z t Output enable to output in low-Z t Chip deselect to output in high-Z t Output disable to output in high-Z t

ACS

CLZ

OLZ

CHZ

OHZ

10 — ns —10ns —10ns —5 ns 3—ns 3 — ns 1 0 — ns 1 — 5 ns 1 — 5 ns 1

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HM624100HC Series

Write Cycle

HM624100HC

-10

Parameter Symbol Min Max Unit Notes

Write cycle time t Address valid to end of write t Chip select to end of write t Write pulse width t Address setup time t Write recovery time t Data to write time overlap t Data hold from write time t Write disable to output in low-Z t Output disable to output in high-Z t Write enable to output in high-Z t

OHZ

WHZ

Note: 1. Transition is measured ±200 mV from steady voltage with Load (B). This parameter is sampled

and not 100% tested.

2. Address should be valid prior to or coincident with CS transition low.

3. WE and/or CS must be high during address transition time.

4. if CS and OE are low during this period, I/O pins are in the output state. Then, the data input signals of opposite phase to the outputs must not be applied to them.

5. If the CS low transition occurs simultaneously with the WE low transition or after the WE transition, output remains a high impedance state.

6. t

is measured from the latest address transition to the later of CS or WE going low.

7. t

is measured from the earlier of CS or WE going high to the first address transition.

8. A write occurs during the overlap of a low CS and a low WE. A write begins at the latest transition among CS going low and WE going low. A write ends at the earliest transition among CS going high and WE going high. t

9. t

is measured from the later of CS going low to the the end of write.

is measured from the beginnig of write to the end of write.

10 — ns 7—ns 7 — ns 9 7 — ns 8 0 — ns 6 0 — ns 7 5—ns 0—ns 3 — ns 1 — 5 ns 1 — 5 ns 1

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Timing Waveforms

Read Timing Waveform (1) (WE = VIH)

HM624100HC Series

Address

Valid address

ACS

OLZ

CLZ

Dout

High Impedance

Read Timing Waveform (2) (WE = VIH, CS = VIL, OE = VIL)

Address

Valid address

CHZ

OHZ

Valid data

Dout

Valid data

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HM624100HC Series

Read Timing Waveform (3) (WE = VIH, CS = VIL, OE = VIL)*

ACS

Dout

CLZ

High Impedance

Write Timing Waveform (1) (WE Controlled)

Address

Valid address

Valid data

CHZ

High Impedance

CS*

WE*

Dout

Din

OHZ

High impedance*

Valid data

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Write Timing Waveform (2) (CS Controlled)

HM624100HC Series

Address

CS *

WE *

Dout

Din

Valid address

WHZ

High impedance*

Valid data

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HM624100HC Series

Low VCC Data Retention Characteristics (Ta = 0 to +70°C)

This characteristics is guaranteed only for L-version.

Parameter Symbol Min Typ*1Max Unit Test conditions

for data retention V

Data retention current I

Chip deselect to data

CCDR

CDR

retention time Operation recovery time t

Note: 1. Typical values are at VCC = 3.0 V, Ta = +25˚C, and not guaranteed.

Low VCC Data Retention Timing Waveform

2.0 — — V VCC CS VCC – 0.2 V (1) 0 V Vin 0.2 V or (2) V

Vin VCC – 0.2 V

— TBD 800 µA VCC = 3 V, VCC CS VCC – 0.2 V

(1) 0 V Vin 0.2 V or (2) V

Vin VCC – 0.2 V

0 — — ns See retention waveform

5 ——ms

4.5 V

2.2 V V

0 V

CDR

Data retention mode

VCC ≥ CS ≥ VCC – 0.2 V

Page 13

Package Dimensions

HM624100HCJP/HCLJP Series (CP-32DB)

20.71

116

21.08 Max

0.74

10.16 ± 0.13

HM624100HC Series

Unit: mm

11.18 ± 0.13

1.30 Max

*0.43 ± 0.10

0.41 ± 0.08

0.10

*Dimension including the plating thickness

Base material dimension

1.27

3.50 ± 0.26

+0.25

–0.17

0.80

9.40 ± 0.25

Hitachi Code JEDEC EIAJ Mass

(reference value)

2.85 ± 0.12

CP-32DB Conforms Conforms

1.2 g

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HM624100HC Series

Cautions

1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document.

2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use.

3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However, contact Hitachi’s sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support.

4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product.

5. This product is not designed to be radiation resistant.

6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi.

7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor products.

Hitachi, Ltd.

Semiconductor & Integrated Circuits. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109

URL NorthAmerica : http://semiconductor.hitachi.com/

Europe : http://www.hitachi-eu.com/hel/ecg Asia : http://sicapac.hitachi-asia.com Japan : http://www.hitachi.co.jp/Sicd/indx.htm

For further information write to:

Hitachi Semiconductor (America) Inc. 179 East Tasman Drive, San Jose,CA 95134 Tel: <1> (408) 433-1990 Fax: <1>(408) 433-0223

Hitachi Europe GmbH Electronic Components Group Dornacher Straße 3 D-85622 Feldkirchen, Munich Germany Tel: <49> (89) 9 9180-0 Fax: <49> (89) 9 29 30 00

Hitachi Europe Ltd. Electronic Components Group. Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA, United Kingdom Tel: <44> (1628) 585000 Fax: <44> (1628) 585160

Hitachi Asia Ltd. Hitachi Tower 16 Collyer Quay #20-00, Singapore 049318 Tel : <65>-538-6533/538-8577 Fax : <65>-538-6933/538-3877

URL : http://www.hitachi.com.sg Hitachi Asia Ltd.

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