Page 1
HM5212325FBPC-B60
128M LVTTL interface SDRAM
100 MHz
1-Mword × 32-bit × 4-bank
PC/100 SDRAM
ADE-203-1122C (Z)
Rev. 1.0
May. 12 , 2000
Description
The Hitachi HM5212325FBPC is a 128-Mbit SDRAM organized as 1048576-word × 32-bit × 4-bank. All
inputs and outputs are referred to the rising edge of the clock input. It is packaged in standard 90-bump fine
pitch BGA.
Features
• Single chip wide bit solution (× 32)
• 3.3 V power supply
• Clock frequency: 100 MHz (max)
• LVTTL interface
• Extremely small foot print: 0.8 mm pitch
Package: FBGA (BP-90)
• 4 banks can operate simultaneously and independently
• Burst read/write operation and burst read/single write operation capability
• Programmable burst length: 4/8/full page
• 2 variations of burst sequence
Sequential (BL = 4/8/full page)
Interleave (BL = 4/8)
• Programmable CAS latency: 2/3
• Byte control by DQMB
• Refresh cycles: 4096 refresh cycles/64 ms
Page 2
HM5212325FBPC-B60
• 2 variations of refresh
Auto refresh
Self refresh
• Full page burst length capability
Sequential burst
Burst stop capability
Ordering Information
Type No. Frequency CAS latency Package
HM5212325FBPC-B60* 100 MHz 3 10 mm × 13 mm 90 bump FBGA (BP-90)
Note: 66 MHz operation at CAS latency = 2.
2
Page 3
Pin Arrangement
HM5212325FBPC-B60
90-bump FBGA
1 2 3
V
A
B
C
D
E
F
G
H
J
K
L
DQ15
SS
DQ13
DQ14
DQ11
DQ12
DQ9
DQ10
NC
DQ8
DQ
Open
MB1
NC CLK
CKE
A9
A6
DQ
A3
MB3
NC
DQ31
6 7 8
V
SS
V
CC
V
SS
V
CC
V
SS
NC
A8A11
A7A5
A4
V
SS
V
CC
V
SS
V
CC
V
SS
V
CC
NC
A12
A13 A10
A1 A2
V
CC
V
DQ0
DQ2 DQ1
NC
WECAS
CS RAS
NC
NC
CC
DQ3DQ4
DQ5DQ6
DQ7
DQ
MB0
NC
A0
DQ
MB2
DQ16
M
N
P
Q
DQ27
DQ25
V
SS
DQ28
DQ26
DQ24
CC
V
SS
V
CC
V
SS
V
DQ30
DQ29
V
SS
V
CC
V
SS
V
CC
DQ17 DQ18
DQ20
DQ19
DQ22DQ21
V
DQ23
CC
(Top view)
3
Page 4
HM5212325FBPC-B60
Pin Description
Pin name Function
A0 to A13 Address input
Row address A0 to A11
Column address A0 to A7
Bank select address A12/A13 (BS)
DQ0 to DQ31 Data-input/output
CS Chip select
RAS Row address strobe command
CAS Column address strobe command
WE Write enable
DQMB0 to DQMB3 Byte data mask*
CLK Clock input
CKE Clock enable
V
CC
V
SS
Open Open*
Power supply
Ground
2
Note: 1. DQMB0: DQ0 to DQ7
DQMB1: DQ8 to DQ15
DQMB2: DQ16 to DQ23
DQMB3: DQ24 to DQ31
2. Don’t connect. Internally connected with die.
1
4
Page 5
Block Diagram
HM5212325FBPC-B60
CS
RAS
CAS
WE
CLK
CKE
14
32
64-Mbit SDRAM
4M × 16
2
4
16
A0 to A13
DQMB 0 to
DQMB 3
DQ 0 to DQ 31
Power-up Sequence and Initialization Sequence
Power up sequence
64-Mbit SDRAM
4M × 16
216
Initialization sequence
V
CC
CKE, DQMB
CLK
CS, DQ
0 V
Low
Low
Low
Power stabilize
100 µs
200 µs
5
Page 6
HM5212325FBPC-B60
Absolute Maximum Ratings
Parameter Symbol Value Unit Note
Voltage on any pin relative to V
Supply voltage relative to V
SS
SS
V
T
V
CC
Short circuit output current Iout 50 mA
Operating temperature Topr 0 to +70 (Tj max = 110) °C
Storage temperature Tstg –55 to +125 °C
Note: 1. Respect to VSS.
DC Operating Conditions (Tcase = 0 to +70°C [Tj max = 110°C])
Parameter Symbol Min Max Unit Notes
Supply voltage V
Input high voltage V
Input low voltage V
Notes: 1. All voltage referred to VSS.
2. The supply voltage with all V
3. The supply voltage with all V
4. V
(max) = VCC + 2.0 V for pulse width ≤ 3 ns at VCC.
IH
5. V
(min) = VSS – 2.0 V for pulse width ≤ 3 ns at VSS.
IL
CC
V
SS
IH
IL
pins must be on the same level.
CC
pins must be on the same level.
SS
–0.5 to VCC + 0.5
V1
(≤ 4.6 (max))
–0.5 to +4.6 V 1
3.0 3.6 V 1, 2
00 V3
2.0 VCC + 0.3 V 1, 4
–0.3 0.8 V 1, 5
6
Page 7
HM5212325FBPC-B60
DC Characteristics
(Tcase = 0 to +70°C [Tj max = 110°C]), VCC = 3.3 V ± 0.3 V, VSS = 0 V)
HM5212325F
-B60
Parameter Symbol Min Max Unit Test conditions Notes
Operating current
(CAS latency = 2) I
(CAS latency = 3) I
Standby current in power down I
Standby current in power down
(input signal stable)
Standby current in non power
down
Standby current in non power
down (input signal stable)
Active standby current in power
down
Active standby current in power
down (input signal stable)
Active standby current in non
power down
Active standby current in non
power down (input signal stable)
Burst operating current
(CAS latency = 2) I
(CAS latency = 3) I
Refresh current I
Self refresh current I
Self refresh current (L-version) I
Input leakage current I
Output leakage current I
Output high voltage V
Output low voltage V
CC1
CC1
CC2P
I
CC2PS
I
CC2N
I
CC2NS
I
CC3P
I
CC3PS
I
CC3N
I
CC3NS
CC4
CC4
CC5
CC6
CC6
LI
LO
— 100 mA
— 110 mA
— 6 mA CKE = VIL,
— 4 mA CKE = VIL, tCK = ∞ 7
— 32 mA CKE, CS = VIH,
— 18 mA CKE = VIH, tCK = ∞ 9
— 8 mA CKE = VIL,
— 6 mA CKE = VIL, tCK = ∞ 2, 7
— 40 mA CKE, CS = VIH,
— 30 mA CKE = VIH, tCK = ∞ 2, 9
— 110 mA tCK = min, BL = 4 1, 2, 5
— 135 mA
— 190 mA tRC = min 3
— 2 mA VIH ≥ VCC – 0.2 V
— 0.8 mA
–2 2 µA0 ≤ Vin ≤ V
–3 3 µA0 ≤ Vout ≤ V
OH
OL
2.4 — V IOH = –4 mA
— 0.4 V IOL = 4 mA
Burst length = 1
tRC = min
t
= 12 ns
CK
t
= 12 ns
CK
t
= 12 ns
CK
t
= 12 ns
CK
V
≤ 0.2 V
IL
CC
CC
DQ = disable
1, 2, 3
6
4
1, 2, 6
1, 2, 4
8
7
Page 8
HM5212325FBPC-B60
Notes: 1. ICC depends on output load condition when the device is selected. ICC (max) is specified at the
output open condition.
2. One bank operation.
3. Input signals are changed once per one clock.
4. Input signals are changed once per two clocks.
5. Input signals are changed once per four clocks.
6. After power down mode, CLK operating current.
7. After power down mode, no CLK operating current.
8. After self refresh mode set, self refresh current.
9. Input signals are V
Capacitance (Ta = 25°C, VCC = 3.3 V ± 0.3 V)
Parameter Symbol Min Max Unit Notes
Input capacitance (CLK) C
Input capacitance
(Input except DQM)
Input capacitance (DQM) C
Output capacitance (DQ) C
Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method.
2. Measurement condition: f = 1 MHz, 1.4 V bias, 200 mV swing.
3. DQMB = V
4. This parameter is sampled and not 100% tested.
to disable Dout.
IH
or VIL fixed.
IH
I1
C
I2
I3
O
4 8 pF 1, 2, 4
4 8 pF 1, 2, 4
2 5 pF 1, 2, 4
2 5 pF 1, 2, 3, 4
8
Page 9
HM5212325FBPC-B60
AC Characteristics
(Tcase = 0 to +70°C [Tj max = 110°C]), VCC = 3.3 V ± 0.3 V, VSS = 0 V)
HM5212325F
-B60
HITACHI
Parameter
Symbol
System clock cycle time
(CAS latency = 2) t
(CAS latency = 3) t
CLK high pulse width t
CLK low pulse width t
CK
CK
CKH
CKL
Access time from CLK
(CAS latency = 2) t
(CAS latency = 3) t
Data-out hold time t
CLK to Data-out low impedance t
CLK to Data-out high impedance t
AC
AC
OH
LZ
HZ
Input setup time tAS, tCS, tDS,
t
CES
CKE setup time for power down
t
CESP
exit
Input hold time tAH, tCH, tDH,
t
CEH
Ref/Active to Ref/Active command
t
RC
period
Active to Precharge command
t
RAS
period
Active command to column
t
RCD
command (same bank)
Precharge to active command
t
RP
period
Write recovery or data-in to
t
DPL
precharge lead time
Active (a) to Active (b) command
t
RRD
period
Transition time (rise and fall) t
Refresh period t
T
REF
PC/100
Symbol Min Max Unit Notes
Tclk 15 — ns
Tclk 10 — ns
Tch 3 — ns 1
Tcl 3 — ns 1
Tac — 8 ns
Tac — 6 ns
Toh 3 — ns 1, 2
2 — ns 1, 2, 3
— 6 ns 1, 4
Tsi 2 — ns 1, 5, 6
Tpde 2 — ns 1
Thi 1 — ns 1, 5
Trc 70 — ns 1
Tras 50 120000 ns 1
Trcd 20 — ns 1
Trp 20 — ns 1
Tdpl 10 — ns 1
Trrd 20 — ns 1
15ns
—64ms
1
1, 2
9
Page 10
HM5212325FBPC-B60
Notes: 1. AC measurement assumes tT = 1 ns. Reference level for timing of input signals is 1.5 V.
2. Access time is measured at 1.5 V. Load condition is CL = 50 pF.
(min) defines the time at which the outputs achieves the low impedance state.
3. t
LZ
4. t
(max) defines the time at which the outputs achieves the high impedance state.
HZ
5. t
define CKE setup time to CLK rising edge except power down exit command.
CES
6. t
Test Conditions
• Input and output timing reference levels: 1.5 V
• Input waveform and output load: See following figures
: Address, tCS/tCH: CS, RAS, CAS, WE, DQM.
AS/tAH
t
DS/tDH
: Data-in, t
CES/tCEH
: CKE
input
2.4 V
0.4 V
2.0 V
0.8 V
I/O
CL
t
T
t
T
10
Page 11
Package Dimensions
HM5212325FBPC (BP-90)
B
C
0.20
Index
10.0
0.15
4×
0.20
HM5212325FBPC-B60
Unit: mm
A
0.8
A
C
-C-
C
0.20
11.2
C
A
0.8
B
13.0
+ 0.04
0.41 – 0.16
9.8 ± 0.10
1.45 Max
12.8 ± 0.10
Hitachi Code
JEDEC
EIAJ
Mass
0.12
90 × φ0.45 ± 0.05
φ0.08
M
(reference value)
2.4
5.6
C
AB
Details of the part A
BP-90
—
—
0.28 g
11
Page 12
HM5212325FBPC-B60
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent,
copyright, trademark, or other intellectual property rights for information contained in this document.
Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual
property rights, in connection with use of the information contained in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you have
received the latest product standards or specifications before final design, purchase or use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,
contact Hitachi’s sales office before using the product in an application that demands especially high
quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of
bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic,
safety equipment or medical equipment for life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for
maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and
other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the
guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or
failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the
equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage
due to operation of the Hitachi product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without
written approval from Hitachi.
7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor
products.
Hitachi, Ltd.
Semiconductor & Integrated Circuits.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109
URL NorthAmerica : http:semiconductor.hitachi.com/
For further information write to:
Hitachi Semiconductor
(America) Inc.
179 East Tasman Drive,
San Jose,CA 95134
Tel: <1> (408) 433-1990
Fax: <1>(408) 433-0223
Europe : http://www.hitachi-eu.com/hel/ecg
Asia (Singapore) : http://www.has.hitachi.com.sg/grp3/sicd/index.htm
Asia (Taiwan) : http://www.hitachi.com.tw/E/Product/SICD_Frame.htm
Asia (HongKong) : http://www.hitachi.com.hk/eng/bo/grp3/index.htm
Japan : http://www.hitachi.co.jp/Sicd/index.htm
Hitachi Europe GmbH
Electronic components Group
Dornacher Straße 3
D-85622 Feldkirchen, Munich
Germany
Tel: <49> (89) 9 9180-0
Fax: <49> (89) 9 29 30 00
Hitachi Europe Ltd.
Electronic Components Group.
Whitebrook Park
Lower Cookham Road
Maidenhead
Berkshire SL6 8YA, United Kingdom
Tel: <44> (1628) 585000
Fax: <44> (1628) 778322
Hitachi Asia Pte. Ltd.
16 Collyer Quay #20-00
Hitachi Tower
Singapore 049318
Tel: 535-2100
Fax: 535-1533
Hitachi Asia Ltd.
Taipei Branch Office
3F, Hung Kuo Building. No.167,
Tun-Hwa North Road, Taipei (105)
Tel: <886> (2) 2718-3666
Fax: <886> (2) 2718-8180
12
Hitachi Asia (Hong Kong) Ltd.
Group III (Electronic Components)
7/F., North Tower, World Finance Centre,
Harbour City, Canton Road, Tsim Sha Tsui,
Kowloon, Hong Kong
Tel: <852> (2) 735 9218
Fax: <852> (2) 730 0281
Telex: 40815 HITEC HX
Copyright © Hitachi, Ltd., 1998. All rights reserved. Printed in Japan.
Page 13
HM5212325FBPC-B60
Revision Record
Rev. Date Contents of Modification Drawn by Approved by
0.0 Oct. 25, 1999 Initial issue S. Hatano S. Hatano
0.1 Jan. 7, 2000 Correct errors of pin arrangement
Correct errors of DC Characteristics
: −4/4 to −2/2 µA
I
LI
I
: −6/6 to −3/3 µA
LO
Package dimension
Change tolerance value
0.2 Feb. 29, 2000 Capacitance
C
min: 5 pF to 4 pF
I1
C
min: 5 pF to 4 pF
I2
C
min: 2.5 pF to 2 pF
I3
C
min: 3 pF to 2 pF
O
1.0 May. 12 ,2000 Package dimension
Change of seated height
Y. Kagaya S. Hatano
M. Nishimura I. Hihara
13
Loading...