Page 1
HM5212325F-B60
128M LVTTL interface SDRAM
100 MHz
1-Mword × 32-bit × 4-bank
PC/100 SDRAM
ADE-203-1053A (Z)
Rev. 1.0
Oct. 18, 1999
Description
The Hitachi HM5212325F is a 128-Mbit SDRAM organized as 1048576-word × 32-bit × 4-bank. All inputs
and outputs are referred to the rising edge of the clock input. It is packaged in standard 108 bump BGA.
Features
• Single chip wide bit solution (× 32)
• 3.3 V power supply
• Clock frequency: 100 MHz (max)
• LVTTL interface
• Extremely small foot print: 1.27 mm pitch
Package: BGA (BP-108)
• 4 banks can operate simultaneously and independently
• Burst read/write operation and burst read/single write operation capability
• Programmable burst length: 4/8/full page
• 2 variations of burst sequence
Sequential (BL = 4/8/full page)
Interleave (BL = 4/8)
• Programmable CAS latency: 2/3
• Byte control by DQMB
• Refresh cycles: 4096 refresh cycles/64 ms
• 2 variations of refresh
Auto refresh
Self refresh
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HM5212325F-B60
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• Full page burst length capability
Sequential burst
Burst stop capability
Ordering Information
Type No. Frequency CAS latency Package
HM5212325FBP-B60* 100 MHz 3 14 mm × 22 mm 108 bump BGA (BP-108)
Note: 66 MHz operation at CAS latency = 2.
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HM5212325F-B60
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Pin Arrangement
(Top view)
108-bump BGA
A
B
C
D
E
F
G
H
J
K
L
M
N
R
T
P
U
1 2 3 4 5 6 7 8 9
DQ31
DQ30
DQ29
DQ28
DQ
MB3
CKE
A12
NC
NC
NC
NC
NC
V
CC
V
CC
A5
NC
NC
NC
NC DQ24
DQ25
DQ26
DQ27
DQ23
DQ22
DQ21
DQ20
NC
NC
NC
NC
NC
NC
NC
NC
NC
V
CC
DQ16
DQ17
DQ18
DQ19
WE
A13
A1
A7
V
SS
A2
A10
RAS
DQ
MB2
A3
A4
A6
V
SS
A0
A8
A11
V
SS
A9 CS
Open CLK V
CC
CAS
DQ
MB0
DQ
MB1
DQ3 NC NC DQ4 V
SS
DQ11 NC NC DQ12
DQ2 NC NC DQ5 V
CC
DQ10 NC NC DQ13
DQ1 NC NC DQ6 V
CC
DQ9 NC NC DQ14
DQ0 NC NC DQ7 V
SS
V
SS
V
CC
V
CC
V
SS
DQ8
NC NC DQ15
NC
NC
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HM5212325F-B60
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Pin Description
Pin name Function
A0 to A13 Address input
Row address A0 to A11
Column address A0 to A7
Bank select address A12/A13 (BS)
DQ0 to DQ31 Data-input/output
CS Chip select
RAS Row address strobe command
CAS Column address strobe command
WE Write enable
DQMB0 to DQMB3 Byte data mask*
1
CLK Clock input
CKE Clock enable
V
CC
Power supply
V
SS
Ground
Open Open*
2
Note: 1. DQMB0: DQ0 to DQ7
DQMB1: DQ8 to DQ15
DQMB2: DQ16 to DQ23
DQMB3: DQ24 to DQ31
2. Don’t connect. Internally connected with die.
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HM5212325F-B60
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Block Diagram
2
4
14
32
16
64-Mbit SDRAM
4M × 16
216
64-Mbit SDRAM
4M × 16
DQMB 0 to
DQMB 3
DQ 0 to DQ 31
A0 to A13
CS
RAS
CAS
WE
CLK
CKE
Power-up Sequence and Initialization Sequence
V
CC
Power up sequence
Initialization sequence
100 µs
0 V
Low
Low
Low
CKE, DQMB
CLK
CS, DQ
200 µs
Power stabilize
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HM5212325F-B60
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Absolute Maximum Ratings
Parameter Symbol Value Unit Note
Voltage on any pin relative to V
SS
V
T
–0.5 to VCC + 0.5
(≤ 4.6 (max))
V1
Supply voltage relative to V
SS
V
CC
–0.5 to +4.6 V 1
Short circuit output current Iout 50 mA
Operating temperature Topr 0 to +70 (Tj max = 110) °C
Storage temperature Tstg –55 to +125 °C
Note: 1. Respect to VSS.
DC Operating Conditions (Tcase = 0 to +70°C [Tj max = 110°C])
Parameter Symbol Min Max Unit Notes
Supply voltage V
CC
3.0 3.6 V 1, 2
V
SS
00 V3
Input high voltage V
IH
2.0 VCC + 0.3 V 1, 4
Input low voltage V
IL
–0.3 0.8 V 1, 5
Notes: 1. All voltage referred to VSS.
2. The supply voltage with all V
CC
pins must be on the same level.
3. The supply voltage with all V
SS
pins must be on the same level.
4. V
IH
(max) = VCC + 2.0 V for pulse width ≤ 3 ns at VCC.
5. V
IL
(min) = VSS – 2.0 V for pulse width ≤ 3 ns at VSS.
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HM5212325F-B60
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DC Characteristics
(Tcase = 0 to +70°C [Tj max = 110°C]), VCC = 3.3 V ± 0.3 V, VSS = 0 V)
HM5212325F
-B60
Parameter Symbol Min Max Unit Test conditions Notes
Operating current
(CAS latency = 2) I
CC1
— 100 mA
Burst length = 1
tRC = min
1, 2, 3
(CAS latency = 3) I
CC1
— 110 mA
Standby current in power down I
CC2P
— 6 mA CKE = VIL,
t
CK
= 12 ns
6
Standby current in power down
(input signal stable)
I
CC2PS
— 4 mA CKE = VIL, tCK = ∞ 7
Standby current in non power
down
I
CC2N
— 32 mA CKE, CS = VIH,
t
CK
= 12 ns
4
Standby current in non power
down (input signal stable)
I
CC2NS
— 18 mA CKE = VIH, tCK = ∞ 9
Active standby current in power
down
I
CC3P
— 8 mA CKE = VIL,
t
CK
= 12 ns
1, 2, 6
Active standby current in power
down (input signal stable)
I
CC3PS
— 6 mA CKE = VIL, tCK = ∞ 2, 7
Active standby current in non
power down
I
CC3N
— 40 mA CKE, CS = VIH,
t
CK
= 12 ns
1, 2, 4
Active standby current in non
power down (input signal stable)
I
CC3NS
— 30 mA CKE = VIH, tCK = ∞ 2, 9
Burst operating current
(CAS latency = 2) I
CC4
— 110 mA tCK = min, BL = 4 1, 2, 5
(CAS latency = 3) I
CC4
— 135 mA
Refresh current I
CC5
— 190 mA tRC = min 3
Self refresh current I
CC6
— 2 mA VIH ≥ VCC – 0.2 V
V
IL
≤ 0.2 V
8
Self refresh current (L-version) I
CC6
— 0.8 mA
Input leakage current I
LI
–4 4 µA0 ≤ Vin ≤ V
CC
Output leakage current I
LO
–6 6 µA0 ≤ Vout ≤ V
CC
DQ = disable
Output high voltage V
OH
2.4 — V IOH = –4 mA
Output low voltage V
OL
— 0.4 V IOL = 4 mA
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HM5212325F-B60
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Notes: 1. ICC depends on output load condition when the device is selected. ICC (max) is specified at the
output open condition.
2. One bank operation.
3. Input signals are changed once per one clock.
4. Input signals are changed once per two clocks.
5. Input signals are changed once per four clocks.
6. After power down mode, CLK operating current.
7. After power down mode, no CLK operating current.
8. After self refresh mode set, self refresh current.
9. Input signals are V
IH
or VIL fixed.
Capacitance (Ta = 25°C, VCC = 3.3 V ± 0.3 V)
Parameter Symbol Min Max Unit Notes
Input capacitance (CLK) C
I1
5 8 pF 1, 2, 4
Input capacitance
(Input except DQM)
C
I2
5 8 pF 1, 2, 4
Input capacitance (DQM) C
I3
2.5 5 pF 1, 2, 4
Output capacitance (DQ) C
O
3 5 pF 1, 2, 3, 4
Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method.
2. Measurement condition: f = 1 MHz, 1.4 V bias, 200 mV swing.
3. DQMB = V
IH
to disable Dout.
4. This parameter is sampled and not 100% tested.
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HM5212325F-B60
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AC Characteristics
(Tcase = 0 to +70°C [Tj max = 110°C]), VCC = 3.3 V ± 0.3 V, VSS = 0 V)
HM5212325F
-B60
Parameter
HITACHI
Symbol
PC/100
Symbol Min Max Unit Notes
System clock cycle time
(CAS latency = 2) t
CK
Tclk 15 — ns
1
(CAS latency = 3) t
CK
Tclk 10 — ns
CLK high pulse width t
CKH
Tch 3 — ns 1
CLK low pulse width t
CKL
Tcl 3 — ns 1
Access time from CLK
(CAS latency = 2) t
AC
Tac — 8 ns
1, 2
(CAS latency = 3) t
AC
Tac — 6 ns
Data-out hold time t
OH
Toh 3 — ns 1, 2
CLK to Data-out low impedance t
LZ
2 — ns 1, 2, 3
CLK to Data-out high impedance t
HZ
— 6 ns 1, 4
Input setup time tAS, tCS, tDS,
t
CES
Tsi 2 — ns 1, 5, 6
CKE setup time for power down
exit
t
CESP
Tpde 2 — ns 1
Input hold time tAH, tCH, tDH,
t
CEH
Thi 1 — ns 1, 5
Ref/Active to Ref/Active command
period
t
RC
Trc 70 — ns 1
Active to Precharge command
period
t
RAS
Tras 50 120000 ns 1
Active command to column
command (same bank)
t
RCD
Trcd 20 — ns 1
Precharge to active command
period
t
RP
Trp 20 — ns 1
Write recovery or data-in to
precharge lead time
t
DPL
Tdpl 10 — ns 1
Active (a) to Active (b) command
period
t
RRD
Trrd 20 — ns 1
Transition time (rise and fall) t
T
15ns
Refresh period t
REF
—64ms
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HM5212325F-B60
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Notes: 1. AC measurement assumes tT = 1 ns. Reference level for timing of input signals is 1.5 V.
2. Access time is measured at 1.5 V. Load condition is CL = 50 pF.
3. t
LZ
(min) defines the time at which the outputs achieves the low impedance state.
4. t
HZ
(max) defines the time at which the outputs achieves the high impedance state.
5. t
CES
define CKE setup time to CLK rising edge except power down exit command.
6. t
AS/tAH
: Address, tCS/tCH: CS, RAS, CAS, WE, DQM.
t
DS/tDH
: Data-in, t
CES/tCEH
: CKE
Test Conditions
• Input and output timing reference levels: 1.5 V
• Input waveform and output load: See following figures
t
T
2.4 V
0.4 V
0.8 V
2.0 V
input
t
T
I/O
CL
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HM5212325F-B60
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Package Dimensions
HM5212325FBP Series (BP-108)
Hitachi Code
JEDEC
EIAJ
Weight
(reference value)
BP-108
—
—
1.2 g
-A-
-B-
-C-
14.00
22.00
0.35
0.15
4×C1.2
Pin 1 Index
C
φ0.30
C
φ0.15
AB
13.0 ± 0.10
0.60
2.10
2.35 Max
C
C
0.20
1.27
21.0 ± 0.10
A
4×
108× φ0.75
Details of the part A
M
M
Unit: mm
123456798
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
1.27
Preliminary
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HM5212325F-B60
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Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent,
copyright, trademark, or other intellectual property rights for information contained in this document.
Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual
property rights, in connection with use of the information contained in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you have
received the latest product standards or specifications before final design, purchase or use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,
contact Hitachi’s sales office before using the product in an application that demands especially high
quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of
bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic,
safety equipment or medical equipment for life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for
maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and
other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the
guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or
failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the
equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage
due to operation of the Hitachi product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without
written approval from Hitachi.
7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor
products.
Hitachi, Ltd.
Semiconductor & Integrated Circuits.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109
Copyright © Hitachi, Ltd., 1998. All rights reserved. Printed in Japan.
Hitachi Asia Pte. Ltd.
16 Collyer Quay #20-00
Hitachi Tower
Singapore 049318
Tel: 535-2100
Fax: 535-1533
URL NorthAmerica : http:semiconductor.hitachi.com/
Europe : http://www.hitachi-eu.com/hel/ecg
Asia (Singapore) : http://www.has.hitachi.com.sg/grp3/sicd/index.htm
Asia (Taiwan) : http://www.hitachi.com.tw/E/Product/SICD_Frame.htm
Asia (HongKong) : http://www.hitachi.com.hk/eng/bo/grp3/index.htm
Japan : http://www.hitachi.co.jp/Sicd/indx.htm
Hitachi Asia Ltd.
Taipei Branch Office
3F, Hung Kuo Building. No.167,
Tun-Hwa North Road, Taipei (105)
Tel: <886> (2) 2718-3666
Fax: <886> (2) 2718-8180
Hitachi Asia (Hong Kong) Ltd.
Group III (Electronic Components)
7/F., North Tower, World Finance Centre,
Harbour City, Canton Road, Tsim Sha Tsui,
Kowloon, Hong Kong
Tel: <852> (2) 735 9218
Fax: <852> (2) 730 0281
Telex: 40815 HITEC HX
Hitachi Europe Ltd.
Electronic Components Group.
Whitebrook Park
Lower Cookham Road
Maidenhead
Berkshire SL6 8YA, United Kingdom
Tel: <44> (1628) 585000
Fax: <44> (1628) 778322
Hitachi Europe GmbH
Electronic components Group
Dornacher Straße 3
D-85622 Feldkirchen, Munich
Germany
Tel: <49> (89) 9 9180-0
Fax: <49> (89) 9 29 30 00
Hitachi Semiconductor
(America) Inc.
179 East Tasman Drive,
San Jose,CA 95134
Tel: <1> (408) 433-1990
Fax: <1>(408) 433-0223
For further information write to:
Page 13
HM5212325F-B60
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Revision Record
Rev. Date Contents of Modification Drawn by Approved by
0.0 May. 12, 1999 Initial issue S. Hatano S. Hatano
1.0 Oct. 18, 1999 Programmable CAS latency: 3 to 2/3
Ordering information
Addition of note
Pin description
Addition of note 1
DC Characteristics
I
CC1
max (CL = 3): 150 mA to 110 mA
I
CC4
max (CL = 3): 180 mA to 135 mA
I
CC5
max: 230 mA to 190 mA
Addition of I
CC1
max (CL = 2): 100 mA
Addition of I
CC4
max (CL = 2): 110 mA
Capacitance
C
I2
max: 10 pF to 8 pF
C
I3
max: 6 pF to 5 pF
C
O
min: 4 pF to 3 pF
C
O
max: 6.5 pF to 5 pF
AC Characteristics
Addition of t
CK
min (CL = 2): 15 ns
Addition of t
AC
max (CL = 2): 8 ns
Package dimension
Change tolerance of height
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